Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
  • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
  • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
  • H01L27/118—Masterslice integrated circuits
  • H01L27/11803—Masterslice integrated circuits using field effect technology
  • H01L27/11807—CMOS gate arrays

Definitions

• the disclosed invention generally relates to configurable gate arrays (CGA's), and is particularly directed to a configurable gate array which utilizes hierarchical cluster levels.
• Custom integrated circuits typically involve expensive custom design to provide a one-of-a-kind integrated circuit for specific functions- While extremely costly to design, such custom integrated circuits are typically intended for large quantity produc ⁇ tion.
• a semicustom integrated circuit generally utilizes a "standardized" integrated circuit chip which includes a plurality of individual circuit elements arranged * . ' in arrays. The integrated circuit chip is then adapted to provide desired electrical functions by selectively interconnecting the circuit elements. For example, such interconnections may be accomplished by appropriate metalization processing.
• a "standardized" integrated circuit chip is basically a foundation on which the desired logic functions are achieved by selective interconnections of the circuit elements..
• One form of semicustom logic design and manufacture is based on integrated circuit gate arrays produced by different companies.
• an integrated circuit gate array includes a plurality of individual logic gates arranged in arrays which typically are not interconnected. The desired logic functions are then achieved by selective interconnection of the inputs and outputs of the gates. As the number of gates in a gate array increases, i.e., as gate density increases, interconnection routing rapidly becomes more complex and difficult. As a result of interconnection difficulties the gate utilization factor, i.e., the percentage of gates actually utilized, decreases.
• Another object of the invention is to provide an improved configurable gate array wherein the areas of the interconnect regions are minimized.
• Still another object of the invention is to provide a hierarchical configurable gate array which includes increasingly larger gate cluster levels, and wherein the area of interconnect regions for the interconnection between clusters of the same level increase as the level increases.
• a further object of the invention is to provide a hierarchical configurable gate array wherein a given gate cluster level forms a component of the next higher gate cluster level.
• Another object of the invention is to provide a hierarchical configurable gate array having cluster levels of respectively increasing numbers of gates, and wherein the respective areas of the interconnect regions are determined as a function of the respective levels of interconnection.
• Still another object of the invention is to provide a hierarchical configurable gate array having cluster levels wherein each level can assume the identity of a component having inputs and outputs.
• a configurable gate array having a first level cluster comprising N multi-terminal circuit components, wherein each component provides a canonical function and N is an integer; a second level cluster comprising N first level clusters; and further level clusters wherein each level cluster includes N clusters of the next lower level.
• Each of the N circuit components or clusters is an element of its respective level cluster, and interconnect regions are provided for interconnection between the N elements of a level cluster. The respective areas or sizes of such interconnect regions depend on the cluster level formed by the elements to be interconnected within each cluster. Selected input or output ports for each element are available at more than one location for interconnection between the elements of such cluster.
• Figure 1 is a top plan schematic view illustrating the first level cluster of the disclosed hierarchical configurable gate array, the elements forming the first level cluster, and the interconnect region for the elements.
• Figure 2 is a schematic diagram of a NAND gate which by way of example can be an element of the first cluster level of Figure 1.
• Figure 3 is a schematic diagram of a NOR gate which by way of example can be an element of the first cluster level of Figure 1.
• Figure 4 is a top plan schematic view of the second level cluster of the disclosed hierarchical configurable gate array, the elements forming the second level cluster, and the interconnect region for the elements.
• Figure 5 is a top plan schematic view of the fourth level cluster of the disclosed hierarchical configurable gate array and the third level cluster which form the elements of the fourth level cluster.
• the level 1 cluster includes four (4) elements 11 distributed about a cruciform shaped interconnect region 13. The width across each area of the cruciform is identified as "D."
• Each of the level 1 cluster elements 11 is a multi-terminal circuit- component which provides a canonical function. Examples of such multi-terminal circuit components include NAND gates and NOR gates.
• Each of the level 1 cluster elements 11 may be different components. However, for ease of reference, the level 1 cluster elements 11 will be generally discussed as being identical and will also be generally discussed as gates.
• the X and Y axes adjacent the level 1 cluster 10 identify reference directions which will be utilized in the description of the level 1 cluster 10 as well as all other clusters of different levels.
• the cruciform shaped interconnect region 13 of the level 1 cluster 10 and the interconnect, regions described below have arms extending in the X and Y directions.
• the disclosed configurable gate array utilizes complementary metal-oxide semiconductor (CMOS) technology.
• Figure 2 illustrates a typical NAND gate in CMOS form.
• Figure 3 illustrates a typical NOR gate in CMOS form.
• IIL integrated injection logic
• ECL emitter coupled logic
• NMOS N-channel MOS
• each level 1 element 11 is schematically shown by elongated input/output ( I/ ⁇ ) contacts which are identified in conformity with Figures 2 and 3. Specifically, VQD identifies the contact for the supply voltage V _,_ j GROUND identifies the ground contact; A and B identify the gate inputs; and OUT identifies the gate output.
• I/ ⁇ input/output
• Each element 11 is regarded as having- four sides defined by the ends of the elongated I/ ⁇ contacts identifed previously. Such four sides form the periphery of each respective element 11.
• the elongated I/ ⁇ contacts of the level 1 elements 11 illustrate the principle of "multiporting" as utilized in the invention. Each I/ ⁇ contact on a particular side of a level 1 element 11 is available on the opposite side. Thus, each I/ ⁇ contact of each level 1 element 11 is accessible on the level 1 interconnect region 13.
• the level 1 cluster 10 also has a periphery formed by the four sides defined by the_ outermost contacts. Since the level 1 cluster is an element of the level 2 cluster (discussed below) , each I/O contact of the level 1 cluster that is to be connected to another cluster is preferably available on two sides, and preferably on opposite sides. The same multiporting principle is applied to higher cluster levels. 6a
• Multiporting achieves the accessiblity of each contact or function on two sides of the cluster element region, and also forces connections between clusters of the same level to originate at the periphery of each cluster. While accessiblity of 1/0's on opposite sides of
• each cluster is like a "black box" for providing functins which are accessible at the multiported I/ ⁇ contacts located about its periphery.
• Multiporting in the level 1 and higher clusters is achieved by appropriate interconnection between elements of each cluster. For various design reasons, multiporting may not always be feasible or practical or beneficial. Accordingly, the requirement of multiporting can be relaxed to some degree by determining in the actual application design process which I/ ⁇ 's for each cluster do not require the accessibility provided by multiporting. Any requirement of multiporting referred to herein is subject to this qualification.
• FIG 4 shown therein is a top plan schematic view of a level 2 cluster 20 which includes as its elements four (4) level 1 clusters 10 distributed about a cruciform shaped level 2 interconnect region 15.
• the I/ ⁇ contacts of the level 2 cluster are located about the periphery of the level 2 cluster region and are multiported.
• the interconnects between the level 2 elements must be located within the level 2 interconnect region 15.
• Each level 3 cluster 30 includes four (4) level 2 clusters 20 as elements, and also includes a cruciform shaped level 3 interconnect region 17. As with the previously discussed level 1 and level 2 clusters, all interconnections between the level 3 cluster 30 elements (i.e., four level 2 clusters) must be located within the interconnect region 17 of the level 3 cluster 30. Also, as with the previously discussed level 1 and level 2 clusters, the I/ ⁇ contacts of the level 3 cluster 30 are located around the periphery of the region occupied by the level 3 cluster, and such level 3 cluster I/ ⁇ contacts are multiported.
• a level 4 cluster 40 includes as its elements four (4) level 3 clusters 30, and also includes a cruciform shaped level 4 interconnect region- 19. All interconnections between the level 4 elements (i.e., four (4) level 3 clusters 30) must be located within the interconnect region 19 of the level 4 cluster 40.
• the I/ ⁇ contacts for the level 4 cluster 40 are located around the periphery of the region occupied by the level 4 cluster 40, and such level 4 cluster I/ ⁇ contacts are multiported.
• each higher level cluster includes four elements, each element being ' .-a preceding level cluster.
• the elements of each cluster are arranged around a cruciform shaped interconnect area, and all interconnectins between the four elements of a cluster must be made within the interconnection area.
• the I/ ⁇ contacts for each level cluster are located about the periphery of the region occupied by such cluster, and the contacts are multiported.
• the foregoing principles for cluster organization are quite rigid, but provide for a truly hierarchical structure.
• Each level cluster is forced to have specific characteristics which enables it to be utilized as an element of the next higher level.
• a level 2 cluster 20 could include sixteen (16) gates (since each level 1 cluster 10 could include four
• a level 3 cluster 30 would include four (4) primitive cells and, therefore, sixty-four (64) gates.
• a level 3 cluster 30 could provide functions generally associated with medium-scale integrated (MSI) circuits, including, registers, arithmetic logic units (ALU's), and adders.
• MSI medium-scale integrated
• each cluster can . be regarded as a separate component for providing electrical function which are availabe at the I/ ⁇ contacts distributed about its periphery. As higher order logic functions are required, higher level clusters are utilized.
• each cluster has its I/ ⁇ contacts distributed about the region occupied by such cluster.
• each cluster has associated, conductor tracks in its interconnect region which are solely for interconnecting the elements of such cluster.
• the number of tracks in the respective interconnect regions will depend on the number of I/ ⁇ contacts that exit on the interconnect region. By way of example, it has been determined as a "rule of thumb" that the number of tracks in each direction (X and Y) is equal to the number of I/ ⁇ contacts that exit from one element to the interconnect region. Assuming complete multiporting, the number of tracks in a given direction (X or Y) is equal to the number of distinct I/ ⁇ functions for one element.
• each side of a cluster element has the same number of I/ ⁇ contacts. Therefore, the number of tracks are the same in both X and Y directions for a given interconnect region. To the extent that one side of an element may have more or less I/ ⁇ contacts than an another side, the number of tracks in a given direction and adjacent such side of the element may be reduced or increased, respectively.
• the number of distinct I/ ⁇ functions for a given cluster element can be determined by design, empirically or by reference to known mathematical models which provide "gate-to-pin" calculations.
• the number of tracks directly affects the width D of each interconnect region, as does the center-to-center spacing W of the tracks.
• the area A of the interconnect region is as follows:
• the width D of an interconnect region is calculated in accordance with Equation 1 by substituting the number of tracks for N in such equation. After the width D is determined, then the area A can be evaluated in accordance with Equation 2.
• each cluster includes four elements that are interconnected in an interconnect region that is within the four-sided region occupied by the cluster, and further includes I/ ⁇ contacts which are distributed about its periphery. Some or all of the I/ ⁇ contacts are multiported, by which such multiported contacts are available on more than one side of the cluster.
• each cluster can be considered a component which provides electrical functions as defined by the interconnections of the elements of the cluster. Further, prior to interconnection all clusters of the same level are identical and -therefore allow design flexiblity as to the placement of defined I/ ⁇ functions.
• the described hierarchical structure is independent of the process technology utilized and requires only the provision of the two metalization layers for the X and Y tracks for the interconnect regions.
• the areas of such interconnect regions are minimized by having element-to-element interconnections contained within the cluster region and having multiported I/ ⁇ contacts distributed about the periphery of the cluster region.

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• 1985
  • 1985-05-31 WO PCT/US1985/001019 patent/WO1986000468A1/en unknown
  • 1985-05-31 EP EP19850902909 patent/EP0188449A1/de not_active Withdrawn
  • 1985-05-31 JP JP50254085A patent/JPS61502574A/ja active Pending

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