EP0169030A2 - Datenverarbeitungsschaltung zur Hochgeschwindigkeitsberechnung von entweder einer Totalsumme oder eines Totalprodukts einer Reihe von Daten - Google Patents

Datenverarbeitungsschaltung zur Hochgeschwindigkeitsberechnung von entweder einer Totalsumme oder eines Totalprodukts einer Reihe von Daten Download PDF

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Publication number
EP0169030A2
EP0169030A2 EP85304956A EP85304956A EP0169030A2 EP 0169030 A2 EP0169030 A2 EP 0169030A2 EP 85304956 A EP85304956 A EP 85304956A EP 85304956 A EP85304956 A EP 85304956A EP 0169030 A2 EP0169030 A2 EP 0169030A2
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Prior art keywords
register
registers
data
processing circuit
data processing
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Ceased
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EP85304956A
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English (en)
French (fr)
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EP0169030A3 (de
Inventor
Kenji C/O Nec Corporation Hasegawa
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NEC Corp
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NEC Corp
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Publication of EP0169030A2 publication Critical patent/EP0169030A2/de
Publication of EP0169030A3 publication Critical patent/EP0169030A3/de
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
    • G06F7/5095—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators word-serial, i.e. with an accumulator-register
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only

Definitions

  • This invention relates to a data processing circuit for use in calculating either a total sum or a total product of a series of data.
  • the data processing circuit is used in carrying out calculation of a predetermined one of a total sum and a total product of a plurality of vector data or vector elements which are designated by a vector instruction.
  • a data processing circuit of the type described may comprise an operand producing section which is responsive to a series of data, such as vector elements, and which successively produces operands two of which will be called a first and a second operand, respectively.
  • the operand producing section is operable on a plurality of pipeline stages.
  • the pipeline stages are carried out under pipeline control of operation of the data processing circuit to carry out the total sum at a high speed.
  • An arithmetic unit successively carries out a local calculation of a local sum of the first and the second operands to produce a local or intermediate result representative of the local sum.
  • the intermediate result is successively delivered as the first operand through the pipeline stages while the data are delivered as the second operand through the pipeline stages.
  • the intermediate result related to one vector element and a next following vector element are synchronously delivered to the arithmetic unit as the first and the second operands, respectively. That is to say, supply of the next vector element to the operand producing section is postponed or delayed until the intermediate result is calculated by the arithmetic unit for the above-mentioned one vector element.
  • Such a delay time results in an undesiredly slow calculation speed of the data processing circuit.
  • the calculation speed of data processing circuit is inevitably reduced on calculating the total sum of the series of data.
  • a data processing circuit comprising calculation carrying out means responsive to a succession of data for carrying out a predetermined calculation iteratively on the data of the succession to provide intermediate results of calculation, a predetermined number of work registers for successively temporarily storing the results of calculation, and administrating means for administrating the work registers to cyclically transfer the intermediate results among the work registers and the calculation carrying out means in a pipeline fashion.
  • the data processing circuit 11 is for use in a data processing system which comprises a memory unit 12 coupled to the data processing circuit 11.
  • the memory unit 12 stores various instructions, such as vector instructions and scalar instructions, for carrying out a wide variety of calculations.
  • the memory unit 12 also stores data, such as vector elements, which should be calculated by the data processing circuit 11.
  • An instruction decoder (not shown) is operatively coupled to the data processing circuit 11 and the memory unit 12.
  • the instruction decoder is responsive to the instruction read out of the memory unit 12 and decodes the instruction to provide various command signals, such as an arithmetic command signal.
  • the arithmetic command signal indicates an arithmetic operation which should be carried out.
  • the data processing circuit 11 serves to carry out a predetermined calculation designated by the arithmetic command signal.
  • the predetermined calculation is carried out on a series of data which are successively read out of the memory unit 12 by the data processing circuit 11.
  • the data processing circuit 11 comprises an operand producing section 14 which is successively responsive to the data series and which produces first and second operands 16 and 17.
  • the operand producing section 14 comprises a first register 21 which is capable of storing data in accordance with a request of software to produce a first output signal representative of the data stored therein.
  • the operand,producing section 14 further comprises a second register 22 which is responsive to readout data from the memory unit 12 and which temporarily stores the readout data to produce a second output signal representative of the data stored therein.
  • a first selector 23 selects one of the first and the second output signals in response to the first and the second output signals to produce a first selected signal.
  • a second selector 24 is responsive to the first and the second output signals and selects one of the first and the second signals to produce a second selected signal. Responsive to the first selected signal, a third register 25 stores the first selected signal to produce the first operand 16 representative of the first selected signal stored therein. Likewise, a fourth register 26 is responsive to the second selected signal and stores the second selected signal to produce the second operand 17 representative of the second selected signal stored therein.
  • An arithmetic unit 28 is_responsive to the first and second operands 16 and 17 and the arithmetic command signal and successively carries out a local calculation of the predetermined calculation designated by the arithmetic command signal to calculate a selected one of a local sum and a local product of the first and the second operands and to produce an intermediate result representative of either the local sum or the local product.
  • the arithmetic unit 28 finally produces an ultimate result of the predetermined calculation.
  • the arithmetic unit 28 is operable as a calculation carrying out section which is responsive to a succession of data and which carries out a predetermined calculation iteratively on the data of the succession to provide intermediate results of calculation.
  • a fifth register 29 is capable of storing the ultimate result in accordance with the request of software to produce writing data which are representative of the ultimate result and which are to be memorized into the memory unit 12.
  • the ultimate result is stored either in the first register 21 or in the fifth register 29 in accordance with the request of software.
  • the data processing circuit 11 is operable in a pipeline fashion of first and second pipeline stages.
  • the first pipeline stage is carried out by the first and the second registers 21 and 22.
  • the second pipeline stage is dealt with by the third and the fourth registers 25 and 26.
  • Such a plurality of pipeline stages are for carrying out the predetermined calculation at a high speed.
  • one machine cycle is necessary in storing a content of either the first register 21 or the second register 22 into either the third register 25 or the fourth register 26 through either the first selector 23 or the second selector 24.
  • another machine cycle is,indispensable on carrying out the local calculation on contents of the third and the fourth registers 25 and 26 in the arithmetic unit 28 and in storing the local or intermediate result into either the first register 21 or the fifth register 29.
  • the content of the first register 21 will be represented by R.
  • Vector elements having different suffixes are stored into the memomry unit 12 with different addresses of the memory unit 12 assigned thereto.
  • a scalar instruction is an instruction to be executed. It will be assumed that the scalar instruction has a sequence of partial instructions as follows.
  • the initial value R and a first scalar data V 1 are stored in the first and the second registers 21 and 22, respectively.
  • the initial value R and the first scalar data V 1 are stored in the third and the fourth registers 25 and 26, respectively.
  • the initial value R and a second scalar data V 2 are stored in the first and the second registers 21 and 22, respectively.
  • a first sum of the initial value R and the first scalar data V l is calculated by the arithmetic unit 28 and is stored in the fifth register 29.
  • the initial value R and the second scalar data V 2 are stored in the third and the fourth registers 25 and 26, respectively.
  • the initial value R and a third scalar data V 3 are stored in the first and the second registers 21 and 22, respectively.
  • a second sum of the initial value R and the second scalar data V 2 is stored in the fifth register 29 like in the third machine cycle 3T.
  • each of first through n-th sums is sequentially stored in the fifth register 29. That,is to say, it is possible to define an execution cycle of each partial instruction as one machine cycle. In other words, it is possible to execute the scalar instruction under pipeline control of operation of the data processing circuit 11 at a high speed.
  • the vector instruction is an instruction which is for calculating a total sum of a plurality of vector elements, n in number, and is for storing the total sum in either the first register 21 or the fifth register 29. That is to say, the vector instruction is represented by Formula (1) hereunder:
  • the vector instruction has a sequence of arithmetic steps as follows. where R represents an initial value. In Fig. 3, a machine cycle is again represented by T. Data flows used in execution of the first through the n-th steps are indicated by numerals 1 through n, respectively.
  • a first machine cycle 1T the initial value R and a first vector element V 1 are. stored in the first and the second registers 21 and 22, respectively.
  • the initial value R and the first vector element V 1 are stored in the third and the fourth registers 25 and 26, respectively.
  • a first local sum of the initial value R and the first vector element V 1 is calculated by the arithmetic unit 28.
  • a first intermediate result R l representative of the first local sum is stored in the first register 21.
  • a second vector element V 2 is stored in the second register 22.
  • the first intermediate result R 1 and the second vector element V 2 are stored in the third and the fourth registers 25 and 26, respectively.
  • a second local sum of the first intermediate result R 1 and the second vector element V 2 is calculated by the arithmetic unit 28.
  • a second intermediate result R 2 representative of the second local sum is stored into the first register 21.
  • a third vector element V 3 is stored in the second register 22.
  • the intermediate result related to one vector.element and a next following vector element are synchronously stored in the first and the second registers 21 and 22, respectively.
  • the arithmetic unit 28 Inasmuch as supply of the next vector element to the operand producing section 14 is postponed or awaited until the intermediate result is calculated by the arithmetic unit 28 for the above-mentioned one vector element, two machine cycles are indispensable as an execution cycle which is for executing an arithmetic operation on each vector element. Due to such a waiting time for the supply of the next vector element, the data processing circuit 11 undesiredly has a slow calculation speed. When the number of the pipeline stages is represented by m, the waiting time is substantially equal to (m - 1) machine cycles. Thus, the data processing circuit 11 is incapable of calculating the ultimate sum of the series of the vector elements at a high speed.
  • WR1 and WR 2 represents values of first and second partial sum, respectively.
  • this invention executes the vector instruction in accordance with arithmetic steps as follows.
  • [] represents the Gauss' notation and MOD represents a modulo arithmetic.
  • WR m represents a value of an m-th partial sum.
  • First and second additional registers 31 and 32 are coupled to the arithmetic unit 28.
  • the first and the second additional registers 31 and 32 are operable as first and second work registers which are for successively temporarily storing the intermediate results calculated by the arithmetic unit 28.
  • the first and the second registers 21 and 22 and the work registers 31 and 32 are simultaneously operable in one machine cycle.
  • a third selector 33 is coupled to the first and the second work registers 31 and 32.
  • the third selector 33 is for selecting each of the first and the second work registers 31 and 32 as a selected register to supply the arithmetic unit 28 through the operand producing section 14 with the intermediate result stored in the selected register.
  • the first selector 23 is responsive to the first and the second output signals given from the first and the second registers 21 and 22 and to the intermediate result given from the third selector 33.
  • the first selector ' 23 selects one of the first and the second signals and the intermediate result to produce a first selected signal.
  • the second selector 24 selects one of the first and the second signals and intermediate result to produce a second selected signal.
  • a specifying circuit 35 is for sequentially and cyclically specifying one of the work registers 31 and 32 as a specified register to provide the specified register with a set command signal which is for making the specified register store the intermediate result.
  • the specifying circuit 35 sequentially specifies the work registers 31 and 32 one at a time, as the specified register every one machine cycle. Consequently, the first work register 31 is supplied with a succession of every other one of the intermediate results while the second work register 32 is supplied with the remaining intermediate results.
  • the specifying circuit 35 also provides the remaining work register with a select command signal which is for making the third selector 33 select that remaining work register as the selected register which is different from the specified work register.
  • the first and the second work registers 31 and 32 are alternately selected as the selected register by the third selector 33.
  • an instruction to be executed is the vector instruction which is represented by Formula (1) described before.
  • the vector instruction is executed in accordance with a sequence of arithmetic steps as follows.
  • R, R 1 , and R 2 represent the registers 21, 31, and 32, respectively, and ( ) represents a content of each of the registers.
  • a machine cycle is again represented by T.
  • an initial value R and a first vector element V 1 are stored in the first and the second registers 21 and 22, respectively, in a known manner.
  • the initial value R and the first vector element V 1 are stored in the third and the fourth registers 25 and 26 through the first and the second selector 23 and 24, respectively.
  • a second vector element V 2 is stored in the second register 22.
  • another initial value R 2 0 is stored in the second work register 32 under control of software.
  • a first local sum of the initial value R and the first vector element V 1 is calculated by the arithmetic unit 28.
  • a first intermediate result (R + V l ) representative of the first local sum is stored in the first work register 31, namely, an R 1 register.
  • a third vector element V 3 is stored in the second register 22.
  • the second vector element V 2 is stored in the fourth register 26 through the second selector 24.
  • a second intermediate result (R 2 + V 2 ) representative of the first local sum is stored in the second work register 32, namely, an R 2 register.
  • a fourth vector element V 4 is stored in the second register 22.
  • the first intermediate result (R + V 1 ) and the third vector element V 3 are stored in the third and the fourth registers 25 and 26, respectively.
  • the third selector 33 selects the first work register 31 as a selected register by operation of the specifying circuit 35.
  • a first content (R 1 ) of the first work register 31 is sent to the operand producing section 14 through the third selector 33.
  • the first content (R 1 ) is stored in the first register 21 through the first selector 23, the third register 25, and the arithmetic unit 28.
  • the third selector 33 selects the second work register 3,2 as the selected register by operation of the specifying circuit 35.
  • a second content (R 2 ) of the second work register 32 is sent to the operand producing section 14 through the third selector 33.
  • the second content (R 2 ) is stored in the third register 25 through the first selector 23.
  • the first content (R 1 ) stored in the first register 21 is sent to the fourth register 26 through the second selector 24.
  • an ultimate result (Rl + R 2 ) is calculated by the arithmetic unit 28.
  • the ultimate result is stored in the first register 21, namely, the R register.
  • a calculation of is carried out.
  • a combination of the specifying circuit 35 and the third selector 33 is operable as an administrating part for administrating the work registers 31 and 32 to cyclically transfer the intermediate results among the work registers 31 and 32 and the arithmetic unit 28 in a pipeline fashion through the third register 25.
  • the data processing circuit 11 executes the vector instruction represented by Formula (1) in accordance with the arithmetic steps represented by Formulae (4). An ultimate result is obtained by adding contents WR1 , ..., and W R m of all work registers like in the data processing circuit 11 illustrated in Fig. 4.
  • a data processing circuit 11 comprises similar parts which are designated again by like reference numerals.
  • the data processing circuit 11 also comprises first and third registers 21 and 25 which are operated like a pipeline as will become clear.
  • the first and the third registers 21 and 25 are furthermore operable as work registers which are for successively temporarily storing intermediate results sent from an arithmetic unit 28.
  • the work registers 21 and 25 do not fixedly correspond to the first and the second work registers 31 and 32 illustrated in Fig. 4, respectively. Instead, each of the work registers 21 and 25 is operable as any one of the first and the second work registers 31 and 32 illustrated in Fig. 4.
  • the data processing circuit 11 further comprises an administrating circuit 41 which is for administrating the work registers 21 and 23 to cyclically transfer the intermediate results among the work registers 21 and 25 and the arithmetic unit 28 in a pipeline fashion.
  • the administrating circuit 41 operates when the registers 21 and 25 are also used as the work registers.
  • the administrating circuit 41 comprises a specifying section which is for specifying the registers 21 and 25 as the work registers and for controlling operations of the registers 21 and 25 specified as the work registers.
  • the specifying section also controls operations of first and second selectors 23 and 24 and a fourth register 26.
  • an instruction to be executed is a vector instruction which is represented by Formula (1) described above.
  • the vector instruction is executed in accordance with a sequence of arithmetic steps represented by Formulae (5) described before.
  • a machine cycle is once again represented by T.
  • an initial value R and a first vector element V 1 are stored in the first and the second registers 21 and 22, respectively.
  • the initial value R and the first vector element V 1 are stored in the third and the fourth registers 25 and 26 through the first and the second selectors 23 and 24, respectively, under control of the administrating circuit 41.
  • a second vector element V 2 is stored in the second register 22.
  • another initial value R 2 0 is stored in the first register 21 operated like the second work register 32 (Fig. 4) under control of the administrating circuit 41.
  • a first local sum of the initial value R and the first vector element V 1 is calculated by the arithmetic unit 28.
  • a first intermediate result (R + V1) representative of the first local sum is stored in the first register 21 (namely, an R 1 register) like the first work register 31 (Fig. 4) under control of the administrating circuit 41.
  • the third register 25 serves as the second work register 32 (Fig. 4) which is for holding a content of an R 2 register for the purpose of obtaining an ultimate result.
  • a third vector element V 3 is stored in the second register 22.
  • the second vector element V 2 is stored in the fourth register 26 through the second selector 24 under control of the administrating circuit 41.
  • a second intermediate result (R 2 + V 2 ) representative of the first local sum is stored in the first register 21 (namely, the R 2 register) serving as the second work register 32 (Fig. 4) under control of the administrating circuit 41.
  • the first intermediate result (R + V 1 ) is stored in the third register 25 through the first selector 23 under control of the administrating circuit 41.
  • the third register 25 serves as the first work register 31 (Fig. 4) which is for holding a content of the R 1 register for the purpose of obtaining the ultimate result.
  • a fourth vector element V 4 is stored in the second register 22.
  • the third vector element V 3 is stored in the fourth register 26 through the second selector 24 under control'of the administrating circuit 41.
  • a content (one of the values R 1 and R 2 ) of the first register 21 is stored in the fourth register 26 through the second selector 24 under control of the administrating circuit 41.
  • the content of the fourth register 26 and another content (the remaining one of the values R 1 and R 2 ) of the third register 25 are added to each other by the arithmetic unit 28.
  • the arithmetic unit 28 produces an ultimate result (R 1 + R 2 ).
  • the ultimate result is stored in the first register 21, namely, an R register, under control of the administrating circuit 41.
  • a calculation of is carried out.
  • first and third registers 21 and 25 serves as the work registers.
  • the first and the third registers 21 and 25 constitute a pipeline in the operand producing section 14. Registers which constitute such a pipeline may be referred to as component registers. If the number m of pipeline stages is greater than two in the operand producing section 14, such a pipeline is composed of the component registers which are greater than two in number. In such a case, all of the component registers serve as the work registers under control of the administrating circuit 41.
  • this invention may be applicable to a data processing circuit for use in calculating a total product of a succession of data.
  • V i 1, 2, ...
  • the total product is represented by
  • the arithmetic unit 28 may be for carrying out a multiplication iteratively on the data of the succession.

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
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EP85304956A 1984-07-11 1985-07-11 Datenverarbeitungsschaltung zur Hochgeschwindigkeitsberechnung von entweder einer Totalsumme oder eines Totalprodukts einer Reihe von Daten Ceased EP0169030A3 (de)

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Application Number Priority Date Filing Date Title
JP143579/84 1984-07-11
JP59143579A JPH0650512B2 (ja) 1984-07-11 1984-07-11 デ−タ処理装置

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EP0169030A2 true EP0169030A2 (de) 1986-01-22
EP0169030A3 EP0169030A3 (de) 1988-07-06

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Cited By (3)

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WO1988009016A1 (en) * 1987-05-14 1988-11-17 Fujitsu Limited Vector processor for processing recurrent equations at a high speed
EP0348030A2 (de) * 1988-06-23 1989-12-27 International Business Machines Corporation Ergebnisverfügbarkeit einer Rechensequenz
EP0606674A1 (de) * 1992-12-04 1994-07-20 Koninklijke Philips Electronics N.V. Prozessor zur gleichförmigen Operationen auf Datenreihenfolgen in entsprechenden parallelen Datenströmen

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JP2806524B2 (ja) * 1988-03-04 1998-09-30 日本電気株式会社 ベクトル演算命令発行制御方法
JPH0527970A (ja) * 1991-07-18 1993-02-05 Seikosha Co Ltd 演算装置
US6128721A (en) * 1993-11-17 2000-10-03 Sun Microsystems, Inc. Temporary pipeline register file for a superpipelined superscalar processor
US5619664A (en) * 1994-01-04 1997-04-08 Intel Corporation Processor with architecture for improved pipelining of arithmetic instructions by forwarding redundant intermediate data forms
EP1162547A3 (de) * 2000-06-05 2003-09-03 DSP Group Ltd. Von Ort FFTspeicherverwaltung

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1988009016A1 (en) * 1987-05-14 1988-11-17 Fujitsu Limited Vector processor for processing recurrent equations at a high speed
US4949292A (en) * 1987-05-14 1990-08-14 Fujitsu Limited Vector processor for processing recurrent equations at a high speed
EP0348030A2 (de) * 1988-06-23 1989-12-27 International Business Machines Corporation Ergebnisverfügbarkeit einer Rechensequenz
EP0348030A3 (de) * 1988-06-23 1993-02-24 International Business Machines Corporation Ergebnisverfügbarkeit einer Rechensequenz
EP0606674A1 (de) * 1992-12-04 1994-07-20 Koninklijke Philips Electronics N.V. Prozessor zur gleichförmigen Operationen auf Datenreihenfolgen in entsprechenden parallelen Datenströmen

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JPS6123276A (ja) 1986-01-31
US4849926A (en) 1989-07-18
EP0169030A3 (de) 1988-07-06
JPH0650512B2 (ja) 1994-06-29

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