EP0163096B1 - Dispositif pour sauvegarder l'état du calculateur - Google Patents

Dispositif pour sauvegarder l'état du calculateur Download PDF

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Publication number
EP0163096B1
EP0163096B1 EP85104649A EP85104649A EP0163096B1 EP 0163096 B1 EP0163096 B1 EP 0163096B1 EP 85104649 A EP85104649 A EP 85104649A EP 85104649 A EP85104649 A EP 85104649A EP 0163096 B1 EP0163096 B1 EP 0163096B1
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EP
European Patent Office
Prior art keywords
memory
processor
archive
address
computer
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Expired
Application number
EP85104649A
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German (de)
English (en)
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EP0163096A1 (fr
Inventor
Hubert Kirrmann
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BBC Brown Boveri AG Switzerland
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BBC Brown Boveri AG Switzerland
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Publication of EP0163096A1 publication Critical patent/EP0163096A1/fr
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1441—Resetting or repowering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements

Definitions

  • the invention is based on a device for saving a computer state according to the preamble of patent claim 1.
  • This device is connected to the processor bus and tracks the bus handles with which the processor changes the state of the main memory (write cycles). Before a variable is changed in the working memory, this device, which is called the “save stack”, addresses the variable concerned, reads the previous content and saves it in a stack.
  • the rescue pile is empty.
  • the state of the computer at this retreat point should be able to be restored if there is a failure before the next retreat point is reached.
  • the processor is reinitialized and the rescue stack is written back to the working memory. This gives all variables their previous value, namely the one they had when the rescue pile was empty, i.e. at the last retreat point, even if this value has been changed several times in the meantime.
  • the invention solves the problem of improving the ratio of useful work time to rescue time.
  • the present invention is also based on a storage of the changed variables, however the new value is not saved, but after the “saving of the changes”.
  • a device for saving the state of a computer with a cascade memory is the subject of part-application EP-A-87110448.5 (published No. 0254247).
  • Fig. 1 denotes a processor, 2 an address bus, 3 a data bus, 4 a working memory, 5 and 6 two archive memories or 5 an archive memory zone 1 and 6 an archive memory zone 2.
  • 4a, 5a and 6a denote address decoders in the working memory 4 and in the archive memories 5 and 6; 4b, 5b and 6b copy areas for the processor state in the main memory 4 or in the archive memories 5 and 6 ..
  • processor 1 and its working memory 4 are required for normal computer operation.
  • the archive stores 5 and 6 are used for fault tolerance.
  • the address bus 2 and the data bus 3 or the address and data lines were drawn separately in order to simplify the explanations. It could just as well be a multiplexed bus or a serial bus.
  • the work of the processor consists of: 1. useful work, 2. state rescue and 3. restoration of the state after overcoming the failure.
  • Useful work is the normal operation of processing a useful program. If a failure should occur during the useful work, the processor 1 undertakes a recovery after the repair, as will be explained below.
  • the useful work is divided into steps, which are called retreat blocks or blocks for short.
  • the blocks are considered to be indivisible operations: either they are completed or the computer returns to the state before the block.
  • the status of the computer at any time is defined by the current status of the user program, ie by the status of its variables, by the status of the internal registers of the processor and the input and output devices, not shown, I / O devices for short .
  • Register state and state of the I / O devices are referred to as processor state or context.
  • the program code is not part of the state.
  • Variable state and processor state together form the computer or Task status.
  • the processor state is stored in the copy area 4b of the main memory 4. Overall, the working memory 4 contains the entire task status.
  • retreat point i RPi
  • RPi + 1 RPi + 1
  • the retreat points are chosen at regular intervals or as required.
  • the state at the retreat point is recorded by executing a state rescue program.
  • the distance between neighboring withdrawal points is given by the application. In fast processes, the interval may not exceed a few 100 ms, in data processing applications it may be a few hours.
  • the processor should abandon the aborted work and try to restore the RPi state as it was at the beginning of the block after repair in order to process the block again from there. This is the job of the recovery program.
  • the state rescue can take place parallel to the work or after the work. First of all, we assume that useful work and state rescue take place in succession.
  • the archive store contains the RPi status. If a block has been calculated without errors, the state of the process RP i + 1 is copied from the working memory 4 into the archive memory 5, and the next block can begin.
  • the copying operation from the main memory into the archive memory can be carried out by the processor 1 itself by addressing a cell of the main memory 4 for reading and the corresponding cell of the archive memory 5 for writing.
  • a control device (not shown) with direct memory access can carry out the copying work somewhat faster than the processor.
  • the archive store 5 should have the same organization as the main memory, i. that is, it should have the same number of memory locations with the same division as the main memory 4. For each memory cell in the main memory 4 there is a corresponding memory cell in the archive memory 5.
  • the bus addresses of the corresponding memory cells in the main memory 4 and in the archive memory 5 do not need to match, they can e.g. differentiate in the most significant bit in order to reduce the circuit complexity. However, it is advantageous if the address is the same relative to the beginning of the memory in the case of corresponding memory cells from the working memory 4 and archive memory 5.
  • the archive store 5 is approximately as fast as the main memory 4.
  • the archive store 5 could e.g. a buffered CMOS read / write memory, a non-volatile read / write memory RAM, as z. B. is commercially available under the name IN-TEL 2004, or a slower memory, such as a core storage.
  • Non-volatile memories such as EAROM or EEPROM
  • EAROM EAROM
  • EEPROM EEPROM
  • a diskette, optical and magnetic disk are not only problematic for reasons of speed, their organization differs considerably from the linear structure of a memory, and an appropriate illustration must first be produced.
  • the restoration consists of the processor 1 being tested for reliability in a self-test or external test after it has been repaired. Then the processor or the control unit with direct memory access loads the task state, which was stored in the archive memory 5, back into the main memory 4. Then the I / O devices and the processor 1 are loaded with their internal state (processor state). Finally, the program counter of processor 1 is set, and useful work can begin again at the last retreat point.
  • the archive store 5 While copying the retreat point into the archive store 5, the archive store 5 is inconsistent, it contains parts from the RP i and parts from the RP i + 1.
  • the copy operation should be indivisible, i.e., it is either fully executed or not at all. Since the copy operation takes a finite time, the probability of failure during that time is not negligible.
  • the archive store 5 does not lose any information in the event of a failure, but the zone or the storage area which was being processed or updated at the time of the failure is inconsistent and is considered lost.
  • the archive store is divided into two identical halves, the archive store areas 5 and 6.
  • the processor 1 can write in both areas of the archive memory 5, 6, but not at the same time. No failure should cause processor 1 to change the part of the archive memory with which it is not currently working.
  • both areas 5 and 6 of the archive memory contain the same content, namely one copy of the main memory 4 (process status on RP i). Both archive stores or archive storage areas are updated one after the other, ie brought from RP i + 1. As a convention, we assume that the archive store 5 is updated first and then the archive store 6.
  • the copies can be provided with the physical or with a logical time to mark their validity.
  • the storage area of the archive store that is currently being processed is referred to as the “dirty” area and the other as the “clean” area.
  • the processor 1 first carries out the state rescue with the archive memory 5. Then the roles of the dirty and clean areas are reversed. The processor 1 then carries out the same operation with the archive memory 6.
  • processor 1 If a failure occurs during the first copy, then the processor returns to the last retreat point RP i, if it occurs during the second copy, then processor 1 starts with the new retreat point RP i + 1. If both copies are valid and contain the same RP, then processor 1 takes any copy.
  • a recovery program checks which half of the archive memory contains a valid RP after the repair has been completed, and if this applies to both halves, the younger RP is selected. Then the task will resume from that point.
  • Simplification of state rescue The state rescue described above is time-consuming, especially with a large memory. So that there is a reasonable relationship between useful work and the rescue period, the retreat blocks should be at least as long as twice the rescue period, which is not always tolerable in time-critical applications.
  • the rescue time can be reduced significantly with the methods described below. Instead of processor 1 writing both memory areas individually, one of the memory areas can already be updated during useful work. This happens because the dirty archive storage area tracks activity on the bus and updates accordingly.
  • the state of the main memory 4 is changed in accordance with the program progress. Any change in the working memory 4 is due to a write operation on the processor bus.
  • the dirty part of the archive store follows this activity on the bus, in principle without disturbing the traffic.
  • the dirty archive memory makes the same change in its copy of that memory cell.
  • the clean part of the archive store is not changed.
  • the processor writes its state and e.g. the time in the main memory (and thus also in the archive memory 5) and reports its status as valid.
  • the dirty archive memory now contains the state of the main memory 4 and the processor 1 at the end of block RP i + 1.
  • both storage areas of the archive storage again contain a consistent state, namely that at the beginning (RP i, clean storage area 6) and that at the end of the block (RP i + 1, formerly dirty storage area 5).
  • This method also allows a slower memory to be used for the archive memory than for the main memory, since the archive memory is only used for the write cycles. It is generally assumed that there is an average of one write cycle per 9 read cycles.
  • the rescue time is reduced by half, in our example from 262 ms to 131 ms.
  • the archive memory can be about 9 times slower than the main memory.
  • Fig. 4 shows an embodiment in which a stack memory 8 with an address memory area 8 a and a data memory area 8 b is provided between the working memory 4 and the archive memories 5 and 6 and is connected to the same address bus 2 and data bus 3.
  • data memory 8 is empty. All changes to the working memory 4 are simultaneously entered in the stack memory 8 and in one of the archive memories (dirty zone). Without using the processor, the associated address / data pair is registered and entered in the stack 8 for each write access to the bus.
  • the stack can be organized as a FIFO (first-in, firstout) or STACK (first-in, last-out).
  • All address / data pairs are entered in the order in which they occur, and a counter or a stack pointer records the respective fill level of the memory and assigns its place to the new value pairs.
  • the stack contains all the data that have changed since the beginning of the block.
  • the first archive store 5 has already been updated, either by listening as described above or using the same method as the archive store 6.
  • the stack memory 8 reduces the time period for the state rescue, since it contains all the information necessary for the state rescue in an ordered form. It is no longer necessary to transfer the entire contents of the working memory to the archive memory 6, but only the part that has been changed since the last retreat point.
  • Fig. 5 shows an embodiment with such a cache memory 7.
  • the first archive memory 5 can e.g. be updated by listening.
  • the stack 8 occurs as a background memory. It is e.g. organized as a FIFO or STACK.
  • the operating mode of the cache memory which is referred to as restoring, is again best suited.
  • restoring In order to save the entire computer state at the retreat point, however, it is necessary to write out the contents of the cache memory.
  • Various methods for this method has already been described. The efficiency of this method depends on the application and is best suited if the addresses of the variables form groups. This is e.g. the case with all modern programming languages.
  • the rescue time can be shortened by a different organization of the stack, as will be shown with reference to FIG. 6.
  • the stack 8 was previously organized as a linear memory (FIFO or STACK). There it happens that the same address appears several times because of a variable, for example a run variable in a loop that has been changed several times. The number of entries in the stack 8 could be reduced if only the last value of the variable were kept. Then it would be possible to use an archive store that is much slower than the stack store.
  • FIFO linear memory
  • the stack 8 is provided with an associative memory which has an associative address memory 8 a ', an associative data memory area 8 b and a counter 8 c.
  • the stack reads the address on each write cycle on the processor bus. He compares them with the entries in his address table by creating the address at the so-called key input of the associative memory. If the address is not found, it is read into the associative memory as a new entry. The counter 8 c assigns it its position, it is then increased by one digit. From now on, the address is considered to be present. If the address already exists or has just been entered, the position of this address appears on the so-called position output to the data storage area 8 b. The position address has the same width as the counter 8 c. The associated date is then recorded in the data storage area 8b.
  • the data memory is a normal semiconductor memory.
  • processor 1 When the stack memory 8 is saved in the archive memory 6, the processor 1 addresses the counter 8 c and thus forces a position address on the position lines and on the address lines. In this mode, processor 1 does not drive the address lines, but rather lets them float.
  • the processor 1 is z. B. buffered by a three-state gate.

Claims (6)

1. Dispositif pour la sauvegarde de l'état d'un ordinateur aux points de reprise de programme dans le programme à traiter par l'ordinateur, l'ordinateur comportant sur un bus d'adresses et de données (2, 3), une mémoire de travail (4), un pro- cessuer (1) avec au moins un registre interne, une unité d'entrée/sortie avec également au moins un registre interne et une mémoire intermédiaire (8), et la mémoire de travail contenant, pendant le déroulement du programme, toujours l'état d'ordinateur du moment y compris les contenus des registres cités, caractérisé en ce que, pur le stockage de l'état de l'ordinateur aux points de reprise de programme (RPi-1, RPi, RPi+1, ...), une première mémoire d'archivage résistant aux pannes (6) est connectée en supplément aux dits bus d'adresses et de données (2, 3), que la mémoire intermédiaire (8) enregistre automatiquement de manière synchrone toutes les modifications de données dans la mémoire de travail (4) y compris leurs adresses associées et que des moyens sont prévus pour transférer le contenu de la mémoire intermédiaire à chaque point de reprise de programme, dans la première mémoire d'archivage.
2. Dispositif suivant la revendication 1, caractérisé en ce que la mémoire intermédiaire (8) est une mémoire dite FIFO.
3. Dispositif suivant la revendication 1, caractérisé en ce que la mémoire intermédiaire est une mémoire STACK.
4. Dispositif suivant la revendication 1, caractérisé en ce que la mémoire intermédiaire est une mémoire associative.
5. Dispositif suivant l'une quelconque des revendications 1 à 4, caractérisé en ce qu'une anté- mémoire (7) est prévue entre le processeur et les bus d'adresses et de données.
6. Dispositif suivant l'une quelconque des revendications 1 à 5, caractérisé en ce qu'une deuxième mémoire d'archivage résistant aux pannes (5) qui enregistre automatiquement de manière synchrone toutes les modifications de données dans la mémoire de travail (4) est connectée aux bus d'adresses et de données.
EP85104649A 1984-04-26 1985-04-17 Dispositif pour sauvegarder l'état du calculateur Expired EP0163096B1 (fr)

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CH205384 1984-04-26
CH2053/84 1984-04-26

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EP87110448.5 Division-Into 1985-04-17

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EP (2) EP0163096B1 (fr)
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DE (1) DE3566314D1 (fr)

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US4905196A (en) 1990-02-27
JPH0619722B2 (ja) 1994-03-16
EP0254247A3 (fr) 1988-08-10
EP0254247A2 (fr) 1988-01-27
DE3566314D1 (en) 1988-12-22
EP0163096A1 (fr) 1985-12-04
JPS60235246A (ja) 1985-11-21

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