EP0162969A1 - Circuits de commutation et dispositif à matrice utilisant ces circuits - Google Patents

Circuits de commutation et dispositif à matrice utilisant ces circuits Download PDF

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Publication number
EP0162969A1
EP0162969A1 EP84200778A EP84200778A EP0162969A1 EP 0162969 A1 EP0162969 A1 EP 0162969A1 EP 84200778 A EP84200778 A EP 84200778A EP 84200778 A EP84200778 A EP 84200778A EP 0162969 A1 EP0162969 A1 EP 0162969A1
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EP
European Patent Office
Prior art keywords
terminals
terminal
circuits
circuit
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP84200778A
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German (de)
English (en)
Inventor
Guido Petrus Theophiel Constant Remmerie
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Bell NV
Alcatel Lucent NV
Original Assignee
Bell Telephone Manufacturing Co NV
Alcatel NV
International Standard Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bell Telephone Manufacturing Co NV, Alcatel NV, International Standard Electric Corp filed Critical Bell Telephone Manufacturing Co NV
Priority to EP84200778A priority Critical patent/EP0162969A1/fr
Priority to AU42703/85A priority patent/AU4270385A/en
Priority to JP11763085A priority patent/JPS6150195A/ja
Priority to BE2/60705A priority patent/BE902538A/fr
Publication of EP0162969A1 publication Critical patent/EP0162969A1/fr
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3681—Details of drivers for scan electrodes suitable for passive matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3692—Details of drivers for data electrodes suitable for passive matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning

Definitions

  • the present invention relates to a matrix device and an associated control device, said coordinate matrix including a plurality of series of crossing electric lines (rows, columns) defining crosspoints, said control device including a plurality of driver units arranged along different sides of said coordinate matrix and having line output terminals coupled to distinct ones of the lines of at least one of said series, and said control device including also an input signal source coupled to said driver units and adapted to supply input signals to said driver units.
  • driver units are on opposite sides of tie coordinate matrix thereby benefiting from a spacing between adjacent unit terminals which is twice that between matrix lines.
  • the lines on opposite sides are used for distinct functions.
  • An object of the present invention is to provide a matrix device of the above type but which enables the use of identical driver units having a maximum number of terminals per unit surface and able to be coupled to the signal source by a minimum of equipment.
  • each of said driver units includes a plurality of driver circuits each having one of said line output terminals and interconnected so as to form a shift register, shift control means to shift said input signals through said shift register, and direction means for controlling the direction of said shift.
  • shift registers which are fed from a same side of the matrix, the number of connector terminals required to coupled the signal source to these shift registers is reduced.
  • these shift registers are bidirectional they can be fed from a same side of the matrix and the driver units can be made identical and arranged with most of their line output terminals facing a side of the matrix.
  • Another advantage of such a driver unit is that, when integrated on a chip, output terminals can be arranged on the four sides thereof.
  • the driver units could be identical if so arranged that most of their line output terminals would face the matrix and the input signals were fed to the shift registers from opposite sides of this matrix. However, in this case the number of connector terminals required would increase and, moreover, the input signals would have to be shifted through the shift registers in reverse order.
  • Another solution permitting the use of identical driver units would be to connect the line output terminals of the driver units arranged at one side of the matrix to corresponding lines of this matrix by prolonging thee lines under these units. However, in this case the side of the chip facing the matrix can not have terminals so that the total number of terminals per unit surface would then be considerably reduced.
  • driver units instead of using identical driver units it is possible to use "mirror-image" driver units. Although a single type of driver unit has a more complex design, it has the advantage that it can be manufactured, tested and stocked at less cost than two separate chips, even though the latter can benefit f.rom a partly common design since a mirror symmetry is present.
  • the present invention relates also to a signal switching circuit enabling controlled complementary couplings between first and second terminals and, alternatively between third and fourth terminals.
  • Such a switching circuit is already known in the art and is generally realized by means of two complementary controlled switches or gates used for respective ones of the two couplings.
  • a further object of the invention is to provide a switching circuit of the above type but which enables the signals transmitted between the first and the second terminals, or between the third and the fourth terminals to be memorized while remaining of a particularly simple structure.
  • this object is achieved due to the fact that said second and fourth terminals are interconnected and coupled through a signal memory circuit to the common terminal of two gates controlled so as to be in complementary conductive states and whose other terminals are respectively coupled to said first and third terminals.
  • the switching circuit memorizes the above signals and is of a very simple structure due to the use of only one electronic change-over contact formed by the two complementary controlled gates having the common terminal mentioned above, and by the common use of the memory circuit by the two couplings.
  • the present invention further relates to a switching circuit able to selectively couple one out of at least three voltages at respective input terminals to a common output terminal.
  • a further object of the present invention is to realize a connection between one of these input terminals and the common output terminal while avoiding short circuits between the voltages applied to these input terminals, especially when the voltage difference between the terminals is relatively high e.g. 300 Volts,
  • first and second circuits coupling respectively the first and the second input terminals to said common output terminal include at least one DMOS switch device, and that at least one third circuit coupling the third input terminal to said common output terminal includes two DMOS switch devices coupled in series opposition.
  • DMOS transistors Using the source-drain paths of DMOS transistors is switch devices is appropriate because they can withstand relatively high voltages such as the 300 Volts mentioned above. Iowever, such DMOS transistors have a parasitic diode shunting their drain-to-source path. If the voltage at the first input terminal is the most positive one of the three, the DMOS transistor of the: first circuit can then be oriented so that its parasitic diode is always blocked and has no influence on the open or closed state of this transistor. Alternatively, if the voltage at: the second input terminal is the most negative one of the three the DMOS transistor of the second circuit can also be oriented so that its parasitic diode is always blocked, e.g. the source of the DMOS transistor of one circuit is connected to the common output terminal together with the drain of the DMOS transistor of the other circuit.
  • the corresponding DMOS transistor in the third circuit would always have its parasitic diode conductive when one of the two other voltages is present at the common output terminal. But two DMOS transistors connected in series with their parasitic diodes back to back solve the problem for this third circuit.
  • the matrix device or flat panel display FPD shown in Fig. 1 includes a liquid crystal display LCD and control circuitry mounted around this display.
  • the latter consists of a thin film of smectic liquid crystal sandwiched between two plates of glass each provided with a set of transparent conductive stripes represented in heavy lines and forming rows and columns of a coordinate matrix respectively.
  • the area of the intersection of two such perpendicular row and column stripes represents one picture element or pixel and the display includes 288,000 such pixels arranged in 400 rows and 720 columns. This is sufficient to display 2000 alphanumeric characters each defined by 9 columns and 16 rows.
  • a transparent state is the result of a "clearing” operation and an opaque state is the result of a "scattering" operation.
  • the change of state of a pixel, from opaque to transparent and vice versa can be derived directly from the drive signals applied to the corresponding crossing row and column stripes.
  • the scatter function create an opaque pixel
  • the clear function create a transparent pixel
  • Additional cycles will have no significant effect.
  • the smectic liquid crystal material is its voltage threshold, i.e. it will not change state until a certain minimum level of voltage is reached. When this level is exceeded on a particular pixel, that picture element will assume the state indicated by the applied frequency. Near the threshold the liquid crystal material responds rather slowly. However, when the stimulating voltage increases, the response time decreases.
  • An unbalanced drive signal should never be used to drive a row or column stripe since a long term DC component applied to the liquid crystal material adversely affect performance and life thereof. All these drive waveforms should therefore be well balanced, i.e. they should have equal positive and negative amplitudes and durations.
  • this entire row is scattered to effectively eliminate all visible information and afterwards, to display new information, selected pixels are cleared whilst the remaining pixels of that row are left in their scattered state.
  • the scatter function is performed on at least one row whilst the clear operation is always done one row at a time. However, in that one row, only specific individual pixels are selected to be cleared.
  • the scattering waveforms are shown in Fig. 2. Scatter of a pixel is performed by differentially applying thereto one cycle of a 50 Hertz square waveform PSC having an amplitude of 600 Volts peak-to-peak. There are two modes used for scattering. According to a first mode the entire panel is scattered. This is accomplished by applying square waveforms CSC and RSC which are in phase opposition to all column stripes and to all row stripes during one cycle respectively. These waveforms have a peak-to-peak voltage of 300 Volts. More particularly during the first half cycle time, a voltage of +150 Volts (CSC) is applied to all the column stripes while a voltage of -150 Volts (RSC) is applied to all the row stripes of the display.
  • CSC +150 Volts
  • RSC voltage of -150 Volts
  • the resulting differential voltage has an amplitude of 300 Volts (PSC).
  • PSC 300 Volts
  • CSC -150 Volts
  • RSC + 150 Volts
  • a second mode of scatter only selected rows are scattered.
  • the voltage waveform CSC is applied to all the columns whilst the voltage waveform RSC in phase opposition with respect to CSC is only applied to the row stripes to be scattered.
  • a square voltage waveform RNSC which is the complement of RSC is applied to the other row stripes. The resultant differential voltage PNSC thus applied across all the pixels in these last mentioned rows is zero so that no scattering occurs therein.
  • the clear function is used to control individual pixels and to thereby display visible information. This operation is performed on selected pixels of a single row which has previously been set to the scattered state and consists of differentially applying three cycles of a 1.5 kilohertz square voltage signal PCL with an amplitude of 360 Volts peak-to-peak (Fig. 3). The creation of the differential voltage is explained hereinafter.
  • STROBE square "row information” signal
  • Fig. 3 To the single selected row stripe three cycles of a square "row information" signal called STROBE (Fig. 3) are applied, all other row stripes being connected to the ground voltage.
  • the signal STROBE has a peak-to-peak voltage of 300 Volts.
  • CNC or CC each 60 Volts peak-to-peak
  • the signal CNC is in phase and the signal CC is in phase opposition with respect to the signal STROBE, these waveforms being shown in Fig. 3.
  • the signal CC is applied to the column stripes whose pixels are to be cleared, whilst the signal CNC is applied to the column stripes whose pixels are to be left in the scattered state.
  • pixels are subjected to the signal CC on the column stripe and to ground voltage on the row stripe. This produces a resulting differential signal (60 Volts peak-to-peak) which is identical to the signal CC and which may be applied for a long time, to the pixels without affecting their previous state.
  • pixels are subjected to the signal CNC on the column stripe and to the signal STROBE on the row stripe.
  • This combination produces a differential voltage PNCL (Fig. 3) of 240 Volts peak-to-peak across these pixels.
  • This voltage PNCL cannot be held on the pixels for a long period but since no more than three cycles (2 milliseconds) are applied to each row the state of these pixels is not affected.
  • the signal CNC is applied to the column stripe while the row stripe is at ground. This produces across the pixel a differential voltage equal to CNC which may be applied for an indefinite period to the pixel without affecting its previous state.
  • the frequencies (50 Hertz and 1.5 kilohertz) mentioned above are average values.
  • temperature sensing means are provided on the display to adjust the above frequencies in function of the temperature of the liquid crystal.
  • these frequencies are between 8.3 Hertz and 50 Hertz, and between 1 kilohertz and 2 kilohertz for the "clear" and the "scatter" respectively.
  • the above mentioned control circuitry includes a plurality of driver units FPDR and each of such unit encompasses 30 drivers which are each coupled to a row or a column stripe.
  • Each driver unit FPDR is realized as a single chip and each driver thereof is able to apply the above mentioned signals CSC, CC, CNC or RSC, RNSC, STROBE to the associated column or row stripe respectively.
  • the switching between the positive and negative portions of these signals occurs with equal rise and decay times which are less than 30 microseconds.
  • the driver units FPDR are mounted along the sides of the display LCD and those arranged at one side of the LCD control either the even or the odd numbered stripes ending on that side, whilst the driver units situated on the opposite side control the stripes of the other parity .
  • each driver unit FPDR is able to control 30 stripes and because there are 720 column stripes, 12 driver units FPDR are disposed along both the top and bottom sides of the LCD. Likewise, because there are 400 row stripes, 7 driver units FPDR are provided along the right and left sides of this display LCD.
  • the driver units FPDR are connected in cascade so that serial control data and information signals may be shited through these cascade connections.
  • the flat panel display FPD further has only two sets of connector terminals located along two adjacent sides of the FPD respectively and the driver units FPDR are all identical and have their output terminals, connected to the associated stripes, oriented towards these stripes.
  • the serial control data and information signals mentioned above have to befitted in one direction in the driver units FPDR located along one side of the display LCD while they have to be shifted in the other direction in the driver units FPDR located along the opposite side of the display LCD.
  • the direction of shifting is controlled in each cascade connection of driver units FPDR by the shift direction signals LC, RC, LR and RR which are applied to each driver unit FPDR of the cascade connections at the top of the columns, at the bottom of the columns, at the left of the rows and at the right of the rows respectively.
  • the serial control data signals applied to the columns stripes are a column clock signal CLKC, a column frequency signal FREQC, a column not enable signal ENC and a column select signal SELC. Since the driver units FPD R arranged along the top of the columns are connected to different stripes than those arranged along the bottom of these columns, additional serial information signals DATALC and DATARC are applied to these two cascade connections of driver units FPDR respectively.
  • serial information signals DATALC and DATARC associated with the previously mentioned serial control data signals are used to generate the above mentioned signals CSC, CC and CNC applied to the column stripes of the display LCD.
  • Serial control data and information signals similar to those applied to the column stripes are also applied to the row stripes.
  • These control data signals are a row clock signal CLKR, a row frequency signal FREQR, a row not enable signal ENR and a row select signal SELR.
  • additional serial information signals DATALR and DATARR are used together with the previous serial control data signals to generate the above mertioried signals RSC, RNSC and STROBE which are applied to the row stripes cf the display LCD.
  • a driver circuit FPDR is shown in detail in Fig. 4. It has control terminal D, terminals I1 to I5 and O1 to 05 and 30 output terminals OUTI/30 and includes 10 interface circuits IC1/10, a clock circuit CKC, a direction control circuit RLC, 30 logical devices LDl/30 and 30 high voltage devices HVD1/30.
  • Control terminal D is coupled through direction control circuit RLC to the internal busses RB and LB which control inputs DA, DB of all the interface circuit IC1/10 as well as inputs RB, LB of all the logic devices LDl/30.
  • Terminals I1 and O1 are connected to terminals AI, BO of LD1 and terminals AO, BI of LD30 via IC1 and IC6 respectively and the pairs of terminals I2, 02; I3, 03; I4, 04 and 15, 05 are connected to the internal busses SB, FB, EB and CKB via IC2, IC7; IC3, IC8; IC4, IC9 and IC5, IC10 respectively.
  • the busses SB, FB, EB are also connected TO the like named terminals of LDl/30 and the bus CKB is connected to an input of clock circuit CKC whose 4 outputs are connected to 4 corresponding inputs of LDl/30.
  • the latter devices LDl/30 each have three outputs INl to IN3 which are connected to like named inputs of HVDl/30 provided with outputs OUT1/30 respectively. These outputs are each connected to a row or column stripe of the display LCD.
  • the control terminal D of RLC is adapted to receive one of the above direction signals LC, RC, LR or RR indicating the direction in which the serial signals have to be shifted (right or left) into FPDR, as will be explained below.
  • the RLC then provides 2 complementary output signals R and L which are applied to the busses RB and LB respectively to inform the other circuits of FPDR of the shift direction.
  • This circuit RLC with input terminal D corresponding to the like named control terminal D of FPDR and output terminals R and L is constituted by a resistor Rl connected to input terminal D and to output terminal L via inverter INVl.
  • INV1 To the input of INV1 are also connected two clamping diodes D1 and D2 whose other ends are connected to a voltage supply terminal VDD (+12 Volts) and a ground terminal OV respectively.
  • a resistor R2 and output terminal R are also connected to the input of the invertor INVl, the other end of R2 being connected to V D D.
  • the input terminal D is permanently connected either to the ground terminal OV or left open.
  • Resistor Rl limits the possible current flowing through the clamping diodes D l or/and D2 when an undesirable voltage, e.g. static electricity, is applied to input terminal D.
  • an undesirable voltage e.g. static electricity
  • output terminals R and L are at logical levels O and 1 respectively.
  • output terminal R is pulled up to logical level 1 by supply terminal VDD and resistor R2, whilst output terminal L is then at O.
  • a logical value 1 at output terminal R indicates a shift right whilst a logical value 1 at output terminal L indicates a shift left.
  • Fig. 6 shows the clock circuit CKC having input terminal CKB connected to the like named internal clock bus CKB and having output terminals ⁇ 1, ⁇ 1 , ⁇ 2 and ⁇ 2 providing like named clock signals respectively.
  • CKC includes a NOR gate NOR1 which has its inputs connected to the terminals CKB and ⁇ 1, and another NOR gate NOR2 with its inputs connected to terminal ⁇ 2 and to terminal CKB via an inverter INV2.
  • the output of NOR1 is connected to ⁇ 2 via the series connection of inverters INV3 and INV4 and to ⁇ 2 via the series connection of inverters INV5 to INV7.
  • the output of NOR2 is connected to ⁇ 1 via the series connection of inverters INV8 and INV9 and to ⁇ 1 via the series connection of inverters INV10 to INV12.
  • F ig. 7 shows the input clock signal CKB which is either the column clock signal CLKC or the row clock signal CLKR, as mentioned above, and also shows the output clock signals ⁇ 1, ⁇ 1, ⁇ 2 and ⁇ 2.
  • the input clock signal CKB is a square wave applied to the like named input terminal CKB of clock circuit CKC via the input terminal I5 or 05, the corresponding interface circuit IC5 or IC10 and the internal clock bus CKB.
  • Output signals ⁇ 1 and ⁇ 2 are the respective complements of ⁇ 1 and ⁇ 2. Due to the cascade connections of the inverters of CKC, signals ⁇ 1 and ⁇ 2 are rectangular waves with positive portions smaller than the negative ones and the positive portions of signal ⁇ 1 occur in the middle of the negative portions of signal 02 and vice versa.
  • One of the above interface circuits IC1/10 is represented in Fig. 8 and indicated by IC. It has bond pad terminal BP connected to terminals Il/5 or 01/5, input and output terminals INI and OUTI respectively and control terminals DA and DB. The latter terminals DA and DB are controlled by the direction control circuit RLC via the internal busses RB and L B .
  • the circuit IC has also a voltage supply terminal VDD (+12 Volts) and a ground terminal OV.
  • Terminal BP is connected to the junction point of the series connected source-to-drain and drain-to-source path of .MOS transistors PM1 and NM1 respectively, the source electrode of PM1 being connected to voltage supply terminal VDD and the source electrode of NM1 being grounded.
  • the gate electrodes of these transistors PM1 and NM1 are respectively connected to the output of a NOR gate NOR3 and to the output of a NAND gate NAND1 each via an inverter INV13 and INV14 respectively.
  • One input of NOR3 is connected to control terminal DA and one input of NAND1 is connected to control terminal DB, whilst input terminal INI is connected to the other inputs of NOR2 and of NAND1 via inverter INV15.
  • Terminal BP is also connected to an input of another NAND gate NAND2 and to an input of another NOR gate NOR4.
  • NAND2 and of NOR4 are respectively connected to the control terminals DA and DB, whilst the outputs of these gates NAND2 and NOR4 are connected to the gate electrodes of MOS transistors PM2 and NM2 respectively.
  • PM1 and NMl the source-to-drain path of PM2 is connected in series with the drain-to-source path of NM2 and the source electrode of PM2 is connected to supply terminal VDD whilst the source electrode of NM2 is grounded.
  • output terminal OUTI is connected to the junction point of PM2 and NM2.
  • a logical value 1 must be applied to control terminal DA and a logical value O must be applied to control terminal DB of IC.
  • a logical value O applied to terminal BP causes a 1 at the outputs of NAND2 and NOR4 so that PM2 is blocked and NM2 is conductive which results in a logical value O or ground being applied to output terminal OUTI.
  • a similar operation occurs when logical values O and 1 are applied to the control terminals DA and DB respectively.
  • the transistors PM2 and NM2 are then blocked so that the output terminal OUTI is disconnected from terminal BP and that the logical value applied to the input terminal INI generates an identical logical value at terminal BP.
  • the input signals applied to the terminals BP or INI of this interface circuit IC are reshaped at the output.
  • inverter circuit contains less transistors than a logical gate (NAND or NOR), it is easier to realize a small output resistance for an inverter circuit. Therefore, inverters INV13 and INV14 having a small output resistance are placed between the output of the logical gates NOR3 and NAND1 and the gates of the MOS transistors PM1 and NM1 respectively.
  • a capacitance appears also between the terminal OUTI and the ground OV. However, this latter capacitance has a smaller value than the one at terminal BP.
  • the MOS transistors PM2 and NM2 are smaller than the MOS transistors PM1 and NM1, and the output resistances (not shown) coupled to the gate capacitances (not shown) of the transistors PM2 and NM2 are minimized in the logical gates NAND2 and NOR4 respectively so that no invertors are used for this part of the interface circuit IC .
  • One of the logical devices LDl/30 of Fig. 4 is represented in detail in Fig. 9 and indicated as LD. It has control terminals LB, RB, EB, FB and SB connected to the like named internal busses of the driver unit FPDR respectively and has output terminals IN1, IN2 and IN3 respectively connected to like named input terminals of a high voltage device HVD, as will be described later.
  • Logical device LD is also connected to the clock circuit CKC via terminals ⁇ 2 , ⁇ 2 and ⁇ 1 and ⁇ 1 carrying respective like named clock signals.
  • Logical device LD includes passing gates PGl to PG7 each constituted by a NM O S transistor and a PMOS transistor (schematically represented with a small circle on its gate electrode) whose source and drain electrodes are interconnected and whose gate electrodes are controlled by complementary control signals as described below.
  • Terminal AI of a logical device LD is connected to terminal BI of this same logical device LD via the series connection of two oppositely connected passing gates PGl and P G2 , each controlled by complementary direction signals applied to the control terminals LB and RB.
  • the junction point of these passing gates PGl and PG2 is connected to both terminals BO and AO of LD via the series connection of passing gate PG3 controlled by the complementary clock signals ⁇ 1 and ⁇ 1 , inverter INV16, passing gate PG4 controlled by the complementary clock signals ⁇ 2 and ⁇ 2 and another inverter INV17.
  • an inverter INV18 has its input connected to the output of inverter INV16 and its output connected to the input of inverter INV16 via passing gate PG5 controlled by the clock signals ⁇ 2 and ⁇ 2.
  • the output of PG3 is also connected to one input of a NAND gate NAND3 via passing gate PG6 which is controlled by complementary signals applied to it via control terminal EB directly and through an inverter INV19 respectively.
  • the output of PG6 is also connected to the input of inverter INV20 which is connected in series with inverter INV21 and to the output of passing gate PG7 whose input is connected to the output of inverter INV21 and which is controlled by signals which are the complement of those controlling PG7.
  • NAND3 which is also the output of passing gate PG6, and control terminal FB are the two inputs of an Exclusive NOR gate XNR.
  • the output of XNR is connected to one input of an AND gate ANDl directly and to one input of another AND gate AND2 via inverter INV22.
  • the other inputs of ANDl and AND2 are both connected to output terminal IN3 which constitutes the output of a AND gate AND3.
  • the two inputs of AND3 are the output of NAND3 and the output of INV19, whilst the second input of NAND3 is connected to the control terminal SB.
  • Output terminal IN1 is constituted by the output of AND2 and output terminal IN2 is constituted by the output of ANDl.
  • a logical value 1 applied to control terminal RB i.e. in case of a shift right operation, and consequently a logical value O applied to control terminal LB, close passing gate PGl and open PG2.
  • the input terminal for the above mentioned serial information signal DATALC, DATARC, DATALR or DATARR of the logical device LD is then AI and the output terminal is AO.
  • the input terminal of the driver unit FPDR (Fig. 4) is Il and its output terminal is O1 so that the serial information signal applied to Il is thus transmitted to O1 via the series connection of interface circuit IC1, its output terminal OUTI, terminal AI of LD1 :o terminal AO of LD30, input terminal INI of IC6 and interface circuit IC6 itself.
  • the values of the output signals IN1, IN2 and IN3 at the respective like named terminals IN1, IN2 and IN3 are dependent on the information signal DATALC/R or DATARC/R (Fig. 1) applied to terminal AI or BI (for the shift right or left) and on the control signals : not enable ENC/R ( F ig. 1) applied to terminal EB, select SELC/R (Fig. 1) applied to terminal SB and frequency FREQC/R (Fig. 1) applied to terminal FB, as will be described below.
  • passing gate PG6 opens and passing gate PG7 closes and the last information signal at the output of PG6 is latched in the circuit comprising inverters INV20 and INV21 and passing gate PG7, due to the high output capacitances (not shown) of these inverters.
  • the output signal IN3 is at O only when the select signal SELC/R at terminal SB and the information signal latched in INV20 and INV21 are both at logical value 1.
  • the values of the signals INI and IN2 may be represented by the following Boolean functions :
  • This high voltage device HVD represents either one of the 30 high voltage devices HVDl/30 of FPDR represented in Fig. 4. It has input terminals INl, IN2 and IN3 connected to the like named output terminals of the logical device LD respectively as well as voltage supply terminals VDD (+12 Volts), +Vl, -V2, +V3 and ground terminal OV. HVD also has output terminal OUT connected to a like named terminal of a stripe (row or column) of the display LCD.
  • the voltages applied to the terminals +V1, -V2 and +V3 are +150 Volts, -150 Volts and +170 Volts or +30 Volts, -30 Volts and +50 Volts depending on the kind of stripe (row or column) connected to terminal OUT and on the operation (scatter or clear) to be performed on that stripe, as described previously.
  • a stripe connected to HVD is represented in Fig. 10 by its equivalent circuit LCDE which comprises the series connection between the HVD terminal OUT and ground OV, of a resistor R3 and a resistor R4 in parallel with a capacitor Cl.
  • the high voltage device HVD comprises three circuits HVl, HV2 and HV3 among which HV1 and HV2 are identical. Therefore, only HV1 and HV3 will be described in detail hereinafter.
  • Circuit HVl has an input terminal TI and further terminals Tl, T2, T3 and T4. It includes a high voltage PNP transistor PI whose base electrode is connected to the junction point of resistors R5 and R6 which are branched in series between VDD and input terminal TI.
  • the emitter electrode of transistor Pl is directly connected to VDD and its collector electrode is connected to the gate electrode of a high voltage NMOS transistor NM3 as well as to terminal Tl via resistor R7.
  • the source electrode of transistor NM3 is directly connected to supply terminal -V2, whilst its drain electrode is connected to terminal T2 via resistor R8 and to the gate electrode of a second high voltage NMOS output transistor NM4.
  • the drain electrode of the latter transistor NM4 is directly connected to terminal T3 and its source electrode is connected to terminal T4.
  • input terminal TI is connected to input terminal INl of HVD
  • terminal T3 is connected to supply terminal +V1
  • terminal T4 is connected to output terminal OUT of HVD.
  • the input terminal TI of circuit HV2 is connected to input terminal IN2 of HVD and the terminals T3 and T4 of HV2 are connected to output terminal OUT and supply terminal -V2 respectively.
  • the terminals Tl and T2 of the two circuits HV1 and HV2 are connected to respective like named terminals Tl and T2 of circuit HVD3 described below.
  • the circuit HV3 has input terminal IN3 corresponding to the like named input terminal of HVD.
  • HV3 includes a NMOS transistor NM5 whose gate electrode is directly connected to terminal IN3, whose source electrode is connected to terminal OV and which has its drain electrode connected to the base electrode of a high voltage PNP transistor P2 via resistor R9.
  • the emitter electrode of transistor P2 is connected to terminal +V3 and to its own base electrode via biasing resistor R1O.
  • the collector electrode of transistor P2 is connected to the gate electrode of a high voltage NMOS transistor NM6 and to terminal T2.
  • the source electrode of transistor NM6 is connected to terminal -V2, whilst terminal Tl is connected to the drain electrode of NM6 via a clamping diode D3.
  • Terminal +Vl is also connected via resistor Rll to the junction point of the drain electrode of transistor NM6, the cathode of diode D3 and to the gate electrodes of a pair of high voltage NMOS output transistors NM7 and NM8 whose source electrodes are interconnected .
  • the drain electrode of output transistor NM7 is connected to terminal OV and the drain electrode of output transistor NM8 is connected to terminal OUT of HVD.
  • the purpose of this device is to provide at its output terminal OUT signals such as CSC, CC, CNC, RSC, RNSC or STROBE depending on the kind of stripe (row or column) to which terminal OUT is connected and also in function of the required operation (scatter or clear).
  • the voltages +Vl and -V2 may be applied to terminal OUT via_the output transistors NM4 of the circuits HVl and HV2, whilst the ground voltage OV may be applied to this output terminal OUT via the pair of output transistors NM7 and NM8, as will be explained below.
  • the selection of the supply voltage which has to be applied to the output terminal OUT is a result of the logical values applied to the input terminals IN1 to IN3.
  • transient short circuits between these supply voltages must necessarily be avoided, e.g. the two output transistors NM4 of the respective circuits HVl and HV2 may never be both conductive since otherwise the voltages +Vl and -V2 would be shorted.
  • the circuits HVl/3 are designed to block the output transistors NM4; NM7, NM8 faster than to make them conductive.
  • the three possible states of the high voltage device HVD indicated by the voltages at its output terminal OUT and corresponding respectively to various combinations of logical values applied to the input terminals IN1 to IN3 are analyzed in detail Hereinafter.
  • a logical value 1 is applied to input terminal IN3 and logical values 1 and O are applied to input terminals IN1/2 and IN2/1 respectively.
  • a third state the logical value at the input terminal IN3 is equal to zero and, consequently, also the other input terminals IN1 and IN2 are at zero.
  • Logical values 0 at all the input terminals INl to IN3 cause the output transistor NM4 of circuits HV1 and HV2 to be blocked and the pair of output transistor NM7, NM8 to be conductive so that the ground voltage OV is then applied to the output terminal OUT.
  • a logical value 1 applied to one of the input terminals IN1 or IN2 causes the operation of the corresponding output transistor NM4. Since in these conditions, input terminal IN3 must be at logical value 1 as described before, the pair of output transistors NM7, N M 8 is blocked so that the ground voltage is disconnected from the output terminal OUT.
  • the supply voltage +Vl or -V2 from the like named supply terminal, to which the above operating output transistor NM4 is connected is applied to the putput terminal OUT.
  • a scenario comprising the succession of the following logical values 1, O, 1 and O, 1, 1 at the respective input terminals IN1, IN2, IN3 will provide at the output terminal OUT of HVD the succession of voltages +Vl and -V2 respectively.
  • the latter succession of output voltages corresponds to one cycle of a signal such as CSC, CC, CNC, RSC, RNSC or STROBE mentioned above, as follows from Figs. 2 and 3.
  • the above mentioned two first states of the high voltage device HVD correspond always to a logical value 1 applied to input terminal IN3 and to complementary logical values applied to the input terminals IN1 and IN2 respectively.
  • a logical value 1 at input terminal IN1 and a logical value O at input terminal IN2 cause the voltage +Vl to be applied to output terminal OUT whilst the logical values O and 1 applied to the input terminals IN1 and IN2 respectively cause the voltage -V2 to be applied to output terminal OUT.
  • These two combinations of input signals are symmetrical due to the fact that the circuits HVl and HV2 are identical. Tkrefore, only one of them, say IN1 at 1 and IN2 at O will be explained in detail hereinafter.
  • transistors NM7 and NM8 are DMOS transistors
  • a parasitic diode (not shown) is coupled across their source and drain electrodes, this diode being inherent to the construction of these transistors.
  • Such a parasitic diode has its cathode electrode connected to the drain electrode of the DMOS transistor whilst the anode electrode of the diode is connected to the source electrode of the transistor. Since either a positive voltage up to +150 Volts or a negative voltage down to -150 Volts may be applied to the output terminal OUT by the circuits HV1 and HV2, these voltages also appear at the drain electrode of transistor NM8 since this electrode is connected to terminal OUT.
  • transistor NM8 instead of the pair of transistors NM7, NM8, e.g. by shorting the source electrode of transistor NM8 to ground terminal OV, a negative voltage at the drain electrode of this transistor NM8 (e.g. -150 Volts) will be grounded via then conductive parasitic diode of this transistor NM8. This happens independently of the state (conductive or blocked) of transistor NM8.
  • transistor NM7 is considered alone, e.g. by shorting the drain-to-source path of transistor NM8, a positive voltage at the terminal OUT (e.g. + 150 Volts) will be grounded via the parasitic diode of this transistor NM7.
  • transistors NM7 and NM8 have to be coupled in series opposition to effectively disconnect the output terminal OUT from the ground terminal Ov when a negative voltage is applied to the gate electrodes of this pair of transistors NM7, NM8 in order to block them.
  • transistor Pl conducts due to the logical value 0 applied to input terminal IN2.
  • Supply voltage VDD is thus applied to the gate electrode of transistor NM 3 via the emitter-to-collector path of conductive transistor Pl. Since the source electrode of transistor NM3 is connected to terminal -V2 and its drain electrode is connected to terminal +V3 via the emitter-to-collector path of transistor P2, terminal T2 and resistor R8, transistor NM3 becomes conductive.
  • the negative voltage -V2 is then applied to the gate electrode of output transistor NM4 of circuit HV2 via the drain-to-source path of conductive transistor NM3.
  • transistor NM4 of circuit HV2 blocks immediately, thus disconnecting terminal T4 which is also the supply terminal -V2 from output terminal OUT.
  • transistor Pl of circuit HV1 is blocked so that the gate electrode of NMOS transistor NM3 of circuit HV1 is disconnected from supply terminal VDD to which it was previously connected via the emitter-to-collector path of transistor Pl. Because transistor NM3 has a high gate capacitance, the latter discharges slowly to the voltage -V2 via high ohmic resistor R7 until this transistor NM3 blocks. At that moment the gate electrode of output transistor NM4 is disconnected from supply terminal -V2 and the high gate capacitance of this transistor NM4 is slowly charged to the positive voltage +V3 supplied thereto via the emitter-to-collector path of transistor P2, terminal T2 and resistor R8. After a while, output transistor NM4 of circuit HVl becomes conductive and applies the supply voltage +Vl to the output terminal OUT via its drain-to-source path.
  • the voltage +V3 is always equal to the voltage +Vl increased by about 20 Volts and for this reason the voltage +V3 at the gate electrode of conductive output transistor NM4 of circuit HVl is always higher than the voltage +Vl at its source electrode so that transistor NM4 remains conductive.
  • transistor NM5 of circuit HV3 is blocked, thereby preventing any current flow through resistors R9 and R1O so that transistor P2 blocks.
  • transistor NM6 has also a high gate capacitance, the voltage at the gate electrode of this transistor NM6 which was previously connected to supply terminal +V3 via transistor P2 decreases slowly.
  • terminal Tl is connected to terminal -V2 via diode D3 and the drain-to-source path of this transistor NM6 in series, whilst the positive voltage +V3 is available at the terminal T2 because of the previous charge of the gate capacitance of transistor NM6.
  • the voltage -V2 is also applied to the gate electrodes of the pair of output DMOS transistors NM7, NM8 via the drain-to-source path of transistor NM6.
  • This negative voltage (-V2) blocks NM7, NM8 and the above mentioned parasitic diodes associated to these transistors and coupled in series opposition inhibit any flow of current in both directions between the output terminal OUT and the ground terminal OV.
  • output terminal OUT is temporarily disconnected from any of the supply terminal +V1, -V2 and ground terminal OV. Since the gate electrode of transistor NM6 is disconnected from terminal +V3 due to the blocked transistor P2, the voltage at this gate electrode decreases slowly until transistor NM6 blocks. The voltage at the drain electrode of blocked transistor NM6, disconnected from terminal -V2, becomes slowly equal to +Vl due to the charging of the gate capacitances of the output transistors NM7 and NM8 via resistor Rll. This voltage +Vl is not applied to terminal Tl because of the blocking diode D3. The output terminal OUT is then connected to ground terminal OV.
  • These voltages are applied to the output terminal OUT of each HVD under the control of the logical values IN1 to IN3 of the signals at the like named input terminals IN1 to IN3 applied thereto via the output terminals IN1 to IN3 of logical device LD.
  • These logical values IN1 to IN3 are themselves controlled by the frequency signal FREQC or FREQR, the selection signal SELC or SELR and the serial information signal DATALC/R or DATARC/R latched by the inverters INV20 and INV21 in the logical device LD when the corresponding not enable signal ENC or ENR is low.
  • DATAR is either DATALR or DATARR
  • DATAC is either DATALC or DATARC
  • X means "don't care”.
  • the rows to be scattered have a logical value O as information signal DATAR while the rows which are not to be scattered have a logical value 1 as information signal DATAR, the resulting signal at the corresponding pixels being PSC and PNSC respectively.
  • the row selection signal SELR is always at logical value 1 while the column selection signal SEL C is still at O.
  • the clearing being performed one row at a time, the selected row has its information signal DATAR at logical value O and the associated columns are either at O or at 1 corresponding to the not clearing PNCL or to the clearing PCL of the pixel respectively.
  • the remaining rows i.e. those which are not addressed receive a logical value 1 as information signal DATAR.
  • the signals on the pixels of these rows are CNC or CC in function of the information signal DATAC on the corresponding column.
  • the other possible combinations of signals are not used in the present embodiment.
  • an active operation such as scattering or clearing is only performed when a logical value 0 is applied to a row stripe as information signal DATAR together with a logical value 1 applied to a column stripe as information signal DATAC.
EP84200778A 1984-05-30 1984-05-30 Circuits de commutation et dispositif à matrice utilisant ces circuits Withdrawn EP0162969A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP84200778A EP0162969A1 (fr) 1984-05-30 1984-05-30 Circuits de commutation et dispositif à matrice utilisant ces circuits
AU42703/85A AU4270385A (en) 1984-05-30 1985-05-21 Switching circuit for a l c d
JP11763085A JPS6150195A (ja) 1984-05-30 1985-05-30 スイツチング回路およびそれを使用するマトリツクス装置
BE2/60705A BE902538A (fr) 1984-05-30 1985-05-30 Circuits de commutation et dispositif materiel y utilise.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP84200778A EP0162969A1 (fr) 1984-05-30 1984-05-30 Circuits de commutation et dispositif à matrice utilisant ces circuits

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EP0162969A1 true EP0162969A1 (fr) 1985-12-04

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EP84200778A Withdrawn EP0162969A1 (fr) 1984-05-30 1984-05-30 Circuits de commutation et dispositif à matrice utilisant ces circuits

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JP (1) JPS6150195A (fr)
AU (1) AU4270385A (fr)
BE (1) BE902538A (fr)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0303510A2 (fr) * 1987-08-13 1989-02-15 Seiko Epson Corporation Dispositif d'affichage à cristaux liquides
EP0487742A1 (fr) * 1990-06-18 1992-06-03 Seiko Epson Corporation Panneau d'affichage plat et dispositif de pilotage des elements d'affichage
EP0506418A2 (fr) * 1991-03-29 1992-09-30 Oki Electric Industry Company, Limited Circuit de commande d'un affichage
US5175535A (en) * 1987-08-13 1992-12-29 Seiko Epson Corporation Circuit for driving a liquid crystal display device
US5179371A (en) * 1987-08-13 1993-01-12 Seiko Epson Corporation Liquid crystal display device for reducing unevenness of display
US5202676A (en) * 1988-08-15 1993-04-13 Seiko Epson Corporation Circuit for driving a liquid crystal display device and method for driving thereof
US5563624A (en) * 1990-06-18 1996-10-08 Seiko Epson Corporation Flat display device and display body driving device
WO2013038151A1 (fr) * 2011-09-14 2013-03-21 Cambridge Enterprise Limited Dispositif optique

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2149554B (en) * 1983-11-08 1987-04-01 Standard Telephones Cables Ltd Data terminals
WO1987007067A1 (fr) * 1986-05-13 1987-11-19 Sanyo Electric Co., Ltd. Circuit de commande d'un dispositif d'affichage d'images
JP2007307453A (ja) * 2006-05-17 2007-11-29 Hitachi Constr Mach Co Ltd リサイクル作業機

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0078402A1 (fr) * 1981-10-29 1983-05-11 Kabushiki Kaisha Toshiba Circuit de commande d'un panneau d'affichage comportant des éléments d'affichage disposés sous forme matricielle

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5541061A (en) * 1978-09-18 1980-03-22 Matsushita Electric Ind Co Ltd Television receiver
JPS5845034A (ja) * 1981-09-10 1983-03-16 Toshiba Corp 押え型製造用元型

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0078402A1 (fr) * 1981-10-29 1983-05-11 Kabushiki Kaisha Toshiba Circuit de commande d'un panneau d'affichage comportant des éléments d'affichage disposés sous forme matricielle

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0303510A2 (fr) * 1987-08-13 1989-02-15 Seiko Epson Corporation Dispositif d'affichage à cristaux liquides
EP0303510A3 (en) * 1987-08-13 1990-03-07 Seiko Epson Corporation Liquid crystal display device
US5298914A (en) * 1987-08-13 1994-03-29 Seiko Epson Corporation Circuit for driving a liquid crystal display device and method for driving same
US5175535A (en) * 1987-08-13 1992-12-29 Seiko Epson Corporation Circuit for driving a liquid crystal display device
US5179371A (en) * 1987-08-13 1993-01-12 Seiko Epson Corporation Liquid crystal display device for reducing unevenness of display
US5202676A (en) * 1988-08-15 1993-04-13 Seiko Epson Corporation Circuit for driving a liquid crystal display device and method for driving thereof
EP0487742A4 (en) * 1990-06-18 1993-01-27 Seiko Epson Corporation Flat displaying device and device for driving displaying elements
EP0487742A1 (fr) * 1990-06-18 1992-06-03 Seiko Epson Corporation Panneau d'affichage plat et dispositif de pilotage des elements d'affichage
US5563624A (en) * 1990-06-18 1996-10-08 Seiko Epson Corporation Flat display device and display body driving device
US5903260A (en) * 1990-06-18 1999-05-11 Seiko Epson Corporation Flat device and display driver with on/off power controller used to prevent damage to the LCD
USRE39236E1 (en) 1990-06-18 2006-08-15 Seiko Epson Corporation Flat panel device and display driver with on/off power controller used to prevent damage to the LCD
USRE40504E1 (en) 1990-06-18 2008-09-16 Seiko Epson Corporation Display and display driver with on/off power controller used to prevent damage to the display
EP0506418A2 (fr) * 1991-03-29 1992-09-30 Oki Electric Industry Company, Limited Circuit de commande d'un affichage
EP0506418A3 (en) * 1991-03-29 1993-07-14 Oki Electric Industry Company, Limited Lcd driver circuit
WO2013038151A1 (fr) * 2011-09-14 2013-03-21 Cambridge Enterprise Limited Dispositif optique

Also Published As

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BE902538A (fr) 1985-12-02
JPS6150195A (ja) 1986-03-12
AU4270385A (en) 1985-12-05

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