EP0148564B1 - Graphisches Videoanzeigesystem mit grosser Auflösung - Google Patents

Graphisches Videoanzeigesystem mit grosser Auflösung Download PDF

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Publication number
EP0148564B1
EP0148564B1 EP84307409A EP84307409A EP0148564B1 EP 0148564 B1 EP0148564 B1 EP 0148564B1 EP 84307409 A EP84307409 A EP 84307409A EP 84307409 A EP84307409 A EP 84307409A EP 0148564 B1 EP0148564 B1 EP 0148564B1
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Prior art keywords
bus
memory
address
video
signal
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French (fr)
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EP0148564A3 (en
EP0148564A2 (de
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Paul Schreiber
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Tandy Corp
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Tandy Corp
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
    • G09G5/06—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed using colour palettes, e.g. look-up tables

Definitions

  • the present invention relates in general to a high resolution video graphics system. More particularly, the invention pertains to such a high resolution system that is adapted for display of either black and white or colour and which is expandable in the number of colours displayed.
  • EP-A-0 085 480 to provide a video display system suitable for use in video games, for generating high resolution video images on a raster scanned video monitor having a matrix array of display positions including a processor having a bus, a video memory having a plurality of commonly addressed memory planes there being an address position in each of said memory planes for each of said display positions, each of said planes containing selected information concerning the display at the display position, video control means for generating address signals for said video memory in synchronisation with said raster scan, means for simultaneously reading information stored at an address position in all memory planes to control the display at the corresponding display position, multiplexer means with a first input to receive information from the bus of the processor, and a second input to receive said information read from the memory planes, a palette RAM means, and means for coupling the output of said multiplexer means as an address input to said palette RAM means, whereby to derive from said palette RAM means signals for video images either in dependence upon information derived from said memory planes or from said processor
  • An object of the present invention is to provide a new and unique bus architecture referred to herein as a split bus system.
  • the split bus system in particular pertains to the system write bus which is split into a plurality of separate buses corresponding to the number of memory planes employed.
  • the invention is accordingly characterised in that the processor has read bus means, and write bus means, and there are means for independently writing information into an address position in a selected memory plane including a write bus for each memory plane.
  • a high resolution video graphics system may interface with a processor to form a part of an overall computer system and in which the high resolution graphics system is substantially entirely transparent as far as the processor is concerned.
  • the invention is instead characterised in that the processor has a read bus, a write bus and latch means are provided for isolating the read bus from the write bus.
  • the number of memory addresses need not change with the number of memory planes employed.
  • the same number of memory addresses can be used regardless of the number of memory planes that are employed.
  • An embodiment of the invention described hereinafter with reference to the accompanying drawings comprises a high resolution video graphics system adapted for use in a computer system employing a processor.
  • the video portion of the system has the capability of displaying both graphics and alpha numeric characters.
  • the system employs the unique split bus architecture.
  • the split bus system is advantageous in reducing the total number of parts employed and also enables expandability of the system particularly with respect to the number of memory planes that are employed. With this technique there is provided very fast screen updates.
  • the split bus architecture means that there are actually a plurality of write buses.
  • the control bus couples signals from the processor to the high resolution video graphics circuitry. Typically, the control bus couples such signals as memory read and write signals, peripheral select signals and data ready signals. These signals are buffered and decoded to provide the proper memory timing.
  • the data communication between the processor and the graphics memory is provided by the read and write buses.
  • the read bus is isolated from the write bus so that the processor may read the graphics memory while simultaneously displaying data to the screen.
  • the write bus is preferably split from the read bus by a buffer means.
  • the write bus split into separate write buses then couples to the memory planes.
  • the write bus goes directly to the black and white plane which has been identified as plane 0 and is gated by bidirectional buffers splitting the bus into second and third buses for coupling to the respective buses.
  • the address bus which is coupled from the processor is used to read and write graphics data.
  • the addresses for the display data since they are sequential, are generated by a scan counter which provides column and row signals. These signals are coupled to a high speed multiplexer which selects between the addresses that are coupled to the memory. It selects between either scan counter addresses or processor generated addresses.
  • the system employs a split bus architecture to minimize the total number of components employed while at the same time providing an expandable upgrade path.
  • This technique permits fast screen updates, on the order of 23 million pixels per second.
  • the system employs four buses including a control bus, a read bus, a write bus, and an address bus. All of these buses intercouple with the central processing unit.
  • the control bus contains signals from the processor which may be a type 186 processor. These control bus signals may include such signals as memory read and write signals, peripheral select signals and data ready signals. These signals are buffered and decoded to provide proper memory timing as to be described in further detail hereinafter.
  • the address bus BUSAOO-BUSAl9 is coupled from the aforementioned 186 processor, and is used to read and write graphics data.
  • the addresses for the display data, since they are sequential, are generated by a 14 bit counter.
  • a very high speed 4:1 multiplexer selects between the addresses, where they go to the memories.
  • the system has three memory planes, each 16K by 16.
  • the outputs of the memories are fed to 16 bit shift registers, where the data is serialized. All the shift registers operate in parallel from common clocks. Ths shift register outputs go to a high speed static RAM as the address inputs to the RAM.
  • the data outputs of the RAM go to the guns on a color monitor which may be a standard CM-1 color monitor, or to the back plane for the black-white graphics on a VM-1 monitor. Further details are described hereinafter in connection with the aforesaid operation relating to the addressing and the video shift registers and associated RAM.
  • the second objective has the highest priority.
  • a user does not want the CRT monitor to blink rapidly, "hash" or go blank for any length of time.
  • the display objective is relatively critical.
  • graphic systems have been designed so that the host computer can access (read or write) data to the graphics memory only during certain times, so as not to disturb the CRT monitor.
  • the common way to accomplish this is to delegate accesses so as to allow them only during a blank time of the CRT beam; i.e. when the CRT beam is turned off. This occurs during retrace times, when the beam goes from the right side of the screen to the next line down on the left side (horizontal retrace), or from the lower right corner of the screen to the upper left corner of the screen (vertical retrace).
  • the aforementioned "hash" problem happens when the host computer is trying to access data at the same time that the graphics circuitry is loading the video shift registers. This may be referred to as "memory contention"; when two different circuits essentially vie over who has control of the memory.
  • the contention happens because processor access can happen virtually at any time, while shift register loading happens at a certain time frame.
  • the processor tries to access memory when the shift register is being loaded, the register is loaded with incorrect data (usually all ones) and the "hash" effect appears, at least for a brief instant of time on the screen.
  • the memory contention is eliminated by guaranteeing access when the shift register is not being loaded with data to be displayed. Since the shift register, once loaded, is not disturbed by the data being changed on its inputs, one can access memory while the data is being shifted out.
  • An interleaved memory is controlled by an interleave clock which divides the accesses up between the processor and the shift register.
  • an interleave clock which divides the accesses up between the processor and the shift register.
  • a 50% duty cycle clock 714 ns period.
  • This clock is identified by the signal DISCYC*.
  • the interleave clock divides the accesses into two equal time slots, each of 357 ns. This means that the processor has 357 ns to an access data and the shift registers have 357 ns to fetch the data to be displayed next. This may be referred to as a 1:1 interleave since the time slots are equal.
  • the previously referred to two accesses are carried out as follows.
  • the 186 processor address is used as the memory address.
  • Data is either written into memory or latched from memory.
  • the scan counter address is used to look up the data in all three memory planes. The shift registers are simultaneously loaded and then control goes back to the processor.
  • equation 1 The equation for the horizontal scan frequency of the video controller is given by equation 1:
  • the system of the invention has 400 visible lines.
  • the vertical display time is less than 16.66 ms, and depends on the size of the CRT that is being used. For a 13" tube, this time is 15.15 ms. Therefore, the horizontal scan rate is 26.403 KHz.
  • the number of horizontal dots is given as 640.
  • the horizontal display time is less than 37.87 us, which is the horizontal period. Since the SMC 9007 video display chip shown in FIG. 4 as circuit U16, which is providing the monitor signals, is character oriented, all the calculations for dot clock are based on this fact. First, the 640 dots are chosen so that 80 characters may be displayed, with each character having an 8 cell width. The CM-1 and VM-1 monitors require at least 2 us sync pulses; the aforementioned SMC 9007 chip can provide 8 character-wide sync pulses. Therefore, the 37.87 us horizontal time may be broken down into 80 characters displayed, eight characters for sync, and 18 for blanking (also due to monitor size). This gives the active display time as 28.59 us and a dot clock frequency of 22.3854 MHz.
  • this load is 714 ns.
  • a 1:1 interleave requires two time slots, each of 357 ns.
  • the data from the shift registers goes to a high speed static RAM referred to herein as a palette RAM.
  • This is identified in the drawing as RAM U16 which is of type 74Sl89A.
  • the palette RAM U16 holds a list of color data for the color monitor.
  • the palette RAM has its own input addresses taken either from the shift registers or the processor and also has a data input from the processor.
  • the output from the palette RAM U16 is a data bus to the video monitor, one data bit per gun.
  • the CM-1 monitor which is not shown in the drawings has four inputs which inputs are labeled in the drawing. These inputs are RED, GREEN, BLUE, and INTENSITY.
  • the palette RAM U16 has four data outputs.
  • the processor can load any of 16, four bit data values into the palette RAM, allowing any address from the shift registers to be any color. Reference is made to this important feature and a further discussion of the details that now follows.
  • FIGS. 1 and 2 The detailed circuitry described herein basically interfaces with two units, including the processor not actually shown herein, and a video monitor also not actually shown herein. It is understood that the video monitor is of conventional design and is a color monitor.
  • the processor has been identified previously as a 186 processor which is a 16 bit machine and which also is of conventional design. Interconnections are labeled in the drawing to indicate connections to and from these other components of the overall system.
  • the internal timing signals used in the video controller are derived from a 22.38 MHz dot clock whose output is buffered by means of the inverter U18 pins 10 and 11.
  • the output of this inverter is the signal DOT CLK.
  • the signal DOT CLK is coupled to video shift registers and also to the high speed counter U19.
  • the signal DOT CLK couples to the clock input at pin 11 of each of the shift registers U22, U24, U26, and U28.
  • the signal DOT CLK couples to the clock input at pin 2 of the counter or divider U19.
  • the delay line U31 is of type DDU4-5200 having three separate output taps at 40 ns, 80 ns and 120 ns.
  • the signal at pin 12 is coupled by way of inverter U18, pins 5 and 6 to provide the signal RAS*.
  • the signal is coupled by way of the inverter U18, pins 1 and 2 to provide the signal CAS*.
  • the signals RAS* and CAS * are for row and column address selection, respectively.
  • the signal DOT CLK is also divided by 16 to provide the signal DIS CYC and the negation signal DIS CYC* which is the aforementioned interleaving clock signal.
  • DIS CYC the negation signal
  • DIS CYC* which is the aforementioned interleaving clock signal.
  • This signal is also coupled by way of NOR gate U14 functioning as an inverter, pins 1, 2, and 3 to produce the signal DISCYC*.
  • the signal DOT CLK is different than a character clock signal generated from the central processing unit and is out-of-phase with this CPU signal. Because the SMC 9007 is used to generate the monitor timing signals (horizontal and vertical sync and blanking) using the out-of-phase character clock of the processor, there is the need for special circuitry to assure that these timing signals are synchronized.
  • a first circuit to carry this out is comprised of D flip-flop U64A. It is noted that the Q output at pin 5 of the flip-flop U64A connects to the load input at pin 9 of the counter U19.
  • the clock input to the flip-flop U64A is the signal 9007 DSYNC.
  • the master reset signal MRST- goes low for about 100 ms. This forces the counter U19 to load all zeroes to its outputs.
  • the Q output at pin 5 from the flip-flop 64A stays low until the signal MRST* goes away and then a vertical sync signal is issued.
  • the leading edge of the vertical sync signal sets the flip-flop U64A so that the Q output goes high, thus allowing the counter U19 to count. Because the vertical sync signal is aligned with the character clock of the SMC9007, this scheme lines up the graphics clock with the character clock; the graphics clock being the signal CCLK taken by way of inversion at an output of the counter U19 and previously referred to.
  • the monitor signals are also lined up using the four bit latch U70.
  • the latch U70 is clocked by the signal DIS CYC*.
  • the dynamic RAMS U2-U13 are clocked by delayed versions of the signal CCLK generated from the delay line U31.
  • the row address strobe signal RAS* is the signal CCLK inverted and delayed 45NS.
  • the signal MUX which switches the 4:1 address multiplexer between row and column addresses, is the signal RAS* delayed 40NS.
  • the address multiplexer just referred to is comprised of multiplexer devices U34-U37.
  • the column address strobe signal CAS* is the signal MUX delayed 40NS.
  • a plane select register U56 which is used to select which of the three planes is to be accessed by the processor. During display cycles, this register is essentially ignored.
  • the register U56 also provides control in the event that the video shift registers are enabled.
  • the register U56 also controls what video plane is accessed by the processor.
  • the signal GROF* couples to pin 1 of each one of each one of the latches U21, U23, U25, U27 and U39.
  • the signal G/A* couples to inverter gate S38 which in turn connects to gate U67 and pin 10.
  • the signal G/A* couples to gate F00A at pin 2 and to gate F00B at pins 4 and 5.
  • the output of gate F00A at pin 3 couples to one input of gate F00D.
  • the output of gate F00B at pin 6 couples to one input pin 9 of gate F00C.
  • Gate F00C at pin 10 also receives an output from the blanking delay register U63.
  • the register U63 is of type LS164 and is clocked from the signal DOTCLK.
  • the output of gate F00C at pin 8 forms the second input to the gate F00D.
  • the output of the gate F00D controls the color and intensity output gates U15A, U15B, U14A and U14B coupled from the output of the palette RAM U16.
  • the Palette RAM is of type 74Sl89A.
  • the high resolution graphics of the system of this invention provides 640 X 400 pixels on the VM-1 and CM-1 video monitors.
  • the system has 96K BYTES of high speed RAM for storage of graphics data and a user programmable color palette U16 for color assignment.
  • the graphics memory is organized in a planar fashion. If two color video is desired, then plane 0 is installed. Installing planes 1 and 2 provides 8 color video. As indicated previously, all three memory planes occupy the same physical address space. Thus, to determine which of the three planes the CPU is reading or writing to there is provided the aforementioned plane select register U56 which is set up prior to accessing the graphic's RAM.
  • the memory starts at address E0000H in the 186 address space. This address corresponds the upper left of the video screen. The next address is to the right. The lower right corner is the last address.
  • the full screen uses 32,000 BYTES or 16,000 words to fully describe a single plane.
  • the system responds to both BYTE and word accesses. Word accesses are on even addresses only. Either the high BYTE or the low BYTE may be transferred during BYTE accesses.
  • the graphics memory may be accessed at any time.
  • the high resolution circuitry uses WAIT states to synchronize the data transfer between the CPU and the graphics memory.
  • the average speed at which data is transferred is 16 BITS per us.
  • Each BIT of the graphics memory represents a DOT (pixel) on a video screen.
  • the MSB of the BYTE or word is the left most pixel.
  • the LSB is the last pixel to the right.
  • the video RAMS U10-U13 are associated with plane 0.
  • the video RAMS U2-U5 are associated with the plane 1.
  • the video RAMS U6-U9 are associated with plane 2.
  • the output signal P0VID at pin 12 from the shift register U28 Also note the output signal P1VID the output pin 12 from the shift register U20.
  • the output signal P2VID at the output pin 12 from the shift register U22 The signals P0VID, P1VID, and P2VID couple respectively to the multiplexers U17A, U17B and U17C. Each of these multiplexers may be of type 74F257 as noted in the drawing.
  • the video plane signals couple to the B input of each of these multiplexers.
  • the A inputs receive the respective signals PA1, PA2 and PA3.
  • the signals PA1, PA2 and PA3 are directly controlled CPU signals from the input address bus.
  • the palette RAM "looks up" a color by forming an address by using the data from each installed plane.
  • Plane 0 is palette address BIT A0
  • plane 1 is palette address BIT A1
  • plane 2 is palette address BIT A2.
  • Palette address BIT A3 as noted in the drawing is tied to a high voltage by way of a resistor at pin 13 to the palette RAM. This maintains the A3 input to the palette RAM at a high or one state. If a plane is not installed, the palette address BIT is a 1. Therefore, if plane 0 contains a 1, plane 1 a 0 and plane 2 a 0 the palette would "look up" the color at address 1001 in the palette memory.
  • the CPU may write the palette to change the color look up table.
  • the palette is located in the 186 processor I/O space and is on word (even address) boundaries.
  • the 186 processor uses PCS3 as the I/O port decode for graphics.
  • the palette appears to the programmer as 16 word addresses, starting at I/O address 0180H.
  • the palette is a write-only device.
  • I/O address 0180H is the first palette address
  • 0182H is the second, etc.
  • Data is stored in the palette by data BITS D0-D3.
  • the inputs to the palette RAM U16 signals RD0-RD3 to respective pins 4, 6, 10 and 12.
  • the control is carried out by means of a signal at pin 3 which is signal WR-PMS.
  • the upper data BITS are ignored.
  • these addresses are not the addresses formed to "look up" a color or a particular pixel. Those were addresses A0-A3 shown in the diagram of the palette RAM U16.
  • the four data outputs from the palette RAM, signals D01-D04 are taken at respective pins 5, 7, 9 and 11.
  • the SMC9007 video controller has a status register which reflects the status of the vertical synch signal. Also, the SMC9007 can provide interrupts to the CPU each vertical sync. It is up to the individual programmer which option is preferred.
  • the data in the palette RAM is tied to the video guns of the CN-1 color monitor in accordance with the table below. It can be seen that the data signal D0 controls the blue gun, D1 controls the green gun, D2 controls the red gun, and D3 controls half intensity. A “1" tor data D3 is full intensity and a "0" is half intensity.
  • the table shows possible colors verses data BITS.
  • the plane select register U56 is I/O mapped as address 01A0H. It is write only and is 6 BITS wide using data BITS D0-D5. In this regard, note the 6 inputs RD0-RD5 to the data inputs D0-D5 of the select register U56.
  • the register U56 is of type LS174.
  • the signals RD0-RD5 are derived from the CPU data bus signals BUS D00-BUS D05.
  • the plane select register U56 has basically three functions. First, it selects which plane of memory the CPU has access to. Only one plane at a time is selected. If more than one plane is selected then the register deselects all planes. Second, the register determines if the graphics planes are displayed or turned off. If they are turned off, the address into the palette is 08H, i.e. the plane data is forced to a 0. This does not erase the data in the planes, but simply forces the palette address to O8H. Third, the register determines if addresses into the palette are from the internal memory planes or from the SMC 9007 video memory.
  • a "1" is in the corresponding bit while the remaining two plane selects are “0". If plane 1 is to be selected, then data bits D0 and D2 contain a “0" while data bit D1 contains a “1".
  • the graphics on/off bit which is bit D4 contains a "1” to turn on (display) the graphics data in the installed planes. A “0” forces the palette to ignore the memory plane data and display the color contained at palette address 08H corresponding to processor 186 I/0 0190H.
  • the graphics/alpha bit, namely, data bit D5 determines which data is used as palette addresses. If this bit is a "1", the high resolution memory planes are used. If this bit is a "0", the data from the SMC9007 video controller is used for displaying text on the CM1 color monitor.
  • circuitry is provided for switching between the internal memory planes or external data for use as palette addresses.
  • the external data is hard wired on the bus as the SMC 9007 video and the video attribute bit intensity. If the external mode is selected, referred to as the alpha mode, the video data is palette address A0 and the attribute bit for intensity is palette address bit A1. Palette address bits A2 and A3 are tied high. This allows four color text to be displayed on the CM-1 color monitor.
  • a gated column address signal CAS* is used to selectively access the different memory planes.
  • the signal CAS 0HR associated with RAMS U6-U9 the signal CAS 1HR associated with RAMS U2-U5, and the signal CAS 2HR associated with the video RAMS U10-U13.
  • all of the planes receive the signal RAS*, a common write signal VWRR* and of course also receive memory addresses.
  • the signal CAS* couples to the memory control PAL U55 and is selectively gated in to access memory. Planes which do not receive the signal CAS* are refreshed by the signal RAS*.
  • the device U55 is a programmable logic array programmed to send the signal CAS* to each memory plane. The nature of the signal changes but it is noted at the output of the PAL U55 there are signals CAS OH at pin 18, CAS 1H at pin 16 and CAS 2H at pin 14. These signals couple to the package RP 4 and generate corresponding signals CAS OHR, CAS 1HR and CAS 2HR. It is this set of signals that controls the video RAMS as noted.
  • the 186 processor can do either byte or word transfers.
  • Two status lines are provided from the processor which tell external devices, the type of transfer which is about to occur. These signals include a bus high enable signal BHE* and the address line signal PAO.
  • the following chart shows how the lines are decoded: PAO BHE* TRANSFER 0 0 word 0 1 byte on D0-D7 1 0 byte on D8-D15 1 1 not used Note the signal BHE* coupled to pin 6 of the PAL U55 in the signal PA0 coupled to pin 7 of the PAL U55.
  • the signal BHE* couples from an input latch U61 relating to the CPU signal BUS BHE.
  • the pal U55 receives all of the aforementioned signals along with signal DIS CYC* and signal 186/SCN* and determines which plane is selected and then which of the memories receive the signal CAS*.
  • the second instance when a CAS* signal is sent is during a processor access when the signal 186/SCN* is high.
  • the PAL U55 looks at the status of the signals BHE* and PAO, but also checks the plane select register U56 and then the proper signal CAS* is then generated. The checking of the plane select register occurs by virtue of the inputs PP0, PP1 and PP2 that couple from register U56 to the PAL U55.
  • signals OE1* and OE2* are used to enable the bidirectional buffers U40, U41, U43 and U44.
  • Each of these buffers is of type 74F245. These buffers isolate the planes from each other. Plane 0 does not need such a buffer since it is on the bottom of the write bus. This topology allows any number of additional planes to be easily added. These signals go low when their associated plane is being accessed by the 186 processor.
  • the buffers U40 and U43 along with U41 and U44 have their terminals A0-A7 coupled to the write bus (WR-BUS). This is referred to herein also as the signal W2BUS.
  • W1D0-W1D15 associated with buffers U40 and U43
  • signals W0D0-W0D15 associated with bidirectional buffers U41 and U44.
  • 8 BIT latches U42 and U45 Each of these is of type 74LS374.
  • the data side of each latch corresponding to data terminals D0-D7 couples to the write bus WR-BUS.
  • the Q output sides identified as outputs Q0-Q7 coupled to the read bus. Note the signals RD0-RD15 coupling to the signal RD-BUS.
  • the graphics memory starts at system address E0000H. Although there are three 16K memory planes, each is mapped at address E0000H.
  • the comparator U51 which is a device of type 74LS85 having A inputs A0-A3 and B inputs B0-B3. The input B0 is tied to ground and inputs B1-B3 are tied to a positive voltage.
  • the address lines PA16-PA19 are coupled to the respective A0-A3 inputs of the comparator.
  • the comparator 51 looks at the addresses and issues a valid graphics memory address when an "E" is detected on the upper address lines.
  • the comparator is gated by the signal EQIN which is generated by the logic array U69.
  • the array U69 may be of type 825153 and may be a programmable array logic.
  • the comparator U51 is gated by the signal EQIN so that the false accesses are blocked when the SCM9007 controller is transferring video in memory.
  • the array U69 determines if a read or write is requested. Depending on the access, the signal BUFDIR* switches the data bus buffers U57 and U58 to the correct direction. Note the signal BUFDIR* at pin 17 at the array U69 coupling to pin 1 of the bidirectional data buffers U57 and U58. Also note the signal BUFEN* at the output pin 18 of the logic array U69. This signal enables the data bus for the access. This signal couples to the enable input at pin 19 of the buffers U57 and U58. The logic array U69 then asserts the signal MACC, signifying a valid memory access is requested. This signal couples to the memory arbitrator flip-flop U48 and also couples to gate U46 at pins 1 and 2.
  • the memory arbitration logic is comprised of two flip-flops U48 and U64.
  • the flip-flop U48 is a J-K flip-flop of type LS73.
  • Flip-flop U64 is a clocked D-type flip-flop of type F74.
  • the assertion output of the flip-flop U64 is the signal DATA-RDY.
  • the data input to the flip-flop U64 at pin 12 is the signal PUP which is taken from the counter U19.
  • the flip-flop U64 is clocked at pin 11 from the output of the gate U66 at pin 11.
  • the J-K flip-flop U48 has at its assertion output at pin 12 the signal 186/SCN*.
  • the K input to the flip-flop U48 is grounded and the J input is the signal MACC previously referred to.
  • the flip-flop U48 is clocked from the output of gate U30 at pin 8.
  • the gate U30, pins 8, 9 and 10 determines when the shift registers are loaded.
  • the assertion output of the flip-flop U48 also connects to gate U30 at pin 2 with the output of gate U30 at pin 3 being the read latch signal RDLTH.
  • the negation output from the flip-flop U48 couples to gate U66 at pin 5.
  • the other input to the gate U66 at pin 4 receives a signal VMWR*.
  • the output from the gate U66 at pin 6 is the signal VWR*.
  • This signal controls, inter alia, the buffers U59 and U60.
  • the gate U66 pins 4-6 assumes that the signal VWR* is asserted only upon a write request.
  • the gates U66 pins 8-10 and U66 pins 11-13 determine the end of access and involve a resetting of the flip-flop U48.
  • the output of the gate U66 at pin 11 also clocks the flip-flop U74.
  • the system of the invention uses a "data ready" handshake scheme for external memory.
  • the 186 processor automatically goes into a WAIT state after requesting access. It is then up to the external memory to assert the signal ARDY when the access is completed. The processor then goes out of the WAIT state, and the external device clears the data-ready signal before the next processor 186 memory cycle.
  • the gate U66 pins 4, 5 and output pin 6 makes sure that the signal VWR* is asserted only if a write has been requested. Also, the Q output of pin 12 from flip-flop U48 is gated with the signal RAS* to form the read latch signal RDLTH which clocks the two 8 BIT latches on the read bus, namely latches U42 and U45. Note the input clock signal at pin 1 which is a signal RDLTH coupling to both 8 BIT latches U42 and U45. These latches may be of type 74LS374.
  • the address multiplexers U34-U37 each have A and B inputs.
  • the aforementioned signal 186/SCN* is coupled in common to all of the B inputs of these multiplexers. When this signal is high it switches the multiplexers from the scan counter addresses to processor generated addresses.
  • the input A inputs are tied in common from the signal MUX.
  • the R0-R7 signals and C0-C5 signals are the scan counter signals and the processor generated addresses are the PA1-PA14 addresses.
  • pins 5 and 6 along with pins 10 and 11 receive scan counter addresses and pins 3 and 4 along with pins 12 and 13 receive processor generated addresses. From the multiplexers the signals are identified as signal VA4 at pin 9 and VA5 at pin 7. Similar arrangements occur with respect to the other multiplexers U34, U36 and U37.
  • the end of an access is basically determined by the gates U66, pins 8-10 and 11-13.
  • the end of an access is determined when the signals CCLK and MUX are both low.
  • the flip-flop U64 is clocked from the output of gate U66 at pin 11 thus asserting the data ready signal DATA-RDY.
  • This signal is driven to the bus in an inverted state by open collector driver U67, pins 1-3.
  • the control then waits until the processor acknowledges the access.
  • the signal MACC then goes low after the access, which clears the flip-flop U64 by way of gates U46, pins 1-3 and U46 pins 4-6. This then drops the data ready signal DATA-RDY.
  • the cycle is now completed and the logic is ready for the next request.
  • the signal SCNCLK is derived from the signal CBLANK* and also from the two inputs to the gate U30 at pins 4 and 5, namely, the signals MUX and DISCYC*.
  • the output of gate U30 at pin 6 couples to pin 12 of gate U46.
  • Gate U46 at pins 9 and 10 are tied together and this gate functions as an inverter with the output at pin 8 being the signal SCNCLK for clocking the scan counter.
  • the scan counter is reset each vertical retrace from the flip-flop U48A at its Q output, pin 8.
  • the flip-flop U48A is of type LS73 and is a J-K flip-flop.
  • the J input is tied to a positive voltage and the K input is tied to ground.
  • the clock input at pin 5 to the flip-flop U48A is the signal VSYNC*.
  • the output from the flip-flop U48A at pin 8 ties to the clear inputs of each stage of the scan counter at pin 1.
  • the vertical sink signal VSYNC* clears the counters to scan address 0 corresponding to processor address E0000H until the signal CBLANK goes low thereby clearing the flip-flop U48A. Note the signal CBLANK coupling to the reset input of the flip-flop U48A.
  • the signal CBLANK is the composite blank signal, and is low during active display time.
  • the scan counters U32, U33, U49 and U50 are clocked by the signal DISCYC* gated by the signal MUX and the signal CBLANK*.
  • This clocking signal is the aforementioned signal SCNCLK.
  • the gating occurs by way of the aforementioned gate U46 pins 8-10, gate U46 pins 11-13 and gate U30 pins 4-6. This clocking assures that the counters advance during active display times.
  • the scan counters produce 8 row outputs R0-R7 corresponding to the scan counters U32 and U33.
  • the outputs R0-R3 are from the counter and the outputs R4-R7 are from the counter U33.
  • the scan counter also produces six column outputs C0-C5.
  • the row outputs couple as follows. Signals R0 and R1 to multiplexer R37, signals R2 and R3 to multiplexer R36, signals R4 and R5 to multiplexer R35 and signals R6 and R7 to multiplexer U34. With respect to the column outputs, output C0 couples to mulitplexer U37, outputs C1 and C2 couple to multiplexer U36, outputs C3 and C4 couple to multiplexer U35 and output C5 couples to multiplexer U34.
  • the column and row outputs always couple to the 0 and 1 inputs of these multiplexers either at pins 5 and 6 or at pins 10 and 11. These are the scan counter inputs to the multiplexers.
  • the processor inputs are at pins 3, 4, 12 and 13.
  • the graphics memory is comprised of 12 dynamic RAMS. Each dynamic RAM is of type TMS 4416-15 and each is a 16K by 4 dynamic RAM.
  • the graphics memory is arranged in three planes. The first plane is comprised of RAMS U10-U13, the second plane is comprised of RAMS U2-U5 and the third plane is comprised of RAMS U6-U9.
  • the plane 0 is the black and white plane and as mentioned is comprised of RAMS U10-U13.
  • the other memory planes are added to upgrade to color.
  • Each plane has four RAMS and also comprises two latches of type 74LS273 and also two shift registers of type 25LS22. Thus, the plane 0 has latches 27 and 29 and shift registers 26 and 28.
  • the plane 1 has latches U21 and U39 and shift registers U20 and U38.
  • the plane 2 has latches U23 and U25 and shift registers U22 and U24.
  • the latches of type 74LS273 have a clock input which receives the signal LD-VID. These latches also receive the signal GROF*.
  • the shift registers are loaded by means of the signal S/L*.
  • the output plane video signals are taken at pin 12 of one of the shift registers of each pair.
  • the signal P0VID is taken at pin 12 of shift register U28.
  • the signal P1VID is taken at the output pin 12 of the shift register U20.
  • the signal P2VID is taken at the output pin 12 of the shift register U22.
  • These signals P0VID, P1VID and P2VID couple to the multiplexers U17A, U17B and U17C. These multiplexers also receive processor addresses PA1, PA2 and PA3 respectively.
  • bus isolation buffers U40-U44 In addition to the latches and shift registers, there are also provided bus isolation buffers U40-U44. These buffers are associated only with planes 1 and 2. It is noted that the write bus (signal WR-BUS) couples directly to the latches U27 and U29. However, the write bus couples by way of bus isolation buffers U40 and U43 to the bus W1-BUS, and also couples by way of bus isolation buffers U41 and U44 to the bus W0-BUS.
  • the bus isolation buffers U40-U44 are necessary because during display cycles all three planes are simultaneously reading data out of their memorys into the latches, therefore, each plane needs a dedicated path its associated latches. Also, the particular type of RAM used has common I/O pins, so data input from the processor cannot be separated from the data going to the latches.
  • the multiplexer selects which address lines go to the palette RAM U16. It selects between processor information represented by the signals PA1, PA2 and PA3; and shift register data as represented by the signals P0VID, P1VID and P2VID.
  • control is provided from the signal WR-PAL*.
  • This signal is normally high and thus the shift register outputs form the palette address.
  • the signal WR-PAL* goes low, switching the multlplexer to the processor 186 addresses.
  • the signal WR-PM* which controls the read/write operation of the palette RAM U16.
  • a buffer that permits direct character data from the 9007 video controller.
  • the singals AGVID and AINT couple to the drivers U1 at respective pins 5 and 12.
  • These drivers are enabled from a signal at the output of the gate U67 at pin 8 derived from the graphics/alpha numerics signal G/A* under control of the signal WR-PAL which is the assertion of the signal used for control of the multiplexers.
  • a shift register U63 which is of type LS164 and which is used to delay the original blanking signal which is the signal 9007 BLANK shown on the drawing and inputted into the shift register U63.
  • the signal DOTCLK controls the clocking of the the blanking shift register U63.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
  • Transforming Electric Information Into Light Information (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Claims (9)

  1. System zur Erzeugung von hochaufgelösten Videobildern auf einem rastermäßig abgetasteten Video-Monitor (CM-1 oder VM-1) mit einer Matrixanordnung von Wiedergabepositionen, das folgende Bestandteile umfaßt: Einen Prozessor (186), der einen Adressen-Bus (BUS-A) aufweist, einen Video-Speicher, der eine Vielzahl von gemeinsam adressierten Speicherebenen (U2-5, U6-9, U10-13) besitzt, wobei für jede der Wiedergabepositionen eine Adressenposition in jeder der Speicherebenen vorhanden ist und jede Speicherebene ausgewählte Informationen bezüglich der Wiedergabe an der Wiedergabeposition enthält, Video-Steuereinrichtungen (U32-33, U49-50) zur Erzeugung von Adressensignalen für den Video-Speicher in Synchronisation mit der rastermäßigen Abtastung, Einrichtungen (U20, U22, U28) zum gleichzeitigen Lesen von Informationen (P0VID, P1VID, P2VID) die an einer Adressenposition in allen Speicherebenen gespeichert sind, um die Wiedergabe an der entsprechenden Wiedergabeposition zu steuern, Multiplexer-Einrichtungen (U17) mit einem ersten Eingang (A) zum Empfang von Information (PA1, 2, 3) vom Adressenbus (BUS-A) des Prozessors und einem zweiten Eingang (B) zum Empfang der von den Speicherebenen gelesenen Informationen (P0VID, P1VID, P2VID), eine Paletten-Speicher-Einrichtung mit wahlfreiem Zugriff (U16), und eine Einrichtung zum Koppeln des Ausgangs (Y) der Multiplexer-Einrichtung (U17) als Adresseneingang an die Paletten-Speicher-Einrichtung mit wahlfreiem Zugriff (U16), um somit von der Paletten-Speicher-Einrichtung mit wahlfreiem Zugriff Signale für Videobilder in Abhängigkeit von Informationen abzuleiten, die entweder von den Speicherebenen oder von dem Prozessor-Adressen-Bus abgeleitet sind, dadurch gekennzeichnet, daß der Prozessor Lese-Bus-Einrichtungen (RD-BUS) und Schreib-Bus-Einrichtungen (WR-BUS) umfaßt, und daß Einrichtungen vorhanden sind, die zum unabhängigen Schreiben von Informationen in eine Adressenposition in einer ausgewählten Speicherebene einen Schreib-Bus (WD) für jede Speicherebene umfassen.
  2. System nach Anspruch 1, bei dem Mehrfach-Ausgangsleitungen von der Paletten-Speicher-Einrichtung mit wahlfreiem Zugriff vorhanden sind, die Farb-Erzeugungsleitungen (BLUV, GRNV, REDV) und eine Intensitätsleitung (INTV) umfassen.
  3. System nach Anspruch 1 oder 2, weiterhin gekennzeichnet durch einen Speicherebenen-Adreß-Multiplexer (U34-37) und eine Einrichtung zum Anlegen des Ausgangs von der Video-Steuereinrichtung (U32, 33, 49, 50) und des Adreß-Busses (PA) vom Prozessor als Eingänge an den Speicherebenen-Adreß-Multiplexer, und Einrichtungen zum Anlegen des Ausgangs vom Speicherebenen-Adreß-Multiplexer als den Adresseneingang an den Videospeicher (U2-13).
  4. System nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß eine Einrichtung vorgesehen ist, die zum Separieren der Speicherebenen-Schreib-Busse Trenn-Puffer (U40, 41, 43, 44) umfaßt, die zwischen den Schreib-Bussen angeordnet sind, um separierte Schreib-Busse abzugrenzen, die der Anzahl der Speicherebenen entsprechen.
  5. System nach einem der vorhergehenden Ansprüche, weiterhin dadurch gekennzeichnet, daß eine Verriegelungseinrichtung (U21, 23, 25, 27, 29, 39) zum Trennen des Schreib-Busses vom Lese-Bus vorgesehen ist.
  6. System nach einem der vorhergehenden Ansprüche, das Schieberegister-Einrichtungen (U20, 22, 28) für die jeweiligen Speicherebenen, Einrichtungen zum parallelen Anlegen von Informationen, die aus jeder Speicherebene ausgelesen sind, an die entsprechende Schieberegister-Einrichtung, und Einrichtungen (DOTCLK) umfaßt, die dazu dienen, die Inhalte einer jeden Schieberegister-Einrichtung in serieller Weise auszulesen.
  7. System zur Erzeugung hochaufgelöster Videobilder auf einem rastermäßig abgetasteten Video-Monitor (CM-1 oder VM-1), der eine Matrixanordnung von Wiedergabepositionen aufweist, wobei das System folgende Bestandteile umfaßt: Einen Prozessor (186) mit einem Adressen-Bus (BUS-A), einen Video-Speicher mit einer Vielzahl von gemeinsam adressierten Speicherebenen (U2-5, U6-9, U10-13), wobei für jede der Wiedergabepositionen eine Adressenposition in jeder der Speicherebenen vorhanden ist und jede der Ebenen ausgewählte Informationen enthält, die die Wiedergabe an der Wiedergabeposition betreffen, Video-Steuereinrichtungen (U32-33, U49-50) zur Erzeugung von Adressensignalen für den Video-Speicher in Synchronisation mit der rastermäßigen Abtastung, Einrichtungen (U20, U22, U28) zum gleichzeitigen Lesen von Informationen (P0VID, P1VID, P2VID) die an einer Adressenposition in allen Speicherebenen gespeichert sind, um die Wiedergabe an der zugehörigen Wiedergabeposition zu steuern, Multiplexer-Einrichtungen (U17) mit einem ersten Eingang (A) zum Empfang von Informationen (PA1, 2, 3) vom Adressen-Bus (BUS-A) des Prozessors und einem zweiten Eingang (B) zum Empfang der aus den Speicherebenen ausgelesenen Informationen (P0VID, P1VID, P2VID), eine Paletten-Speicher-Einrichtung (U16) mit wahlfreiem Zugriff, und Einrichtungen zum Verbinden des Ausgangs (Y) der Multiplexer-Einrichtung (U17) als Adresseneingang mit der Paletten-Speicher-Einrichtung (U16) mit wahlfreiem Zugriff, um auf diese Weise von den Paletten-Speicher-Einrichtungen mit wahlfreiem Zugriff Signale für Videobilder in Abhängigkeit von Informationen abzuleiten, die entweder von den Speicherebenen oder von dem Prozessor-Adressen-Bus abgeleitet sind, dadurch gekennzeichnet, daß der Prozessor (186) einen Lese-Bus (RD-BUS) und einen Schreib-Bus (WR-BUS) umfaßt, und daß Verriegelungseinrichtungen (U21, 23, 25, 27, 29, 39) vorgesehen sind, um den Schreib-Bus vom Lese-Bus zu isolieren.
  8. System nach einem der vorhergehenden Ansprüche, das einen Steuer-Bus für den Prozessor (186) umfaßt.
  9. System nach einem der vorhergehenden Ansprüche, weiterhin dadurch gekennzeichnet, daß die Video-Steuereinrichtung Video-Zählereinrichtungen (U32-33, U49-50) erfaßt, um Adressensignale für den Videospeicher in Synchronisation mit der rastermäßigen Abtastung zu erzeugen.
EP84307409A 1983-11-29 1984-10-26 Graphisches Videoanzeigesystem mit grosser Auflösung Expired - Lifetime EP0148564B1 (de)

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AT84307409T ATE75872T1 (de) 1983-11-29 1984-10-26 Graphisches videoanzeigesystem mit grosser aufloesung.

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US55617883A 1983-11-29 1983-11-29
US556178 1983-11-29

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US4771275A (en) * 1983-11-16 1988-09-13 Eugene Sanders Method and apparatus for assigning color values to bit map memory display locations
JP2526857B2 (ja) * 1984-12-27 1996-08-21 ソニー株式会社 画像信号変換方法
WO1986006234A1 (en) * 1985-04-12 1986-10-23 Ampex Corporation Apparatus and method for processing previously processed video signals
US4783652A (en) * 1986-08-25 1988-11-08 International Business Machines Corporation Raster display controller with variable spatial resolution and pixel data depth
AU602213B2 (en) * 1987-05-28 1990-10-04 Digital Equipment Corporation Computer work station including video update arrangement
US4851826A (en) * 1987-05-29 1989-07-25 Commodore Business Machines, Inc. Computer video demultiplexer
US5091721A (en) * 1988-12-22 1992-02-25 Hughes Aircraft Company Acoustic display generator

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JPS559742B2 (de) * 1974-06-20 1980-03-12
US4092728A (en) * 1976-11-29 1978-05-30 Rca Corporation Parallel access memory system
US4342029A (en) * 1979-01-31 1982-07-27 Grumman Aerospace Corporation Color graphics display terminal
FR2463555A1 (fr) * 1979-08-14 1981-02-20 Option Sa Dispositif d'affichage permanent d'information graphique sur un ecran de television et de transmission simultanee sur ligne telephonique
JPS5716487A (en) * 1980-04-11 1982-01-27 Ampex Computer graphic system
GB2090506B (en) * 1980-11-12 1984-07-18 British Broadcasting Corp Video colour graphics apparatus
GB2112256B (en) * 1981-11-18 1985-11-06 Texas Instruments Ltd Memory apparatus
EP0085480A3 (de) * 1982-01-13 1986-01-08 Europel Systems (Electronics) Ltd. Video-Anzeigesysteme
JPS5960488A (ja) * 1982-09-29 1984-04-06 フアナツク株式会社 カラ−グラフイツクメモリのデ−タ書き込み装置

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DE3485705D1 (de) 1992-06-11
EP0148564A2 (de) 1985-07-17
AU3475184A (en) 1985-06-06
ATE75872T1 (de) 1992-05-15
CA1237207A (en) 1988-05-24

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