EP0142935A2

EP0142935A2 - Voice recognition interval scoring system

Info

Publication number: EP0142935A2
Application number: EP84307003A
Authority: EP
Inventors: Takehiro Ishikawa; Toshio Sakata; Nobuo Obara
Original assignee: Seiko Instruments Inc
Current assignee: Seiko Instruments Inc
Priority date: 1983-10-24
Filing date: 1984-10-12
Publication date: 1985-05-29
Also published as: EP0142935A3; JPS6090396A

Abstract

A voice recognition interval scoring system comprises a pitch extractor (3) for extracting at least a fundamental pitch of the wave of a voice or a musical sound, a processor (CPU) for transducing pitch data generated by the pitch extractor into a musical interval, a memory (4) for storing the result of the processor, and a note indicator (5) with a musical sound generator (6) for visually or audibly expressing the content of the memory.

Description

This invention relates to voice recognition interval scoring systems, for example, for scoring intervals of a voice singing a song or for reproducing the scored interval in a musical sound waveform.
The present invention seeks to provide a voice recognition interval scoring system having a small sized microprocessor and hardware and scoring the interval of a voice or musical sound efficiently, easily and precisely and making it possible to correct scored interval data easily.
According to the present invention there is provided a voice recognition interval scoring system characterised by comprising:

pitch extracting means for extracting at least the fundamental pitch of the wave of a voice or a musical sound; transducing means (_CPU) for transducing pitch data generated by said pitch extracting means into a musical interval; memory means for storing the result of said transducing means; and interval reproducing means for visually or audibly expressing the content of said memory means.

Said interval reproducing means mean include a musical sound generator for producing a plurality of musical sound waves.
The voice recognition interval scoring system may comprise correcting means for correcting interval data stored in said memory means. Said correcting means may include a switch for selecting an address of said memory means and a switch for changing the interval of the address selected.
In a preferred embodiment there is provided an external switch for setting reproduction at an octave-shift action when the content of saidmemory means is produced by said interval reproducing means.
Preferably a voice recognition interval scoring system includes a tempo generator, said pitch extracting means operating in response to a tempo signal from said tempo generator and being inhibited until said voice or musical sound is applied.
Said pitch extracting means may comprise an inverting circuit for inverting the wave of said voice or said musical sound, a first peak hold circuit, a second peak hold circuit and a flip-flop controlled by said first peak hold circuit and said second peak hold circuit, said first peak hold circuit in operation detecting a positive peak of said wave of said voice or said musical sound, said second peak hold circuit in operation detecting a positive peak of the output of said inverting circuit so that a period of said voice or said musical sound is detected by measuring the period of the output of said flip-flop.
The invention is illustrated, merely by way of example, in the accompanying drawings, in which:-

Figure 1 is a block diagram of a voice recognition interval scoring system according to the present invention;
Figure 2 is an exterior view showing a LED note indicator of the interval scoring system of Figure 1;
Figure 3 is a diagram showing details of a voice pitch extractor of the interval scoring system of Figure 1;
Figure 4 is a timing chart illustrating the operation of the voice pitch extractor of Figure 3;
Figure 5 is a diagram showing details of a note indicator of the interval scoring system of Figure 1;
Figure 6 is a diagram showing details of a portion of the note indicator of Figure 5;
Figure 7 is a timing chart illustrating the operation of the note indicator of Figure 5;
Figure 8 is a block diagram of a musical sound generator of the interval scoring system of Figure 1;
Figure 9 is a diagram of a switch unit of the interval scoring system of Figure 1;
Figure 10 is a diagram of a portion of the switch unit of Figure 9;
Figure 11 is a diagram showing details of a tempo generator of the interval scoring system of Figure 1; and
Figure 12 is a timing chart illustrating the operation of the tempo generator of Figure 11.

The present invention relates to a voice recognition interval scoring system for scoring the interval of a voice singing a song and for reproducing the scored interval in, for example, a musical sound waveform.
In the case of a song which is audibly sung, it never fails to result in that the interval of the voice goes out of tune. This is because the singer does not make voice sounds in an accurate interval. This scoring scarcely makes a song if it is reproduced unchanged. The present invention contemplates providing correcting means for easily correcting interval data scored and to correct the interval in a correcting mode by shifting cursors at portions to be corrected.
Figure 1 is a block diagram of one embodiment of a voice recognition interval scoring system according to the present invention. The interval scoring system has a CPU 1, and an address decoder 2, a voice pitch extractor 3, a RAM 4, a note indicator 5, a musical sound generator 6, a switch unit 7 and a tempo generator 8.
The CPU 1 has its address signal AD connected with the address decoder 2, and a data bus DATA BUS connected commonly with data terminals of the voice pitch extractor 3, the RAM 4, the note indicator 5, the musical sound generator 6 and the switch unit 7. Moreover, the CPU 1 provides a signal RD to respective terminals RD of the voice pitch extractor 3, the RAM 4 and the switch unit 7 and provides a signal WR to respective terminals WR of the RAM 4, the note indicator 5 and the musical sound generator 6.
From the address decoder, a signal ADO is connected with the voice pitch extractor 3, a signal AD1 is connected with the ram 4, signals _AD2 to AD9 are connected with the note indicator 5, the signal AD10 is connected with the musical sound generator 6, and signals AD11, AD12 are connected with the switch unit 7. A voice inputting microphone MIC is connected with a terminal IN of the voice pitch extractor 3, a signal φL as the output of the voice pitch extractor 3 is fed to the tempo generator 8. A signal TEMP as the output of the tempo generator 8 is fed to an interruption terminal INT of the CPU 1.
Next, the operation of the individual blocks of the interval scoring system of Figure 1 will be briefly described. The address decoder 2 judges what block the CPU 1 is working for at present and selects one of the blocks. The voice pitch extractor 3 is selected by the signal ADO from the address decoder 2 to amplify the voice signal inputted from the microphone MIC, to detect the peak of the fundamental wave of that voice waveform, to measure the time period from peak-to-peak, and to score the measured value. If necessary (i.e. when the CPU 1 selects the signal ADO), moreover, the data is superposed on the data bus DATA BUS. On the other hand, the signal φL as shown is generated only with the voice input, and this period is substantially equal to the pitch period of the voice input waveform.
The _RAM 4 is selected by the signal AD1 from the address decoder 2. In the case of the RAM 4, there are generally a plurality of address input terminals which are accessed only with the signal AD1. Of course, a plurality of address signals are connected from the CPU 1 to the RAM 4 but are not shown in Figure 1. Therefore, the signal AD1 is shown as a chip select signal of the RAM 4. The connections between a CPU and a RAM are already well known and so will not be described further.
The RAM 4 stores musical scale data after pitch data obtained from the voice pitch extractor 3 has been judged and transduced by the CPU 1. Specifically, the CPU 1 stores scale data which is obtained from the voice pitch extractor 3, consecutively in the RAM 4. When the scale data stored is to be corrected or reproduced, moreover, the CPU 1 consecutively reads out and processes the data stored in the RAM 4.
The note indicator 5 consecutively indicates a portion of the data stored in the RAM 4 and is constructed of a liquid or LED indicator and a drive circuit.
Figure 2 is an exterior view of the note indicator 5 constructed of LEDs. LEDs corresponding to individual musical scales are mounted on a staff notation so that musical scales up to eight tones may be displayed simultaneously as a whole. Moreover, LEDs for sharps are also mounted for indicating half tones.
The musical sound generator 6 recognises the scale data stored in the RAM 4 and transduces it into musical tones and has a function arbitrarily to select a plurality of musical sounds. In the musical sound generator 6, the scale data stored in the RAM 4, which is instructed by the CPU 1, is transduced into musical sound signals which are amplified by a filter unit and an amplifier unit to drive a speaker, none of these being shown in the drawings.
The switch unit 7 comprises a mode switch for setting the recording, correcting and reproducing modes, start and end switches for the respective modes, a cursor shifting switch for the correcting mode, an octave shift switch for correction or reproduction, and a tune correcting switch for correcting the tune of a musical scale. These switches are selected in response to the signals AD11, AD12 and switch data produced thereby is superposed on the data bus. The CPU 1 reads out the switch data from the data bus and conducts a switching process, if necessary.
The tempo generator 8 comprises a variable oscillator whose frequency of oscillation is easily varied by means of a variable resistor, a tempo generator circuit for generating a tempo signal, a tempo pronunciating circuit synchronised with the tempo signal, a tempo display circuit for visually confirming the tempo, and a voice synchronisation tempo control circuit constructed so that the tempo signal may be synchronised with the voice input and has its signal TEMPO connected with the terminal INT of the CPU 1.
Next, the operations of the CPU 1 will be explained. The CPU 1 is interrupted in response to the signal TEMP to read in the data of the voice pitch extractor 3 a plurality of times at a timing of about one half of the period of the signal TEMP. When the voice input is applied in accordance with the signal TEMP generated by the tempo generator, specifically, the CPU 1 reads in the pitch data of the voice signal at a relatively stable interval. The CPU 1 promptly reads in the relatively stable pitch data a plurality of times and transduces it into a plurality of scale data. A majority logic is taken from the plurality of scale data and the most frequent scale data is stored in the RAM 4. Thus, a system having a relatively high detecting efficiency can be realised even if the interval is pronounced more or less unstably. At this time the voice pitch extractor 3 outputs new pitch data at each pitch of the voice signal inputted. In other words, the voice pitch extractor 3 extracts the voice pitch data in real time.
The CPU 1 causes the scale data detected in the RAM 4 consecutively in response to the signal TEMP. The foregoing operations are those in the song making mode or in the recording mode. Simultaneously with this storing operation in the RAM 4, moreover, the CPU 1 transfers the scale data to the note indicator 5 so that the note can be displayed in real time.
In the correcting mode, the scale data stored in the RAM 4 is read out and corrected. In this case, the scale data of eight tones is displayed in the note indicator 5 and is corrected while being confirmed. In this correcting mode, the correcting operations can be better facilitated if the scale data is transferred to the musical sound generator also to effect two expression systems of the musical sounds and the displays simultaneously as the musical scales are displayed by the musical sound generator 6.
In the reproducing mode, the scale data stored in the RAM 4 is reproduced simultaneously in the note indicator 5 and the musical sound generator 6 in synchronism with the signal TEMP coming from the tempo generator 8. As a result, the musical scales of a song, which were slowly inputted in the song making mode, can be speeded up when they are reproduced. This is because the CPU 1 operates in synchronism with the variable signal TEMP.
The description thus far is directed to the construction of the interval scoring system of the present invention. Next, a pore detailed description will be made with reference to the other Figures. In order to make an orderly explanation, the description will be first directed to the voice pitch extractor 3 details of which are shown in Figure 3.
The voice pitch extractor 3 has an amplifier 30, a voltage follower 31, an inverting amplifier 32 having an amplification factor of 1, peak hold circuits 33,34, a set/reset flip-flop (S_RF/_F) 35, a differentiator 36, a delay circuit 37, an oscillator 38 for generating a clock signal of 1 MHz, a counter 39, a latch circuit 40, an electronic switch 41 which is turned on and off in response to a signal at an S input terminal, an AND circuit 42, and a microphone 43.
The microphone 43 is connected with the input terminal of the amplifier 30, the output of which is connected with the input terminal of the voltage follower 31, the output of which is connected with both an input terminal of the peak hold circuit 33 and an input terminal of the inverting amplifier 32. The output of the inverting amplifier 32 is connected with an input terminal of the peak hold circuit 34, and the output of the peak hold circuit 33 is connected with an input terminal of a set input terminal S of the SRF/F 35. Moreover, the output of the peak hold circuit 34 is connected with a reset input terminal R of the SRF/F 35, an output terminal Q of which is connected with an input terminal of the differentiator 36. An output terminal φI. of the differentiator 36 is connected with an input terminal of the delay circuit 37 and an input terminal Q of the latch circuit 40. An output terminal φR of the delay circuit 37 is connected with a reset input terminal of the counter 39, and the output terminal (indicated by letters 1 MHz) of the oscillator 38 is connected with a clock input terminal of the counter 39, the counted output of which is connected with an input terminal of the latch circuit 40, the output of which is connected with the electronic switch 41, the output of which is connected with the data bus DATA BUS. The signal ADO and the signal RD are inputted to the AND circuit 42, the output of which is connected with the input terminal S of the electronic switch 41. Here, this electronic switch 41 is generally constructed as a tri-state buffer so that it is turned on for an input at the input terminal S of level 1 and so that its output takes a high impedance when the input at the input terminal S is at level 0.
Next, the operations of the voice pitch extractor will be described with reference to Figures 3 and 4, Figure 4 being a timing chart illustrating the timings of the voice pitch extractor of Figure 3.
First of all, the voice signal inputted from the microphone 43 is caused by the amplifier 30 and the voltage follower 31 to have such a waveform as indicated at A in Figure 4. On the other hand, the output of the inverting amplifier 32, having an amplification factor of 1, becomes such an inversion from the waveform A as is indicated at B in Figure 4. The waveforms A and B are prepared by amplifying the voice waveform and are inverted to become symmetric to each other. The waveform A is connected with the input terminal of the peak hold circuit 33 whereas the waveform B is connected with the input terminal of the peak hold circuit 34 so that the two peak hold circuits 33, 34 detect the peak values of the respective waveforms and hold them. Here, these peak hold circuits 33, 34 analogously hold the peak values in a capacitor C but discharge, although slightly, through a resistor R. After detection of the peaks of the input waveforms, more specifically, the potential at a point P is caused to follow broken curves, which are located above the waveforms A and B of Figure 4, in accordance with the time constant determined by the values of the capacitor C and the resistor R. Moreover, the respective outputs (as indicated at C and D in Figure 4) of the peak hold circuit 33, 34 take level 1 when the peak of the waveform A or B is detected. More specifically, the peak hold circuit 33 detects the positive peak of the voice waveform whereas the peak hold circuit 34 detects the negative peak of the voice waveform. Generally speaking, the voice waveforms are complicated as are indicated at A and B in Figure 4, but the voice pitch can be efficiently detected if the peak hold circuit is as shown in Figure 3. Moreover, since the voice frequency is usually 70 Hz to 900 Ez, the time constant of the circuit comprising the capacitor C and the resistor R is preferred to be about 10 ms or longer.
Next, the output (as indicated at C) of the peak hold circuit 33 operates to set the SRF/F 35 whereas the output (as indicated at _D) of the peak hold circuit 34 operates to reset the SRF/F 35. The operating timings are indicated at C, D, and E in Figure 4. The waveform E is the output at the Q terminal of the S_RF/_F 35. In other words, the SRF/F 35 is set by the positive peak of the voice waveform and is reset by the negative peak. Moreover, the output at the Q terminal of the SRF/F 35 is synchronised with the voice pitch, as indicated at E in Figure 4.
In Figure 4, the output signals of the differentiator 36 and the delay circuit are denoted at φL and φR respectively. In short, the signal φL or the signal ÒR is generated only at the positive peak of the voice waveform, and its generating period is substantially equal to the voice pitch.
Here, the signal φL operates as the clock input of the latch circuit 40 whereas the signal φR operates as the reset input of the counter 39. This counter 39 may preferably be of a binary- up type of 15 to 16 bits. Moreover, the counter 39 is reset by the signal φR which is generated at each voice pitch, and counts the clock signal of 1 MHz in other time periods. In response to the signal φL on the other hand, the latch circuit 40 latches the counted value of the counter 39. Since the signal φL is generated slightly before the signal φR, the latch circuit 40 latches the value immediately before the counter 39 is reset.
More specifically, the value counted at a timing T1 (as shown) of Figure 4 is latched and held in the region of a timing _T2 (as shown). Thus, the held content of the latch circuit 40 detects new data in real time in accordance with the voice pitch. Since the clock of the counter 39 is 1 MHz, moreover, the period of the voice pitch becomes 2 ms, and the fundamental frequency of the voice becomes 500 Hz, if the counted value of the counter 39 is "2000".
Next, the held data of the latch circuit 40 is fed to the -data bus DATA BUS on instruction from the CPU 1 when the signal _ADO and the signal RD become effective. In other words, the voice pitch data is fed to the data bus in real time when they are required by the CPU.
A list of the counted values and the tone names, concerning what interval of the voice input for what counted value of the counter 39 corresponds to what tone name, are tabulated in the following Table:
In this Table, the item "voice pitch allowable period" means the voice input pitch period, which is to be allowed in comparison with the musical absolute interval, so that the interval generated by a person is recognised as is replaced by a tone name in the vicinity of the corresponding interval even if it is slightly shifted. On the other hand, the allowable counted value expresses the counted value of the counter 39.
As has been described hereinbefore, the voice pitch extractor has a highly accurate and simple circuit construction so that it can efficiently extract the voice pitch data.
Next, the note indicator 5 will be described in detail with reference to Figures 2, 5, 6, and 7 where Figure 5 is a diagram showing details of the note indicator, Figure 2 is an external view of the note indicator, Figure 6 is a detailed diagram corresponding to Figure 5 and Figure 7 is a timing chart illustrating the operation of the note indicator.
As shown in Figure 5 the note indicator includes AND circuits 50, tri-state latch circuits 51a to 51h which are composed of latch circuits and tri-statebuffers, a decoder 52, an X-driver 53, a Y-driver 54, a timing generator 55 and an LED display 56.
As the display element, LED or liquid crystal elements can be used, the former being exemplified in the present embodiment.
The AND circuits 50 are gate elements for turning on and off the signals AD2 to AD9 in response to the signal WR. Signals φ2 to φ9 from the outputs of the AND circuits 50 are connected with input terminals φ of the tri-state latch circuits 51a to 51h, respectively. On the other hand, these tri-state latch circuits 51a to 51h have their input terminals IN connected with the data bus DATA BUS and their terminals OUT connected commonly with the input terminal of the decoder 52. Since the data bus has eight bits, the input terminal of the decoder 52 also has eight bits.
Signals φA to φH at the outputs of the timing generator 55 are connected with an input terminal of the Y-driver 54 and with input terminals S of the tri-state latch circuits 51a to 51h, respectively.
The output of the decoder 52 is connected with an input terminal of the X-driver 53, the output of which is connected with an output terminal of the Y-driver 54 and the LED display 56. The LED display 56 is as shown in Figure 2, with an LED group mounted on each staff notation. Moreover, the LED display is composed of eight blocks, each of which is so connected that it is controlled by the output of the Y-driver 54. In other words, the LED display shown in Figure 2 is so arranged that it is driven by the X-driver 53 and the Y-driver 54. Output timings φA to ¢H of the timing generator 55 are such shift pulses as are shown in the timing chart of Figure 7. In other words, the Y-driver 54 sequentially drives the eight blocks of the LED display in response to the pulses shown in Figure 7.
Next, how data is to be transferred from the CPU to the note indicator will be explained. In order to instruct what note is displayed in which of the eight blocks of the note indicator, first of all, the CPU selects one of the signals AD2 to AD9 and generates the signal WR at the same time. For example, in the case where a predetermined note is to be displayed in the most left-hand note block, the CPU selects a signal AD2 and feeds predetermined scale data to the data bus. Of the outputs of the AND circuits 50, the signal φ2 becomes active so that the tri-state latch circuit 51a takes in the scale data on the data bus. Here, the tri-state latch circuit 51a has the construction shown in Figure 6, and takes in the data from a terminal φ to output it from a terminal S. As a result the tri-state latched circuit 51a transfers the scale data to the decoder 52 in response to the signal ϕA shown in Figure
7. The decoder 52 transduces the scale data into a predetermined LED lighting signal to drive the X-driver 53. In this case, the LED display of one block has sixteen components and the decoder 52 has sixteen outputs.
In other words, the LED display 56 is driven only by the output timing of the timing generator 55 and is not synchronised with the data transfer from the CPU.
In the construction so far described, the CPU is enabled to transfer arbitrary scale data to an arbitrary display at an arbitrary time. As a result, the load upon the processing of the C_PU is reduced, and the construction of the program can be facilitated.
Next, the musical sound generator 6 will be described in detail with reference to Figure 8. Figure 8 shows a musical sound generator 80, effect switches 81 for vibrating and sustaining to control the musical sound waveforms, an AND circuit 82, a musical sound generator 83, a filter 84, an amplifier 85 and a speaker 86.
The data bus is connected with an input terminal DIN of the musical sound generator 80, and the AND circuit 82 is fed with the signal AD10 and the signal WR and has its output connected with the input terminal WR of the musical sound generator 83.
The musical sound generator 80 and the effect switch 81 are connected with the musical sound generator 83. An output OUT is connected with the input terminal of the filter 84, the output of which is connected with the input terminal of the amplifier 85, the output of which is connected with the speaker 86.
In the case where a musical sound is to be generated, the CPU selects the signal AD10 to feed predetermined scale data to the data bus and to generate the signal WR at the same time. The musical sound generator 83 reads in the scale data which is applied to the DIN terminal, in response to the signal WR to recognise the scale data and compose the musical sound. Here, the musical sound generator is sufficiently constructed of a musical sound generating ISI available in the market, and its peripheral circuit is known as the electronic circuit for an electronic instrument. In the present embodiment, the musical sound generating LSI is a custom built ISI. The present embodiment must naturally have the CPU data receiving function.
As has been described hereinbefore, the CPU can reproduce beautiful musical sounds with ease by transferring the predetermined scale codes to the addresses of the signal AD10.
The switch unit 7 will now be explained in detail with reference to Figure 9. The switch unit 7 has tri-state buffers 90a to 90c which are to be controlled through an input terminal S as shown in Figure 10, a mode switch 91 for setting the song making, correcting and reproducing modes, a start switch 92, an end switch 93, cursor shifting switches 94, 97 for the correcting mode, a rotary digital switch 98 for octave shift in the correcting or reproducing mode, a rotary digital switch 99 for tune correction in the correcting or reproducing mode, and AND circuits 100, 101.
The mode switch 91, the start switch 92 and the end switch 93 are connected with input terminals of the tri-state buffer 90a and the cursor shifting switches 94 to 97 are connected with input terminals of the tri-state buffer 90b. Moreover, the respective outputs of the rotary digital switches 98, 99 are connected with the input terminals of the tri-state buffer 90c. The respective outputs of the tri-state buffers 90a, 90b, 90c, are connected commonly with the data bus. The signal RD is connected with one input terminal of each of the AND circuits 100, 101, and the signal AD11 is connected with the other input terminal of the AND circuit 100 whereas the signal AD12 is connected with the other input terminal of the AND circuit 101. The output of the AND circuit 100 is connected with the respective input terminals S of the tri-state buffers 90a, 90b, whereas the output of the AND circuit 101 is connected with the input terminal S of the tri-state buffer 90c.
The operation of the switch unit 7 will now be described. When the CPU wants to know the states of the switches, first of all the states of the respective switches from the mode switch 91 to the cursor shifting switch 97 are outputted to the data bus by activating the signal AD11 and the signal RD. The CPU reads and stores the data. By activating the signal AD and the signal RD, moreover, the states of the rotary digital switches 98, 99 can be known.
Next, the operations of the respective switches will be explained in the following in accordance with the operating procedures. First of all, the mode switch 91 is set in the song making mode, and the start switch 92 is turned on. In this state, the CPU detects the voice input in accordance with the signal TEMP. Specifically, the CPU takes in the pitch data of the voice pitch extractor 3 and transduces it into the scale data which is stored consecutively in the _RA M 4. Next, at the instant when the voice input is ended, the end switch 93 is turned on to end the song making mode.
Next, the mode switch 91 is set in the correcting state, and the start switch 92 is turned on. The CPU detects this state and reproduces the scale data, which is stored in the top to eighth one of the RAM 4, in the note indicator 5 in the musical sound generator 6. In this case, the CPU refers the switch data of both the octave shifing rotary digital switch 98 and the transposing rotary digital switch 99. For example, if both the rotary digital switches 98, 99 are in the shift zero positions, the scale data of the RAM 4 is reproduced as it is. If the octave shifting rotary digital switch 98 is in a "one octave up" position, the scale data in the RAM 4 is reproduced after it is shifted up by one octave. At this time, the scale data to be transferred to the note indicator 5 and the musical sound generator 6 is processed with the scale data in the RAM 4 being left as it is.
On the other hand, the transposing rotary digital switch 99 has a function to effect reproduction by transferring a C major into an F minor, for example. In the case where a melody of C₅, A₅, B and
is to be reproduced by raising the musical scale by one, more specifically, the reproduction results in
, A5, C₅and ^E ₄.
In the correcting mode, the notes in arbitrary positions can be arbitrarily corrected by the actions of the cursor shifting switches 94 to 97. In the corrections by the cursor shifts in this case, the scale data in the RAM 4 is corrected.
When the start switch 92 is turned on in the correcting mode, moreover, the following eight scales are reproduced, namely, the operations of reproducing and correcting the eight scales. If the corrections of the eight tones are ended, therefore, the start switch 92 can be turned on to enter the corrections of the eight tones.
Next, the reproducing mode will be explained. In the reproduction, the mode resembles the operation which has been explained in the correcting mode. First of all, the mode switch 91 is set in the reproducing mode, and the start switch 92 is turned on. The CP_U sequentially reproduces the scale data of the RAM 4 in the note indicator 5 and the musical sound generator 6 in synchronism with the signal TEMP. At this time, it goes without saying that the reproduction is made in accordance with the switch states of the octave shifting rotary digital switch 98 and the transposing rotary digital switch 99.
With the switch unit thus far described the CPU can easily read the switch data at its arbitrary timing. Incidentally, since the switches may be promptly operated, consideration has to be taken to take into the switches every 100 ms.
As a result of the many correcting functions and the various reproducing functions, moreover, the scale data once stored can be corrected repeatedly many times and can be reproduced at an arbitrary octave and in an arbitrary transposition.
The tempo generator 8 will be explained in detail with reference to Figure 11. The tempo generator has a variable oscillator 110 whose frequency of oscillation can be varied by a resistor _Rx, a counter 111, differentiators 112, 113, a set/reset flip-flop (S_RF/_F) 114, AND circuits 115, 117, 118, an OR circuit 116, a delay circuit 119, a visual display 120, an audio display 121, and a speaker ON switch 122.
The output of the variable oscillator 110 is connected with a clock input terminal of the counter 111, the output of which is connected with an input terminal of the differentiator 112, an output terminal TX of which is connected with one input terminal of the OR circuit 116.
The song making signal and the start signal are fed from the switch unit 7 to the input terminals of the AND circuit 115, respectively. The output of the AND circuit 115 is connected with a reset input terminal R of the SRF/F 114, whereas the signal φL is connected with a set input terminal S of the SRF/F 114. Here, the signal QL is level 1 which is fed from the voice pitch extractor 3, and is generated only when the voice input is applied, in synchronism with the pitch of the voice. As a result, the signal φL is not generated in the case of no voice.
An input terminal Q of the SRF/F 114 is connected with the input terminal of the differentiator 113 and one terminal of the AND circuit 117 and an output terminal BGN of the differentiator 113 is connected with the other input terminal of the OR circuit 116 and a reset terminal of the differentiator 112. The output of the OR circuit 116 is connected with the other input terminal of the AND circuit 117, one input terminal of the AND circuit 118 and an input terminal of the visual display 120. Moreover, a signal of 1 KHz is connected with the other input terminal of the AND circuit 118. An output terminal TY of the AND circuit 117 is connected with an input terminal of the delay circuit 119, the output of which is connected as the signal TEMP with the input terminal INT of the CPU 1 of Figure 1.
The output of the AND circuit 118 is connected through the speaker ON switch 122 with an input terminal of the audio display 121.
Here, the visual display 120 is composed of an LED and a circuit for driving the LED and operates to effect tempo display. On the other hand, the audio display 121 is composed of a speaker and a circuit for driving the speaker and generates a tempo sound in response to the 1 KHz signal.
Next, the operations of the tempo generator 8 will be explained with reference to the timing chart of Figure 12. Figure 12 is a timing chart showing the timings of the respective portions of Figure 11. The tempo generator of the present embodiment contemplates to practice a tempo synchronising system by which the tempo is synchronised with the voice input at the start of a song.
First of all, in the song making mode, the song singing is not started before the start switch is turned on. When the start switch is turned on in the song making mode, a signal Q takes the level 0 at a timing tab of Figure, 12. In the timing region ta of Figure 12, the signal Q is at level 1 and the signal T_X becomes a signal TY as it is, so that the signal TEMP is generated. However, the CPU does not score in accordance with the signal TEMP so long as the start switch receives no input even in the song making mode. In other words, the CPU does not score in the timing region ta. Since the signal Q is caused to take the level 0 as a result that the start switch is turned on, the signal TEMP is not generated in a timing region tb so that the CPU does not score. Even if the start is made in the song making mode, more specifically, the _CPU does not score to spare the memory region of the RAM 4.
Next, if the song singing is started at a timing tbc, the signal ¢_L begins to be inputted to set the SRF/F 114. Simultaneously with this, the differentiator 113 operates to generate the signal BGN at the rise of the output Q. The signal BGN resets the counter 111 and the differentiator 112 so that the signal TX is generated for a predetermined period after the signal BGN has been generated. In the region tc, moreover, the signal TEMP is generated in response to the signal BGN and the signal TX.
On the other hand, a signal TZ is generated at such a timing as is shown in Figure 12 only when the speaker on switch 122 is turned on. In other words, since those tempo confirming means are provided even in any state, the tempo of the song can be easily taken.
The counter 111 receives and divides the clock from the variable oscillator 110 to generate the tempo period which is determined by the resistor Rx. As a result, the signal TX is a tempo pulse in a normal state.
On the other hand, the signal TZ is delayed to produce the signal TEMP. This is because the start of a voice has a relatively unstable waveform so that the pitch extracting efficiency drops as the voice pitch is extracted at the first timing. In other words the interruption of the CPU, (i.e. the signal INT or the signal TEMP) is more or less delayed so as to extract the pitch in the vicinity of the centre of a timing 1β of Figure 12.
With the tempo generator thus far described, no consideration need be taken into the start of the song, and the storing efficiency of the RAM can be improved. At the start in the reproducing mode, moreover, the soundless section can be cut to reproduce the song in high fidelity from the start.
The interval scoring system according to the present invention and described above has the following advantages:

(1) A relatively stable interval of a voice can be extracted;
(2) Since the recorded song can be reproduced with the octave shifted and transposed, a wide melody range can be reproduced;
(3) The recorded melody (i.e. the scale data) can be corrected by simple switching operations;
(4) Since the positive and negative peaks of the voice waveform are detected simultaneously at the voice pitch extractor, the interval detecting efficiency is excellent, and a remarkably simple circuit construction is sufficient.
(5) Since the start of the song need not be synchronised with the tempo, the song can be easily sung, and the RAM is used efficiently;
(6) For the user, the absolute interval can be easily studied;
(7) Since the melody made by the user can be reproduced in a plurality of tones, it is possible to provide a product which has a high commercial value;
(8) Since the voice pitch extractor has a relatively wide use, scoring can be made of not only a song that is sung but also music resulting from the playing of instruments; and
(9) Since the data transfer is conducted through the data bus of the CPU, I/O devices such as printers and CRTs can be easily added by making use of that data bus.

Claims

1. A voice recognition interval scoring system characterised by comprising: pitch extracting means (3) for extracting at least the fundamental pitch of the wave of a voice or a musical sound; transducing means (CPU) for transducing pitch data generated by said pitch extracting means into a musical interval; memory means (4) for storing the result of said transducing means; and interval reproducing means (5,6) for visually or audibly expressing the content of said memory means.

2. A voice recognition interval scoring system as claimed in claim 1 characterised in that said interval reproducing means includes a musical sound generator (6) for producing a plurality of musical sound waves.

3. A voice recognition interval scoring system as claimed in claim 1 or 2 characterised by further comprising correcting means (7) for correcting interval data stored in said memory means.

4. A voice recognition interval scoring system as claimed in claim 3 characterised in that said correcting means includes a switch (94,95,96,97) for selecting an address of said memory means and a switch for changing the interval of the address selected.

5. A voice recognition interval scoring system as claimed in any preceding claim characterised by comprising an external switch for setting reproduction at an octave-shift action when the content of said memory means is produced by said interval reproducing means.

6. A voice recognition interval scoring system as claimed in any preceding claim characterised by including a tempo generator (8), said pitch extracting means operating in response to a tempo signal from said tempo generator and being inhibited until said voice or musical sound is applied.

7. A voice recognition interval scoring system as claimed in any preceding claim characterised in that said pitch extracting means comprises an inverting circuit (32) for inverting the wave of said voice or said musical sound, a first peak hold circuit (33), a second peak hold circuit (34) and a flip-flop (35) controlled by said first peak hold circuit and said second peak hold circuit, said first peak hold circuit in operation detecting a positive peak of said wave of said voice or said musical sound, said second peak hold circuit in operation detecting a positive peak of the output of said inverting circuit so that a period of said voice or said musical sound is detected by measuring the period of the output of said flip-flop.