JPS6090376A - Voice recognition type musical scale learning apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] The present invention involves singing the entire song in voice, extracting the basic pitch of the voice, converting it to a musical sound +
The present invention relates to a voice recognition type pitch learning device that is useful for learning how to accurately generate pitches by reproducing musical scales or melodies.

Traditionally, you sing a song and let it go! As an electronic device for sampling the pitch of 1, there was a cod collecting device that applied a large or small computer at the ω1 laboratory level. , and there was no mackerel that could be caught easily.

In order to solve the disadvantages of the present invention, the present invention is constructed using an ultra-small microprocessor and some hardware,
The purpose is to easily, efficiently, and accurately transcribe songs. Furthermore, it is equipped with a correction function so that the transcribed melody can be stopped, and when it is played back, it is intended to be played back in a musical score waveform with a beautiful tone. Hereinafter, the present invention will be explained in detail according to the drawings.

FIG. 1 is a block diagram of the present invention.

1; jOPUs 2 is an address decoder, 3 is an audio pitch extraction section, 4 is a RAM, 5 is a note display section, 6 is a musical tone generation section, 7 is a switch section, and 8 is a tempo generation section. From the CPU 1, an address decoder 2 head address signal AD is connected, and a data bus (indicated by DATA BUS) is connected after iA with the data terminals from the audio pitch extraction section 3 to the switch section 7. Also,.

RD multiplied signal from CPU 1, audio pitch extraction unit 3 and RA
Connected to M4 and each RD terminal of the switch section 7,
The WR double signal, R.AMII, is connected to each WR terminal of the note display section 5 and musical tone generation section 6.

The iJ and AD\ signals from the address decoder 2 go to the audio pitch extractor 3, the AD1 signal goes to the RAM 4, A D 2. ~
The 9 signal goes to the note display section 5, and the AD10 signal goes to the musical tone generation section 6.
and AD11 to AD12 signals are respectively connected to the switch section 7. In addition, the microphone for voice input (indicated by M C) is connected to the 1N terminal of the voice pitch extraction section 3.
Tl!, which is the output of the tempo generator 8, is sent to the φL times signal tempo generator 8, which is the output of the tempo generator 8. iMP signal is CPU 1
Each is connected to the T (interrupt) input terminal.

Next, the operation of each block will be briefly explained.

The address decoder 2 determines which block the PU 1 is currently working on and selects one of the blocks.
.

The audio pitch extractor 3 amplifies the audio signal selected by the ADIIk signal output from the address decoder 2 and input from the microphone, detects the peak of the fundamental wave of this audio waveform, and calculates the time between the peaks. This block measures and stores the measured values. and,
If necessary (in this case, when the CPU 1 selects AD\), data is loaded onto the data bus (indicated by DATA BUS). Further, the illustrated φL multiplied signal occurs only when there is audio input, and its period is approximately equal to the pitch period of the audio input waveform.

RAM 4 U, A which is the output of address decoder 2
Selected by D1 signal. In the case of a RAM, there are generally a plurality of address input terminals, but in FIG. 1, it is shown that it is accessed only by the AD1 signal.

Naturally, a plurality of address signals are connected to the RAM 4 from 0PU1, but these are omitted in Figure 1. Therefore, the AD1 signal is shown as a chip select signal for RAM4. Further, since the connection between the CPU 1 and the RAM 4 is already known, detailed connection relationships will not be described.

The RAM 4 is a block that stores scale data obtained by determining and converting the pitch information obtained from the audio pitch extraction unit 3 using 0PU1. In other words, 0PU1 sequentially stores the scale data obtained from the audio pitch extraction unit 3 in RAM.
4, and also modify the memorized scale data,
Alternatively, during playback, the data stored in the RAM 4 is sequentially read out and processed.

The musical note display section 5 is a block that sequentially displays a part of the data stored in the RAM 4 mentioned above, and is a liquid crystal or LF! D
It consists of a display body and a drive circuit.

Figure 2 is an external view of the display when configured with LEDs.
LEDs corresponding to each scale are mounted on the 5-line staff, and are arranged so that up to 8 scales can be displayed simultaneously. Also,
A sharp LED (indicated by ≠) is also implemented to display semitones.

The musical tone generator 6 is a block that recognizes scale data stored in the RAM 4 and converts the scale data into musical tones, and also has a function of arbitrarily selecting a plurality of types of musical tones. The musical tone generator 6 generates the scale data (indicated by the jPU1).
The data stored in RAM 4) is converted into a musical tone signal, which is amplified by a filter section and an amplification section to drive a speaker.

The switch section 7 includes a mode switch section for setting each mode of recording, correction, and playback, and a mode switch section for setting each mode of recording, modification, and playback, and a mode switch section for setting each mode of recording, correction, and playback, and a start and control section for each mode.
It consists of end switches, a cursor movement switch in correction mode, an octave shift switch during correction or playback, and a key correction switch for correcting the key of the scale. These switch groups also have ADl 1 to 1
2 signal and is placed on the data bus. 0PU1
ij, read this switch data from the data bus,
The tempo generation section 8, which performs switch processing as necessary, includes a variable oscillation circuit whose oscillation frequency can be easily varied using a variable resistor, a tempo generation section, and a tempo generation circuit synchronized with the tempo signal. It consists of a tempo display circuit that can check the tempo and an audio synchronized tempo control section configured so that the tempo signal is synchronized with audio input, and is connected to the IN input (interrupt input) of the TKMP signal (shown) icpσ1.

Next, the operation of the CPU 1 will be explained according to the operating procedure.

0PU1 reads the data of the audio pitch extractor 5 multiple times at a timing of about half the cycle of the TInMP signal r (signal side interference occurs, this T]IcMP signal. In other words, the TFiMP signal generated from the tempo generator 8 When the audio input is applied according to the pitch, the pitch data of the audio signal with a relatively stable pitch is read.The 0PU1 quickly reads this relatively stable pitch data multiple times, and then reads the pitch data of the multiple times. Convert to multiple scale data.Then, the majority logic of these multiple data is
, the most accurate scale data is stored in the RAM 4 as a single scale data. By using C, it is possible to achieve relatively high detection efficiency even if the pitch of the utterance is slightly unstable. At this time, the audio pitch extraction section 3 outputs new pitch data for each pitch of the input audio signal, that is, the audio pitch extraction section 5 extracts audio pitch data in real time.

apr, tl are Tl1l;MP times the signal.Accordingly, the detected scale data is sequentially stored in the RAM4. The above is the operation in composition mode or recording mode.

Furthermore, at the same time as storing it in the RAM 4, the note display section 5
It is also possible to transfer scale data to display notes in real time.

In the modification mode, the scale data stored in the RAM 4 is read out and modified. In this case, display the scale data for 8 notes on the note display section 5, and correct it while checking it7.
In this correction mode, when the scale is displayed on the note display section 5, the scale data is also transferred to the musical tone generating section 6 at the same time, and the correction can be made even easier by expressing the musical tone and the display in two systems. Probably.

In playback mode, the scale data stored in RAM4 is
Tempo generation part 8-gara T F! In synchronization with the MP signal, it is simultaneously reproduced to the note display section 5 and the musical tone generation section 6. Therefore, in composition mode, the scale of a song input slowly is
It is also possible to speed up when playing,
That is, the CPU 1 operates in synchronization with the variable TIMP signal.

The above is the explanation of the system configuration of the present invention.

Next, a more detailed explanation will be given with reference to FIG. 2 and subsequent figures.

First, in order to explain in order, a detailed explanation of the voice pitch extracting section 3 will be given.

FIG. 3 is a detailed diagram of the audio pitch extraction section B.

50 is an amplifier circuit, 31 is a voltage follower, 3
2 is an inverting amplifier circuit (amplification $=1 times), 33 and 34 are peak hold circuits 11t3, 351d set reset flip-frog (hereinafter abbreviated as SRF/F), 56 is a differentiation circuit, 37 is a delay circuit, 381 39 is a counter, 40 is a latch circuit, 41 is an electronic switch that is opened and closed by the date input (shown in the figure), 42 is an AND circuit, and 43 is a microphone (hereinafter referred to as "M"). (abbreviated as C).

The M-engine 043 goes to the input end of the amplifier circuit 3o, the output of the amplifier circuit 30 goes to the input end of the voltage follower 31, the output cover of the voltage follower 31, the input end of the peak hold circuit 33, and the input end of the inverting amplifier circuit 52. are connected to each
The output of the inverting amplifier circuit 32 goes to the input terminal of the peak hold circuit 64, and the output of the peak hold circuit 33 goes to the SRF/F3.
5 set (indicated by S), the output of the peak hold circuit 34 is RRF/F! +5 reset (denoted by R)
To the input terminal, the Q output of the 8 RF/F 35 is connected to the input terminal of the differentiating circuit 36, and the output of the differentiating circuit 36 (indicated by φL) is connected to the input terminal of the delay circuit 37 and the φ input terminal of the latch circuit 40, respectively. . The output of the delay circuit 57 (indicated by φR) is input to the reset input terminal of the counter 39, and the output 1 of the oscillation port r638 is input to the reset input terminal of the counter 39.
: IMH2) is sent to the clock input terminal of the counter 39, the counting output of the counter 39 is sent to the input terminal of the latch circuit 40, the output of the latch circuit 40 is sent to the electronic switch 41, and the output of the electronic switch 41 is sent to the data bus ( DATABUS)
connected to each. The AD\ signal and the RD multiplied signal are input to the AND circuit 42, and its output is the electronic switch 4.
108 input end.

Here, the electronic switch 41 is generally composed of a 3-state buffer, and is turned on when the 8 inputs are at level 1, and when the level is \, the output becomes high impedance.

Next, the operation of the voice pitch extraction section will be explained with reference to FIGS. 3 and 4. FIG. 4 is a timing diagram of each part in FIG. 5.

First, the audio signal input from M1013 is sent to the amplifier circuit s.
o and the voltage follower 31, the waveform shown by A in FIG. 4 is obtained. Furthermore, the output of the inverting amplifier circuit 32 with an amplification factor of 1 is an inverted version of waveform A as shown by B in FIG. 4. Waveforms A and B are amplified audio waveforms and are inverted symmetrical waves. be. This waveform A is connected to the input end of the peak hold circuit 35, and the waveform B is connected to the input end of the peak hold circuit 54, respectively, and the peak hold circuits 33 and 34 detect and hold the peak value of each waveform. However, although the peak hold circuits 35 and 34 hold the capacitor OVc peak value shown in the figure in an analog manner, it is slightly released by the resistor RVc.

That is, after the peak of the input waveform is detected, the potential at point P (shown) becomes a broken line curve shown on the human waveform and the B waveform in FIG. 4 according to the time constants of C and R. Then, the respective outputs of the peak hold circuits 33 and 34 (C and D in FIG.
) becomes level 1 when the peak of waveform A or the peak of waveform B is detected. That is, the peak hold circuit 33 detects the positive peak of the voice waveform, and the peak hold circuit 34 detects the negative peak of the voice waveform. Although the waveform is complex, a peak bold circuit like the one shown in Figure 3 can efficiently detect all pitches of the voice.Furthermore, the frequency of the voice generally ranges from 70H2 to 900H28.
Therefore, the time constants of C and R are preferably about 10 m8 or more.

Next, the output of the peak hold circuit 33 (indicated by C) l-
1: Operates to set the SRF/F35, and the output of the peak hold circuit 34 (indicated by D) is set to the RF/F35.
works to reset.

The timing is shown by C, D, and E in FIG.

The E waveform is the q output of the SRF/F 35. That is, the SRF/F 35 is set at a positive peak of the audio waveform and reset at a negative peak. and SRF/F35
The Q output of is equal to the period of the voice pitch, as shown by E in FIG.

Next, the output of the differentiating circuit 36 and the output of the delay circuit are denoted by φL and φR, respectively, and the timing is φL in FIG.
and ψR. That is, φL1 or φR occurs only at the positive peak of the audio waveform, and its generation period is approximately equal to the audio pitch.

Here, it operates as a clock input for the φL times signal latch circuit 4o, and as a reset input for the φR times signal counter 39. This counter 39 is preferably in a 15-16 bit binary up format. The counter 39 is reset by the φR multiplied signal generated for each voice pitch, and otherwise counts the clock of IMH2. The switched latch circuit 40 is a signal counter 4o multiplied by φL.
Latch the count value. Since the φL multiplied signal and ψR multiplied signal are generated slightly before, the latch circuit 40 holds the value immediately before the counter 40 is reset.

That is, the value counted at timing T1 (illustrated) in FIG. 4 is latched in the region of timing T2 (illustrated at 6). In this way, new data is detected in real time according to the audio pitch held by the latch circuit 40, and the clock of the counter 39 is set to IMHz.
Therefore, for example, the count value of the counter 59 is [oo
If oJ, the period of the voice pitch is 2 mS, and the fundamental frequency of the voice is 500H2.

Next, according to the instruction from the content H1aptr held in the latch circuit 40, when the ADR signal and the RD double signal become valid, the audio pitch data is transferred to the data bus in real time when the CPU needs it. Supplied onto the data bus.

The table below shows a list of counted values and pitch names, which indicates which pitch name the pitch of the voice input corresponds to, depending on the counted value of the counter 39.

In this table, the item "acceptable voice pitch period" means the voice input pitch period that should be allowed compared to the musical absolute pitch, and even if the pitch produced by a person is slightly off, the corresponding pitch The permissible count value represents the entire measured value of the counter 39.

As described above, the voice pitch extraction section can efficiently extract voice pitch data with high accuracy and a simple circuit configuration.

Next, the RAM 4 will be described. The element called RAM is already well known, and the connection relationship with the j7X CPU is also widely known. Therefore, detailed explanation will be omitted here.

Next, the note display section 5 will be explained in detail.

The explanation will be made according to FIGS. 5, 2, 6, and 7. FIG. 5 is a detailed view of the note display section, FIG. 2 is an external view of the note display section, and FIG. 6 is a detailed view of the note display section. 5 is a detailed view of the block in FIG. 5, and FIG. 7 is a part of the evening and f-ming in FIG. 5.

First, to explain from Fig. 5, the 5ojq AND circuit group,
51a to 51b are three-step latch circuits consisting of a latch circuit and a three-state buffer, 52 is a decoder, 53 is an X driver, 54t'JY driver, 55I
a, a timing generator; 56, an L1nD display body;

Generally, an LID or a liquid crystal can be considered as a display element, but in this embodiment, an LFtD display is shown as an example.

A detailed explanation of the case of LPAD display will be given below.

The AND circuit group 50 receives AD2 to AD9 signals (illustrated) IW
This is a gate element that opens and closes with the R signal (shown). The outputs ψ2 to φ9 (shown) of the AND circuit group 50 are connected to the φ inputs of three-step latch circuits 51a to 51h, respectively. In addition, the three-step latch circuits 51a to 5
Data bus (DATA Bus) is connected to the 1h N input terminal.
are connected to each other, and their OUT terminals are commonly connected and connected to the input end of the decoder 52. Here, since the data bus is 6 bits, the input end of the decoder 52 is also 8 bits.

The outputs of the timing generator 55, φA to φH (
(shown) are connected to the input terminal of the Y driver 54 and the S input terminals of the three-step latch circuits 51a to 51b, respectively.

The output of the decoder 52 goes to the input terminal of the X driver 53, and the output of the X driver 53 and the output of the Y driver 54 go to L.
It is connected to the ED display body 56. Here, the LlnD display body 56 has an external appearance as shown in FIG.
A group of LEDs is mounted on the line score. And that LED #
consists of eight blocks, each block being connected to be controlled by the output group of the Y driver 54.

That is, the LP! shown in FIG. D group is X driver 5
They are arranged to be driven in a matrix by M and Y drivers 54. And timing generator 5
The output timing (φA to φH) of No. 5 is a shift pulse as shown in the timing diagram of FIG. That is, Y
The driver 54 sequentially drives the 8 blocks of the L)IiD group in Figure 2 in response to the pulses shown in Figure 7.

Next, we will explain how data is transferred from the apo to the note display section.

First, the CPU selects one of the AD2 to AD9 signals (/) in the figure to instruct what kind of note is to be displayed where in the eight blocks of the note display area, and at the same time
Generates WR signal. For example, the leftmost note LF
When it is desired to display a predetermined musical note on the iD block, the AD2 signal is selected and predetermined scale data is placed on the data bus. Among the outputs of the AND circuit group 50, the ψ2 signal becomes active, and the 6-step latch circuit 51a takes in the scale data on the data bus. Here, the six-step latch circuit 51a has a configuration as shown in FIG.
Data is read through the φ terminal and outputted through the S terminal. Therefore, the three-step latch circuit 5
1a transfers scale data to the decoder 52 using the φA signal shown in FIG. The decoder 52 converts the scale data into a predetermined LED lighting signal and drives the X driver 53. In this case, since one block of LED displays is composed of 16 LEDs, the output of the decoder 52 is 16.

That is, the LFiD display body 56 is driven only according to the output timing chart of the timing generator 55.
It may be asynchronous with the data transfer from CP[J.

With the above configuration, the CPU can transfer any scale data to any display unit at any time, reducing the processing load on the CPU and making program configuration easier. become.

Next, the musical tone generating section 6 will be explained in detail.

FIG. 8 is a detailed diagram of the musical tone generator. 80 is a group of musical tone selection switches, 81 is a vibrato and sustain effect switch that controls the musical sound waveform, 82 is an AND circuit, 8
3 is a musical tone generation circuit, 84 is a filter, 85 is an amplifier circuit, and 86 is a speaker.

The data bus is connected to the D and N input terminals of the musical tone generation circuit.
The AND circuit 82 receives the ADIQ signal and the WR bright signal, and its output is the WR signal of the musical tone generating circuit 8!1.
Connected to the input end.

The musical tone selection switch group 80 and the effect switch 81 are each connected to a musical tone generation circuit 83.

The output of the musical tone generation circuit 83 (indicated by OUT) is sent to the input terminal of the filter 84, and the output of the filter 84 is sent to the amplifier circuit 85.
The output of the amplifier circuit 85 is connected to the input terminal of the speaker 86, respectively.

When the CPU generates musical tones, it selects the AD10 signal,
Next, put the specified scale data on the data bus, and at the same time
Generate R signal money. The musical tone generating circuit 83 reads the musical scale data applied to the DIN terminal from the WR bright signal, recognizes the musical scale data, and synthesizes musical tones. As the musical tone generation circuit, a currently commercially available LSI for musical tone generation is sufficient, and its peripheral circuits are also well known as electronic circuits for electronic musical instruments. In this embodiment, the musical tone generator L8 is positioned as a custom LSI and is applied. Naturally C
Must have PU data reception function.

As explained above, the CPU can easily reproduce beautiful musical tones by transferring to the address of the predetermined scale code f:AD10.Next, the switch unit 7 will be explained in detail.

a 91%l is a detailed diagram of the switch section. 90a-9
0c is a 3-sart buffer as shown in Fig. 10, which is controlled by 8 human-powered 14V power, 91 is a mode switch for setting each mode of composition, correction, and playback, 92 is a start switch, 93 (dHiND switch, 94- 97
98 is a rotary digital switch for correction or octave shift during playback; 99 is a rotary digital switch for correction or key adjustment during playback; 100 and 101 are rotary digital switches for adjusting the key during playback. Mode switch f91, start switch 92, and end switch 95, which are AND circuits
are respectively connected to the input terminals of the 3-state buffer 90a, and the cursor movement switches 94 to 97 are respectively connected to the input terminals of the 3-state buffer 90b. Three state buffers 90a, 90t+ and 90 are connected to the input terminal of the s-state buffer 90c.
The outputs of each of the 0's are commonly connected to the data bus. Rp (i) is connected to one input terminal of AND circuits 100 and 101, ADl 1 signal is connected to the other input terminal of AND circuit 100, and ADl 1 signal is connected to the other input terminal of AND circuit 101. The HAD12 signals are connected to each other.The output of the AND circuit 100 is connected to the three-state buffers 90a and 90.
The outputs of the AND circuit 101 are connected to the respective S input terminals of the 8 input terminals of the 3-state buffer 90c.

Next, the operation will be explained.

As a CPU, switch status ri! When you want to know this, first, by activating the AD11 signal and the RD double signal, the states of each switch from the mode switch 91 to the cursor movement switch 97 are output on the data bus. ,0
PIJ should read and store the data. Also, ADI
By activating the /L signal and the RD double signal, it is possible to know the switch-like caps of the rotary digital switches 98 and 99.

Next, follow the operating instructions and explain the function of each switch.
First, the mode switch 91 is set to composition mode, and the start switch 92t is turned on.

In this state, the CPU detects audio input according to the TKMP signal. Specifically, the pitch data from the audio pitch extractor 3 is taken in, converted into scale data, and stored in the RAM 4 in order. Next, when the voice input is finished, turn on the end switch 93 to end the composition mode.
Turn on the start switch 92. The CPU detects this state and reproduces the musical scale data from the beginning to the eighth in the RAM 4 to the note display section 5 and the musical tone generation section 6. in this case,
The switch data of the rotary digital switch 98 for octave shift and the rotary digital switch 99 for adjusting the key are referred to. For example, both rotary digital switches 98 and 99 are set to 111 in the shift flow
, the scale data in RAM 4 is played back until that time. Also, rotary digital switch 9B for octave
If it is at a position one octave up, the scale data in RAMA is shifted up one octave and then played back.

At this time, the scale data in RAMd remains unchanged, and only the scale data to be transferred to the note display section 5 and musical tone generation section 6 is processed. It has the function of converting into short and long lengths and reproducing them. Specifically, C11
AII+ 84+ If you play a melody like ``4'' one step up, CIT + All + 01
1 r 1! ! The playback will be something like 4.

In the correction mode, cursor movement switches 94 to 9
7 allows you to arbitrarily modify notes at any position. In this case, the modification by moving the cursor modifies the scale data itself in RAMJ6-Also, when the start switch 92 is turned on in the modification mode, the next 8 scales are reproduced. That is, the operation is to play and correct eight notes at a time.Therefore, when the correction for eight notes is completed, you can turn on the start switch 92 and start correcting the next eight notes.

Next, the explanation of the regeneration mode, Regeneration to Power, is mostly similar to the operation described in the correction mode. First, the mode switch 91 is set to the reproduction mode, and the start switch 92 is turned on (7).The CPU sequentially reproduces the scale data in the RAMd to the note display section 5 and the tone generation section 6 in synchronization with the T1nMP signal.

At this time, it goes without saying that the reproduction is performed according to the switch shapes of the octave shift rotary digital switch 98 and the key adjustment rotary digital switch 99.

If the switch unit as described above is implemented, the CPU can easily read the switch data, and this can be done at any timing of the OPU. However, since the switches may be operated quickly, for example
There is no need to consider things like importing switches every 0m5.

In addition, it has abundant correction functions and various playback functions,
Once you have memorized the scale data, you can repeatedly modify it as many times as you like.
Moreover, it can be played in any octave and in any key.

Next, the tempo generator 8 will be explained in detail.

@Figure 11 is a detailed diagram of the tempo generation section.

110 is a variable oscillation circuit whose temperature can be changed by resistor Rx; 11
1 is a counter, 112 and 113 are differentiating circuits, 114 is a set-reset flip-flop (hereinafter abbreviated as SRF/F), 115, 117, and 118 are AND circuits, 116 is an OR circuit, 119 is a delay circuit, and 120 is a visual display means,
121 is an auditory display means, and 122 is a speaker on switch.

The output of the variable oscillation circuit 110 is connected to the clock input terminal of the counter 111, the output of the counter 111 is connected to the input terminal of the differentiating circuit 112, and the output of the differentiating circuit 112 (indicated by Tx) is connected to one input terminal of the OR circuit 116. be done.

A composition mode signal and a start signal (shown) are signals supplied from the switch section 7 and are connected to the input terminals of the AND circuit 115, respectively. The output of the AND circuit 115 is SR
It is connected to the reset input (indicated by R) of the F/F 114 and the set input (indicated by S) of the φL multiplied signal SRF/F 114, respectively.

Here, the φL multiplied signal is a signal supplied from the aforementioned audio pitch extractor 3, and is generated only when audio input is added, in synchronization with the pitch of the audio. Therefore, in the case of silence, the φL times signal is not generated.

The Q output of the SRF/F' 114 is connected to the input terminal of the differentiating circuit 113 and one input terminal of the AND circuit 117, and the output of the dividing circuit 161r 113 (indicated by BGN) is connected to the other one of the OR circuit 116. Input terminal and counter 111
are connected to the reset input terminal of the differential circuit 112 and the reset terminal of the differentiating circuit 112, respectively. The output of the OR circuit 116 is the AND circuit 1
17, one input terminal of the AND circuit 11B, and the input terminal of the visual display means 120, respectively.

In addition, IKH is connected to the other input terminal of the AND circuit 11B.
z signal is connected. The output of the AND circuit 117 (T
Y) is connected to the input terminal of the delay circuit 119, and the output of the delay circuit 119 is connected as the T JUMP signal to the INT input terminal of the CPU 1 in FIG.

The output of the AND circuit 118 is the speaker on switch 122
is connected to the input end of the auditory display means 121 via.

Here, the visual display means 120 is composed of a circuit for driving an LED and LffiD, and operates as a tempo display. The auditory display means 121 is composed of a speaker and a speaker drive circuit, and generates a tempo sound using an IKHz signal.

Next, the operation will be explained with reference to the timing diagram shown in FIG. FIG. 12 is a timing diagram of each part in FIG. 11. The tempo generator of this embodiment attempts to realize a tempo synchronization system in which the tempo is synchronized with the audio input at the beginning of a song.

First, put it in composition mode, turn on the start switch, and start singing the song, but if you put it in song mode and turn on the start switch, Q will start at the timing of t e and b of 121''21. The signal becomes level ＼.

In the timing region of ta in FIG. 12, the Q signal is level 1.
Therefore, the Tx times signal becomes the TY times signal, and T
A KMP signal is generated, but the CPU does not output T unless the start switch is input even in composition mode.
Do not perform transcription using IICMP signals. That is, ta
No transcription is performed in the timing region of Q, and when the start switch is turned on, the Q signal goes to level 1.
Q'l'll in the timing area of tb because it becomes 1LK
No liMP signal is generated and no transcription is performed. In other words, even if you start in the composition mode, the score is not transcribed, which saves the memory area of RAM4.Next, if you start singing at the timing of tbc, the φL times signal will start to be input here, and the S RF/F114 is set. At the same time, the type 1 circuit operates for the rising voltage vrcta of this Q output, and a BGN signal is generated. This BGN signal is counter 1
11 and the differential circuit 112, a Tx multiplied signal is generated at a predetermined period after this BGN signal is generated, and in the tC region, a TBMP signal is generated by the BGN signal and the TX signal. 7t, the TZ signal is only available when the speaker on switch 122 is on.
This occurs at the timing shown in Figure 12. In other words, since these tempo checking means generate μ in any form, it becomes easy to determine the tempo of the song.

The counter 111 receives a clock from the variable oscillation circuit 110, divides the frequency thereof, and generates a tempo cycle determined by a resistor RX. Therefore, the Tx signal is a normal tempo pulse.

In addition, the Tlf1MP signal is created by delaying the Tz signal, but this is because the audio waveform is relatively unstable at the beginning of the audio, and if the audio pitch is extracted at this initial timing, the pinch extraction efficiency will decrease. Because we want to extract the pitch near the center of timing 1β in Fig. 12, an interrupt to the CPU (NT, that is, T
I! : MP multiplication signal is delayed slightly.

If you use the tempo generator as explained above, you don't have to worry about the beginning of the song, and you can also improve the RAM memory, and you can cut out the silent section when starting in playback mode. It is possible to faithfully reproduce the song from the beginning.

The entirety of the present invention has been explained above, and the following effects can be expected by implementing the present invention.

1) Relatively stable pitches of speech can be extracted.

2) Since a recorded song can be played back with octave shift and key adjustment, a wide range of melodies can be played back.

3) Recorded melodies (scale data) can be modified with a simple one-inch operation.

4) The voice pitch extraction section simultaneously detects the positive and negative peaks of the voice waveform, so the pitch detection efficiency is high.
Moreover, an extremely simple circuit configuration is sufficient.

5) There is no need to match the tempo at the beginning of the song,
Easy to sing and efficient use of RAM.

6) From the user's perspective, it is easy to learn absolute pitches; 7) Melodies composed by the user can be played back with multiple tones, making it possible to supply products with high commercial value. .

8) The audio pitch extraction unit is a relatively versatile extraction unit, so it can easily transcribe not only audio but also musical instruments. 9) Data is transferred using the CPU path line, so this You can easily add equipment such as printers or CRTs using pass lines.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the present invention, FIG. 2 is an external view of the LED note display section, FIG. 3 is a detailed diagram of the audio pitch extraction section, and FIG. FIG. 5 is a detailed view of the note display section, and FIG.
'; j: Detailed diagram of some blocks in Figure 5, Figure 7 is a timing diagram of Figure 5, Figure 8 is a detailed diagram of the musical tone generation section, and Figure 9 is a detailed diagram of the switch section. FIG. 10 is a detailed diagram of some blocks in FIG. 9, and FIG.
The figure is a detailed diagram of the tempo generating section, and FIG. 12 is a timing diagram of FIG. 11. 1... CPU 2... Address decoder 3... Audio pitch extraction section 4... RAM 5... Musical note display section 6... Musical tone generation section 7... Switch section 8... Tempo generation Section 30...Amplification circuit 31...Voltage follower 32...Inverting amplifier circuit 33.34...Peak hold circuit '55...Set-reset flip-flop 37...
・Delay circuit 3B...Oscillation circuit 39...Counter 40...Latch circuit 41...Multiple switch 42...AND circuit 43...Microphone 50...AND circuit group 51a to 51b. ...3-step latch circuit 52...
Decoder 53...X driver 54...X driver 55...Timing generator 80...Tone selection switch 81...Effect switch 82...AND circuit 83...Tone generation circuit 84...Filter 85...Amplification circuit 86...Speakers 90a-90c...3-state buffer 91...Mode switch 92...Start switch 93...End switches 94-97...Kanle movement switch 9B. ...Rotary digital switch for octave shift 99...Rotary digital switch for key correction 100.
101...AND circuit 110...Variable oscillation circuit 111...Counter 112.113...Differentiating circuit 114...Set-reset flip-prop 115.
117, 118...AND circuit 116...OR circuit 119...Delay circuit 120...Visual display means 121...Audible display means 122...Subika on switch

Claims (1)

[Scope of Claims] (1) At least pitch extraction means for extracting all basic pitches of the waveform of a voice or musical tone, a conversion device for converting pitch information obtained from the pitch extraction means into a musical scale IC, and the conversion device Record the output of step 1. It consists of a memory circuit for # and a means for visually or aurally expressing the memory contents of the memory circuit, and performs notation by sequentially converting input audio information into a musical scale and storing it,
Furthermore, by sequentially playing back the transcribed scales, the absolute +
1. A voice recognition type pitch learning device characterized in that it is configured to be able to perform the following learning. f21 1r￥The voice recognition pitch learning device according to claim 1, characterized in that it comprises a musical tone generation circuit 41 capable of generating a plurality of musical sound waveforms as an auditory reproduction means. (3) The voice recognition type pitch learning device according to claim 1, further comprising a tempo generating section, and performing memorization according to a tempo signal obtained from the core tempo generating section. (4) The voice recognition pitch learning device according to claim 1, further comprising a correction function so that all of the pitch data that has been transcribed can be corrected.