EP0131952A3 - Logik-Schaltungsanordnung - Google Patents

Logik-Schaltungsanordnung Download PDF

Info

Publication number
EP0131952A3
EP0131952A3 EP84108362A EP84108362A EP0131952A3 EP 0131952 A3 EP0131952 A3 EP 0131952A3 EP 84108362 A EP84108362 A EP 84108362A EP 84108362 A EP84108362 A EP 84108362A EP 0131952 A3 EP0131952 A3 EP 0131952A3
Authority
EP
European Patent Office
Prior art keywords
bfl
input
arrangement
circuit
logical circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP84108362A
Other languages
English (en)
French (fr)
Other versions
EP0131952A2 (de
Inventor
Klaus Hanno Dr. Ing. Wiedeburg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0131952A2 publication Critical patent/EP0131952A2/de
Publication of EP0131952A3 publication Critical patent/EP0131952A3/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0952—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using Schottky type FET MESFET
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018535—Interface arrangements of Schottky barrier type [MESFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)

Abstract

Zur Verbindung einer in BFL-Technik realisierten Logik-­ Schaltung mit einer in ECL-Technik realisierten Logik-­ Schaltung ist der Ausgang der BFL-Logik-Schaltung über einen BFL-Negator-Zweig mit dem einen Eingang und direkt mit dem anderen Eingang einer MESFET-Push-Pull-Stufe verbunden ist, die dem Eingang der ECL-Logik-Schaltung vorgeschaltet ist.
EP84108362A 1983-07-18 1984-07-16 Logik-Schaltungsanordnung Withdrawn EP0131952A3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3325873 1983-07-18
DE19833325873 DE3325873A1 (de) 1983-07-18 1983-07-18 Logik-schaltungsanordnung

Publications (2)

Publication Number Publication Date
EP0131952A2 EP0131952A2 (de) 1985-01-23
EP0131952A3 true EP0131952A3 (de) 1985-03-06

Family

ID=6204265

Family Applications (1)

Application Number Title Priority Date Filing Date
EP84108362A Withdrawn EP0131952A3 (de) 1983-07-18 1984-07-16 Logik-Schaltungsanordnung

Country Status (3)

Country Link
EP (1) EP0131952A3 (de)
JP (1) JPS6039919A (de)
DE (1) DE3325873A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4631426A (en) * 1984-06-27 1986-12-23 Honeywell Inc. Digital circuit using MESFETS
JPS61125224A (ja) * 1984-11-21 1986-06-12 Sony Corp 半導体回路装置
JPS61202523A (ja) * 1985-03-06 1986-09-08 Fujitsu Ltd 半導体集積回路
US5075885A (en) * 1988-12-21 1991-12-24 National Semiconductor Corporation Ecl eprom with cmos programming
FR2648971B1 (fr) * 1989-06-23 1991-09-06 Thomson Composants Microondes Circuit d'interface de sortie entre deux circuits numeriques de natures differentes

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
IEEE JOURNAL OF SOLID STATE CIRCUITS, Band SC-16, Nr. 5, Oktober 1981, Seiten 578-584, New York, US;C.D. HARTGRING et al.: "Silicon MESFET digital circuit techniques" *
IEEE JOURNAL OF SOLID STATE CIRCUITS, Band SC-17, Nr. 3, Juni 1982, Seiten 569-584, New York, US; G. NUZILLAT et al.: "GaAs MESFET IC's for gigabit logic applications" *
IEEE JOURNAL OF SOLID STATE CIRCUITS, Band SC-9, Nr. 5, Oktober 1974, Seiten 269-276, New York, US; R.L. VAN TUYL et al.: "High-speed integrated logic with GaAs MESFET's" *
IEEE TRANSACTIONS ON ELECTRON DEVICES, Band ED-27, Nr. 6, Juni 1980, Seiten 1074-1091, New York, US;K. LEHOVEC et al.: "Analysis of GaAs FET's for integrated logic" *

Also Published As

Publication number Publication date
EP0131952A2 (de) 1985-01-23
DE3325873A1 (de) 1985-01-31
JPS6039919A (ja) 1985-03-02

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Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

PUAL Search report despatched

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AK Designated contracting states

Designated state(s): AT BE CH DE FR GB IT LI NL

AK Designated contracting states

Designated state(s): AT BE CH DE FR GB IT LI NL

17P Request for examination filed

Effective date: 19850627

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19870110

RIN1 Information on inventor provided before grant (corrected)

Inventor name: WIEDEBURG, KLAUS HANNO, DR. ING.