EP0130974A1 - Puce a integration tres poussee comportant un circuit de test - Google Patents

Puce a integration tres poussee comportant un circuit de test

Info

Publication number
EP0130974A1
EP0130974A1 EP19830900478 EP83900478A EP0130974A1 EP 0130974 A1 EP0130974 A1 EP 0130974A1 EP 19830900478 EP19830900478 EP 19830900478 EP 83900478 A EP83900478 A EP 83900478A EP 0130974 A1 EP0130974 A1 EP 0130974A1
Authority
EP
European Patent Office
Prior art keywords
circuit
chip
integrated circuit
latches
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19830900478
Other languages
German (de)
English (en)
Inventor
John J. Zasio
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Storage Technology Partners II
Original Assignee
Storage Technology Partners II
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Storage Technology Partners II filed Critical Storage Technology Partners II
Publication of EP0130974A1 publication Critical patent/EP0130974A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G01R31/318538—Topological or mechanical aspects

Definitions

  • This invention relates to large scale and very large scale integrated circuits (LSI and VLSI) and more particularly to integrated circuit chips including CMOS logic circuitry. Still more particularly, the present invention relates to VLSI chips including integral test circuitry which is utilized to test the chip prior to packaging in an integrated circuit package.
  • LSI and VLSI large scale and very large scale integrated circuits
  • integrated circuit chips including CMOS logic circuitry.
  • the present invention relates to VLSI chips including integral test circuitry which is utilized to test the chip prior to packaging in an integrated circuit package.
  • the yield in a chip manufacturing process (i.e., the number of properly operating chips obtained from each wafer) is often less than 10 percent. Therefore, chip testing is generally done while the chip is part of a wafer. The wafer is then separated into individual chips and properly operating chips are packaged integrated circuits. In order to test a chip, it is necessary t make electrical contact with some or all of the I/O pads. A faulty connection can result in a determination that the chip under test is defective, even though such aay not be the case. 2. Description of the Prior Art
  • the most common device for testing chips is a probe which physically contacts each one of the I/O pads of the chip. With smaller sized chips, contact is not difficult and this device is acceptable. As the number of pads increases, however, it become very difficult to produce a probe which can aake positive contac with each I/O pad. Slight angular rotation of the probe with respect to the chip will cause misalignment and aissed contact, thereby resulting in a determination that the chip is faulty. Probes of this type which are used to test large chips are extremely expensive due to the rigid aechanical tolerances which must be aaintained in order to insure that proper contact will be aade with the I/O pads.
  • the multiplexer test circuitry of the prior art device is designed to be removed from the chip after testing is accomplished, resulting in the waste of a significant amount of semiconductor material.
  • the present invention is directed to an improvement in the testing of integrated circuits containing a large number of I/O pads.
  • the invention includes an integrated circuit having integral test circuitry which includes a shift register having storage locations corresponding to some or all of the I/O pads.
  • Test signals are serially entered into the shift register and subsequently transferred from the shift register into the internal circuit of the chip to thereby test the chip.
  • Output signals which are generated by the internal circuit in response to the application of the test signals are transferred to the shift register and subsequently serially shifted out of the register.
  • Control of the testing operation is provided by clock circuitry which requires a very small number of I/O pad connections.
  • the shift register technique greatly reduces the number of I/O pads which must be contacted to perform a test on the chip.
  • all of the I/O pads to which connection is required for testing may be located on a single side of the chip, thereby facilitating viewing of the connections under the necessary magnification.
  • the chip may be designed so that the test circuitry remains a part of the chip and can be utilized after packaging in order to perform further tests.
  • the integral test circuitry is especially useful when the chip is fabricated with CMOS devices, since CMOS has the characteristic of little or no power drain under DC conditions.
  • the associated probe which is utilized to test the chip may be a very simple and inexpensive device. The cost of providing additional circuitry on the chip to facilitate testing is therefore outweighed by the fact that the cost of testing is greatly reduced.
  • FIGURE 1 is a diagra atic top plan view of the chip of the present invention.
  • FIGURE 2 is a top plan view of a corner of the chip showing control circuitry used in testing the chip.
  • FIGURE 3 is a schematic diagram of an input driver and associated latch.
  • FIGURE 4 is a schematic diagram of an output driven and associated latch.
  • FIGURE 5 is a block diagram showing the provision of complementary inputs to the control circuit.
  • FIGURE 6 is a schematic diagram of the input buffer of FIGUR 5.
  • FIGURE 7 is a schematic diagram of clock circuitry utilized to generate timing signals to control the testing of the chip.
  • FIGURE 8 is a timing diagram showing various operations of the test circuit.
  • FIGURE 9 is a schematic diagram of the output circuitry of the test circuit.
  • the present invention comprises an integrated circuit 10 which includes internal circuitry 12 connected to a plurality of I/O pads 14 via I/O drivers 16.
  • the integrated circuit in the present embodiment employs very large scale integration (VSLI) and includes two hundred and fifty-six I/O pads 14. Seven of the I/O pads 14, designated DI, A, B, C, D E, and DO, are connected to clock control circuitry 18 which form part of the test circuitry used to test the internal circuit 12.
  • VSLI very large scale integration
  • a shift register 20 including a plurality of individual latches is formed around the perimeter of the chip 10 adjacent th I/O pads 14.
  • a single bit shift register or latch is connected t each pad 14, with the exception of dedicated pads utilized for ground or power supply connections (not shown) and the test pads.
  • Test signals are provided at the input pad DI and are serially shifted into the latches until all of them are loaded. The loading is controlled by the control circuit 18.
  • the test signals are transferred to the internal circuit 12 via the I/O drivers 16.
  • the internal circuit 12 upon receipt of the test signals, the internal circuit 12 generates output signals, the values of which indicate whether or not the circuit is operating properly. These output signals are transferred back into the latches through the I/O drivers 16.
  • the contents of the latches are then serially shifted out of the chip at the DO, or data out, pad. These operations are all controlled by means of the control circuitry 18.
  • the chip 10 is typically formed by utilizing photolithographic techniques in which a number of aasking operations are performed to fora a plurality of transistor cells.
  • the internal circuit 12 is derived fro blocks composed of four CMOS transistor pairs. The blocks are formed by a step and repeat operation so as to result in a regular array.
  • the internal circuit includes 25 columns and 80 rows of blocks.
  • Final steps in the foraation o the chip include the laying down of metallization patterns which interconnect the individual transistors so as to determine the function of each block.
  • the functions of chips are thus customized by means of the metallization layers.
  • the circuit functions which may be obtained vary from a simple inverter to complex latches or flip flops (which require interconnection of several blocks) .
  • the completed internal circuit is comprised of a number of registers and a large amount of combinatorial logic.
  • the registers In order to test the chip, the registers must all be preloaded to desired values. This may be accomplished by cycling signals from the input pads through the internal circuitry until the registers are loaded with the appropriate value. However, this may require the circuit to go through an excessively large number of cycles, thereby resulting in an unreasonably long test time.
  • the internal circuit is designed so that all the registers may be serially connected and loaded directly, thus eliminating the need to cycle signals through the combinatorial logic. Such a structure is well known in the art and need not be described in detail here. After the registers have been loaded, the circuit is switched to connect the internal circuit so that it is in a normal run mode.
  • both the internal registers and the external register 20 are loaded through the DI pad, with the control circuit 18 determining whether input signals at the DI pad are directed to the external shift register 20 or to the internal registers.
  • FIGURE 2 the corner of the chip 10 containing the I/O pads used in conjunction with the test circuit is shown.
  • Input signals from the DI pad and the clock pads A-E are applied to input buffers 22, which supply normal and inverted signals.
  • One of the data in signals is connected to a first latch 20a and the clock signals are in turn coupled to clock driver circuitry 24 which provides clocking signals to control the operation of the testing circuitry.
  • Output signals from the last latch 20b are applied to a data out circuit 26, which in turn supplies output signals to an output buffer 28 connected to the data out pad DO.
  • FIGURE 3 shows driver circuitry which is utilised when a pad is employed as an input pad
  • FIGURE 4 shows driver circuitry utilized when >* * » & l is employed as an output pad.
  • the pads function either as input or output pads, although in certain instances a pad aay operate as both an input and output pad.
  • the input driver circuitry includes an input buffer comprised of inverters 30 and 32, an input resistor 34 and diodes 36 and 38 which serve to protect against static discharge while handling the chip.
  • the input circuit provides complementary outputs I and ⁇ which are delivered to the internal circuit.
  • the output driver circuitry includes inverters 40 and 42 which receive output signals from the internal circuit 12 and operate as an output buffer.
  • the latches utilized in the present embodiment of the invention are master-slave or A-B type latches.
  • Each latch includes four inverters 44-50 and six transmission gates T1-T6.
  • the operation of the master-slave latch is such that data will be entered into the A latch on a first clock pulse and transferred to the B latch on a second clock pulse, thus insuring that a data pulse does not mistakenly pass through a latch and to one or more subsequent latches on the same clock pulse.
  • a first clock pulse causes data to be loaded into the A latch and a second, independent clock pulse causes data to be transferred from the A latch to the B latch.
  • the use of an A-B lath and independent clock pulses reduces precision requirements with respect to the clock (i.e. rise time and pulse shape need not be tightly controlled) while maintaining precise shift register operation.
  • the test circuitry input pads A-E and DI are each connected to an input buffer IB which provides complementary output signals.
  • the input buffers include inverters 52 and 54, resistor 56 and protection diodes 58 and 60.
  • the outputs of the buffers are utilized by the clock circuitry 24 to generate internal clock signals A ⁇ , B ⁇ and CX which are used to control the operation of the internal circuit 12 and external clock signals AB, AS, BE, BE, CE, CE, DE, DE and CS.
  • the clock circuitry (FIGURE 7) includes HAND gates
  • FIGURES 3 and 4 indicate which clock signals are used to control the transmission gates T1-T6.
  • the transmission gates T1-T4 are clocked the same whether or not a latch is connected to an input driver or output driver.
  • the gates T5 and T6, however, are driven differently depending upon whether the shift register is connected to an input driver or output driver.
  • test signals are loaded into the latches by controlling gates T1-T4 by means of clock signals A and B. During this time, the gate T5 is on.
  • the control signals for this shifting operation are shown in FIGURE 8A.
  • the E clock signal is switched and test signals are loaded into the internal registers (shown in FIGURE 8B) • Susequently, the D clock signal is used to transfer the test signals from the latches to the internal circuit 12 via the input buffers to initiate a test. If a latch is connected to an input driver circuit (FIGURE 3 ⁇ , the gate T5 will remain on and gate T6 will be turned on thereby enabling test data to be transferred from latch 20c to the internal circuit 12 via the input buffer.
  • a latch is connected to an output buffer (FIGURE 4) then the gate T5 will be closed and T6 and Tl opened, thereby enabling the latch 20d to receive and store an output signal from the internal circuitry 12 via the output buffer.
  • This operation is controlled by the signals CE and AE, as shown in FIGURE 8C.
  • the circuit can be put back into the shift mode (FIGURE 8A) to serially transfer the signals out of the chip through the DO pad. The output signals can then be compared with the desired output signals to deteraine if the circuit is properly operating.
  • FIGURE 8A shows the- timing signals used to shift test signals through the external
  • FIGURE 8A shows the timing signals used to shift data through the internal shift register *
  • test patterns are intially shifted into the external shift register 20 by the application of control signals shown in FIGURE 8A. Additional test signals are then shifted into the internal shift register by applying the clock signals shown in FIGURE 8B (clock signal E is shifted from 1 to 0) .
  • An actual test is intiated by applying the signals shown in FIGURE 8C, which causes the signals in the external shift register to be applied to the combinatorial logic in the internal circuit 12.
  • the output signals generated in response to the application of the test signals will appear almost immediately at the outputs of the internal circuits and will be loaded into the external shift register 20.
  • the shift signals of FIGURE 8A are then reapplied to shift the results out of the external shift register.
  • the shifted signals are transferred to the data output pad DO through the data output circuit 26 which is shown in greater detail in FIGURE 9.
  • the signal DOE is the output of the last latch (20b in FIGURE 2) of the external shift register 20, and the signal DOI is the output of the last latch of the internal shift register in the internal circuit 12.
  • These singals are applied to NAND gates 110 and 112, with the signal E determining which output is applied to a NOR gate 114. (The contents of the internal registers will be serially shifted out through the DO pad when new test signals are entered.)
  • the output of the NOR gate 114 is connected to an inverter 116, which is in turn connected to the output buffer 28.
  • all of the circuitry on the chip 10 is comprised of CMOS devices. These devices have the characteristic that they consume little or no DC power. Therefore, the test circuitry can be left on the chip and packaged with the internal circuit without increasing power dissipation of the device. After the packaging, the test circuitry can be utilized to provide a functional test and a wiring check, i.e., to determine whether the connections between chips are faulty. This is accomplished simply by loading the values present at the I/O pads of a chip into the external shift register 20 and shifting the contents out of the chip. The contents can then be compared to then known value of the output from other chips- which are connected to corresponding I/O pads of the chip under test.
  • the chip 10 includes a number of dedicated ground and power supply pads. These pads do not require latches to be associated with them in order to test the internal circuit. However, latches are included which correspond to these pads and may be used to store information representing a part number for each chip. Each latch input adjacent to each ground and power supply pad can be selectively connected to either ground or voltage. In order to determine the part number, the voltage applied to the sampling wires are strobed into the latches. These values are then shifted out and the binary combination from the pads rep ⁇ resents the part number of the chip. This test may be accom ⁇ plished after the chip has been assembled onto a PC board, thereby enabling a tester to determine if the proper chip has been installed without having to look at the chip (which may be in an inaccessible location) .
  • the internal circuit 12 is fabricated from a regular array of transistors as previously described.
  • the I/O drivers 16 and latches 20 could also be fabricated from this regular array.
  • this circuitry is specifically configured so as to achieve maximum packing density. That is, the latches can be made more dense by specially designing their physical layout rather than employing the regular array to fabricate them.
  • the I/O drivers 16 may utilize a custom design apart from the regular array. This design may, however, be customized to operate in several different ways, i.e., as an input driver, output driver, ground connection or the like.
  • the present invention provides a VLSI chip which includes integral test circuitry which is designed to remain a permanent part of the chip.
  • the test circuitry includes a shift register which surrounds the internal chip circuit and control circuitry for controlling testing operations.
  • the provision of the test circuitry greatly reduces the number of pins which must be contacted in order to test the integrated circuit test.
  • the pads which must be contacted may all be located on a single side of the chip, thereby simplifying the connection of a test probe.
  • the test circuit may remain with the chip and be used to test wiring connections between chips.
  • the test circuitry may be used to store a binary part number for each chip.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Une puce de circuit intégré VLSI (very large scale integration) (10) comprend un circuit de test formé dans la puce. Ce circuit de test comprend un registre à décalage (20) comprenant une pluralité de bascules disposées à proximité des bornes d'entrée/sortie (14) de la puce (10). Un circuit de commande (18) permet à des données de test d'être introduites de manière sérielle dans le registre à décalage (20) pour être ensuite introduites à la fréquence d'horloge dans le circuit interne (12) de la puce (10) pour en vérifier le fonctionnement. Les signaux de sortie produits par le circuit interne (12) en réponse aux signaux de test sont transférés dans le registre à décalage (20). Le contenu du registre à décalage (20) est ensuite extrait du dispositif par décalage sériel et peut être comparé aux résultats désirés afin de déterminer si la puce (10) fonctionne correctement. L'inclusion de ce circuit permet de réduire considérablement le nombre de bornes (14) qui doivent être mises en contact pour vérifier le fonctionnement de la puce (10).
EP19830900478 1982-12-27 1982-12-27 Puce a integration tres poussee comportant un circuit de test Withdrawn EP0130974A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1982/001819 WO1984002580A1 (fr) 1982-12-27 1982-12-27 Puce a integration tres poussee comportant un circuit de test

Publications (1)

Publication Number Publication Date
EP0130974A1 true EP0130974A1 (fr) 1985-01-16

Family

ID=22168496

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19830900478 Withdrawn EP0130974A1 (fr) 1982-12-27 1982-12-27 Puce a integration tres poussee comportant un circuit de test

Country Status (2)

Country Link
EP (1) EP0130974A1 (fr)
WO (1) WO1984002580A1 (fr)

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JPS61265829A (ja) * 1985-05-20 1986-11-25 Fujitsu Ltd 半導体集積回路
JPH0627785B2 (ja) * 1986-07-08 1994-04-13 富士通株式会社 半導体集積回路
JPS6337270A (ja) * 1986-07-31 1988-02-17 Fujitsu Ltd 半導体装置
US5059819A (en) * 1986-12-26 1991-10-22 Hitachi, Ltd. Integrated logic circuit
US4860288A (en) * 1987-10-23 1989-08-22 Control Data Corporation Clock monitor for use with VLSI chips
NL8801835A (nl) * 1988-07-20 1990-02-16 Philips Nv Werkwijze en inrichting voor het testen van meervoudige voedingsverbindingen van een geintegreerde schakeling op een printpaneel.
JP2839547B2 (ja) * 1989-05-02 1998-12-16 株式会社東芝 半導体集積回路装置
US5150047A (en) * 1989-07-21 1992-09-22 Nippon Steel Corporation Member for use in assembly of integrated circuit elements and a method of testing assembled integrated circuit elements
US5132614A (en) * 1989-08-03 1992-07-21 Kabushiki Kaisha Toshiba Semiconductor device and method and apparatus for testing the same
GB8921561D0 (en) * 1989-09-23 1989-11-08 Univ Edinburgh Designs and procedures for testing integrated circuits containing sensor arrays
GB2253710B (en) * 1989-09-23 1993-08-25 Univ Edinburgh Test circuit
JP2925287B2 (ja) * 1990-10-17 1999-07-28 富士通株式会社 半導体装置
GB2288666B (en) * 1994-04-12 1997-06-25 Advanced Risc Mach Ltd Integrated circuit control
GB2290877B (en) * 1994-07-01 1997-08-20 Advanced Risc Mach Ltd Integrated circuit test controller
US5869979A (en) 1996-04-05 1999-02-09 Altera Corporation Technique for preconditioning I/Os during reconfiguration

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AU530415B2 (en) * 1978-06-02 1983-07-14 International Standard Electric Corp. Integrated circuits
US4357703A (en) * 1980-10-09 1982-11-02 Control Data Corporation Test system for LSI circuits resident on LSI chips

Non-Patent Citations (1)

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Also Published As

Publication number Publication date
WO1984002580A1 (fr) 1984-07-05

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