EP0106044A2

EP0106044A2 - Space charge modulating semiconductor device and circuit comprising it

Info

Publication number: EP0106044A2
Application number: EP83107607A
Authority: EP
Inventors: John Lawrence Freeouf; Thomas Nelson Jackson; Steven Eric Laux; Jerry Mac Pherson Woodall
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 1982-09-17
Filing date: 1983-08-02
Publication date: 1984-04-25
Also published as: US4638342A; JPS5961190A; JPH0213928B2; EP0106044A3; EP0106044B1; DE3382340D1

Abstract

A semiconductor device employing two-dimensional space charge modulation in a semiconductor body 1 has an approximately Debye length wide ohmic contact 3 and a rectifying contact 2 positioned within a Debye length of the contact 3. Electrical conduction between the contact 3 and a remotely positioned contact 4 is controlled by the potential applied to the rectifying contact 2.

Description

This invention relates to semiconductor devices.
The invention seeks to provide a semiconductor device in which electrical conduction between a pair of contacts is controlled by space charge modulation effected via a third contact.
A semiconductor device comprising first and second contacts disposed on one side of a semiconductor body, the second contact being a rectifying contact, and a third contact disposed on the semiconductor body in a position remote from the first and second contacts, is characterised, according to the invention, by the first contact having a dimension substantially equal to or less than to the Debye length in the semiconductor of the body and by the second contact being disposed a distance substantially equal to or less than said Debye length from the first contact.
How the invention can be carried out will now be described by way of example, with reference to the accompanying drawings, in which:-

FIG. 1 represents a semiconductor device according to the invention;
FIG. 2 is a diagram of one circuit configuration employing the device of FIG. 1;
FIG. 3 is a current voltage characteristic obtained with the circuit configuration of FIG. 2;
FIG. 4 is a diagram of another circuit configuration employing the device of FIG. 1;
FIG. 5 is a current voltage characteristic obtained with the circuit configuration of FIG. 4;
FIG. 6 represents another semiconductor device according to the invention; and
FIGS. 7 through 10 illustrate successive stages in a process for making the device represented in FIG. 6.

In accordance with the invention, a rectifying contact is placed within a Debye length of a second contact of the order of a Debye length in size on one surface of a semiconductor body and a third contact is placed elsewhere on the same semiconductor body. Under proper biasing the space charge in the semiconductor body under the rectifying contact can control the conduction between the other two contacts.
The Debye length is a characteristic distance in semiconductors. It is defined and discussed in the text "Physics of Semiconductor Devices" by S. M. Sze, Second Edition, pages 77 and 78, published by Wiley, N.Y.
An embodiment of the invention is represented in FIG. 1 wherein on one surface of a semiconductor body 1 there is positioned an intrinsically rectifying contact 2. The intrinsic conducting behavior of a contact may be defined as the two-terminal current voltage behavior of the contact when that contact is forming a two-terminal device with the substrate. The rectifying contact 2 surrounds or is parallel with a small width intrinsically ohmic contact 3 positioned a distance D from the rectifying contact 2. The dimension D is about equal to or less than the extrinsic Debye length of the semiconductor of body 1. The contact 3 has a dimension C that is also about equal to or less than the Debye length. A third, ohmic contact 4 is positioned a distance A from the contacts 2 and 3 on the opposite side of the semiconductor body 1.
The semiconductor of body 1 should be of sufficiently high resistivity to permit the space charge under the rectifying contact 2 to penetrate a physical distance into the semiconductor under moderate voltage levels to affect carrier flow between the contacts 3 and 4.
The semiconductor body 1 may be of silicon doped with 10¹⁵ impurity atoms per cubic centimeter. With this resistivity and dimensions maintained at C and D less than approximately 0.1 micrometers, the polarity of the signal on the contact 2 will affect current flow between contacts 3 and 4.
The device of FIG. 1 is preferably fabricated by using Schottky barrier contacts with different barrier heights so that ohmic or rectifying behavior is produced. Where the semiconductor 1 is silicon doped to about 10¹⁵ atoms per cubic centimeter with conductivity type n, the ohmic contacts 3 and 4 may be obtained using a relatively low barrier Schottky contact where that barrier height is about 0.2 to 0.3 eV. Such contacts can be obtained through the use of rare earth silicides as set forth in IBM Technical Disclosure Bulletin, Vol. 21, p. 2811. The rectifying contact 2 can be formed using a higher barrier Schottky contact. For a rectifying contact, the barrier height should be of the order of 0.8 eV, such as is obtainable with Au or PtSi on a silicon substrate.
An illustration of the operation of the device may be seen in connection with FIGS. 2 through 5 wherein FIGS. 2 and 3 illustrate a circuit and corresponding performance in one polarity and FIGS. 4 and 5 illustrate a circuit and corresponding performance in an opposite polarity.
Referring to FIG. 2 using a battery 6 of about 1.5 volts as a source of power, the semiconductor body 1 has one ohmic contact 4 connected to the battery 6 and the other ohmic contact 3 and rectifying contact 2 connected through a current indicator 7 to the other side of the battery 6.
Under these conditions a space charge under the rectifying contact 2 will penetrate the high resistivity body 1 far enough to affect the conductivity through the body 1 between the ohmic contacts 3 and 4.
In the body 1 of the device, for a voltage equal to zero, the depletion depth in 10 atoms per cc n-type silicon radiating from contact 2 would deplete the area below contact 3 when positioned lateral 0 to contact 2 for the intergap D of about 500A and contact size C of 0.15 micrometers. These dimensions result in the distance from the edge of the contact 2 to the center of contact 3 being of the order of a Debye length in semiconductor material of this resistivity. This would not permit any significant current flow between contacts 3 and 4.
Where the voltage is selected to be greater than zero, the depletion depth radiating from contact 2 would decrease thus allowing a clear conducting path of electrons between contacts 3 and 4. By appropriate choice of size for contact 3 and for the gap between contacts 2 and 3, that portion of the current through contact 3 dominates the flow for voltages of the order of 0.6V. Hence, a high impedance is maintained at contact 2 and a low impedance between contacts 3 and 4. Where the impressed voltage from battery 6 is less than zero, the depletion width will radiate even more below contact 2 than for the V=0 case and the current flow between contacts 3 and 4 will be very small.
Referring next to FIG. 3, there is shown the current voltage (I-V) characteristic curve for the circuit of FIG. 2. It will be apparent to one skilled in the art that the the curve of FIG. 3 is similar to that of an ordinary I-V curve for a diode. Since the silicon of the body 1 is doped n-type in this example, the IV characteristic of contact 3 is qualitatively that of a normal Schottky diode as shown in FIG. 3.
Using the device of the invention, ·it is also possible to provide an opposite or reverse diode characteristic. This is illustrated in connection with the circuit of FIG. 4 and the current voltage (IV) output characteristic of FIG. 5. In FIG. 4 the circuit configuration is such that the rectifying contact or contact segments 2 and the ohmic contact 4 are shorted together and the ohmic contact 3 is held at a positive potential with the battery 6. The (IV) characteristic of FIG. 5 is achieved by varying the voltage V of the battery 6 and observing the current flow through the current indicator 7.
Under these conditions, for V = 0, the depletion depth below contacts 2 and 3 remains as configured for the forward diode. However, for the condition V < 0, the electron accumulation situated directly below contact 3 as a result of a standard ohmic n ⁺ doping pocket or below the low barrier height of contact 3 is pushed farther into the semiconductor, effectively parting the depletion layers radiating from contact 2. This provides a clear path for electron flow between contacts 3 and 4.
For the condition where V > 0, the electron accumulation present below contact 3 is pulled closer to contact 3 than the previously described V = 0 case and no significant path of electron conduction exists between contacts 3 and 4.
The I-V characteristic corresponding to the circuit configuration of FIG. 4 is shown in FIG. 5. The characteristic polarity is clearly reversed and is in marked contrast to that of FIG. 3. The impedance of contact 2 also remains high in this reversed diode case.
In essence, the three-terminal device of the invention implements a reversing diode concept in that the polarity of conduction between the two contacts 3 and 4 is determined by the potential that is present on a high impedance contact 2.
The structure of the invention is susceptible of application by one skilled in the art to many circuits and structures in addition to the applications using the standard rectifying characteristics shown in FIGS. 3 and 5.
Specifically, the change in current between two contacts at a well-defined potential due to a change in potential at a separate third contact implies a transistor-like action.
As an illustration, the following application of the principles of the invention involves the performance equivalent of a device known as a Permeable Base Transistor described in the IEEE Transactions on Electron Devices, Vol. ED 25, No. 3, March 1978 and IEEE Transactions on Electron Devices, Vol. ED 27, No. 6, June 1980.
The Permeable Base Transistor has a small grating having a period of 400-3200 Angstroms, and a thickness of 50-300 Angstroms imbedded in single crystal GaAs. This device has very favorable performance in speed and power consumption but the extremely small device dimensions and the imbedding process have made manufacture difficult.
Employing the principles of the invention, the structure of FIG. 6 will provide an equivalent performance to the Permeable Base Transistor with a much simpler construction. The structure of FIG. 6 has an ohmic contact 4 on one surface performing an analogous function to the source electrode in the permeable base transistor. A series of low impedance Schottky barrier electrodes or ohmic contacts 3A, 3B, 3C, etc., serve the function of the drain electrode of the permeable base transistor. A series of higher impedance Schottky rectifying contacts, labelled 2A, 2B, 2C, etc., serve the function of the gate electrode of the permeable base transistor. The distance between the contacts 2A2C, etc. and 3A3C, etc. is of the order of a Debye length as is the width of the contacts 3A3C, etc. The body 1 is of n-conductivity type GaAs doped to around 10 atoms per cubic centimeter.
Thus the structure of FIG. 6 employs surface Schottky barrier gate electrodes 2A-2C, etc. rather than a buried grid and takes advantage of the fact that for small enough device structures, where the electron spacing is of the order of a Debye length, the performance is comparable with Permeable Base Transistor performance.
In accordance with the invention, the two dimensional depletion layer spreading from the gate electrodes can give controlled device operation for such surface electrodes. Doping pockets of n ⁺ labelled 8A, 8B, 8C, etc., under each of the low barrier Schottky or ohmic contacts 3A, 3B, 3C, etc., are provided to prevent the phenomenon of punch-thru between the gate electrodes 2A2C, etc., and drain 3A-3C, etc., electrodes.
In order to produce the structure of FIG. 6, the steps illustrated in FIGS. 7 through 10 may be employed as an illustrative process.
The process of FIGS. 7 to 10 will produce a structure with an interdigitated series of contacts.
In FIG. 7, a GaAs substrate is provided with an ohmic layer 4 on one surface. A higher n conductivity region 1A is provided adjacent to what will be the source contact 4, and is employed to decrease parasitic source resistance. A higher resistivity n GaAs region labelled 1B is to serve as the active region of the device.
Referring next to FIG. 8, a double layer of metallization is provided comprising a first layer 9 adjacent to the surface of the higher resistivity semiconductor region lB and a second layer 10 above layer 9. The metal layers 9 and 10 are such that they perform differently with respect to an eroding operation so that the top layer 10 can be patterned and then used as a mask to pattern an undercut 11 on the lower metal layer 9. When metals such as platinum for the second layer 10 and tungsten for the first layer 9 are employed and the technique of plasma etching well known in the art is utilized, the structure of FIG. 8 is readily achieved. The electrode spacings in the 0 patterning are of the order of 300A. The undercut 11 will permit vertical deposition in a later step without shorting.
Referring next to FIG. 9, the electrode structure involving the metal layers 10 with the undercut layer 9 of FIG. 8 is employed in a standard ion implantation of n conductivity type impurities which operates to form the n⁺ pockets 8A and 8B described in connection with FIG. 6 close to the undercut 11. Since an implanting operation will require annealing that operation is done at this point.
Since the first layer electrode metal 9 is in contact with the GaAs lB during an annealing step, it will be apparent to one skilled in the art that the metal selected for the first layer 9, if annealing and implantation are to be used, must be a metal like tungsten or an alloy of titanium and tungsten that can withstand a proximity anneal.
Other techniques such as diffusion for forming the n⁺ regions 8A and 8B could be used.
Referring next to FIG. 10, the vertically differentiated or two-level metallisation gate electrodes 2 are used as shadow masks to define the drain electrodes 3. This is accomplished by a vertical deposition of a metal such as aluminum 12 which is confined by the overhang of metal layer 10.
Large contacts to the gate 2 and drain 3 electrodes of FIG. 10 are formed at the edge of the device in standard large scale integrated circuit practice, but are not shown.

Claims

1. A semiconductor device comprising first and second contacts disposed on one side of a semiconductor body, the second contact being a rectifying contact, and a third contact disposed on the semiconductor body in a position remote from the first and second contacts, the device being characterised by the first contact having a dimension substantially equal to or less than the Debye length in the semiconductor of the body and by the second contact being disposed a distance substantially equal to or less than said Debye length from the first contact.

2. A semiconductor device as claimed in claim 1, in which the first and third contacts are ohmic contacts.

3. A semiconductor device as claimed in claim 1 or claim 2, in which the third contact is a broad area contact disposed on the opposite side of the body to that on which the first and second contacts are disposed.

4. A semiconductor device as claimed in any preceding claim, in which said dimension of the first contact is about 0.15 microns and in which 0 the second contact is disposed about 500 A from the first contact.

5. A semiconductor device as claimed in any preceding claim, in which the first contact is a Schottky barrier contact with a relatively low barrier height and the second contact is a Schottky barrier contact with a relatively high barrier height.

6. A semiconductor device as claimed in claim 5, in which the first contact has a barrier height of from 0.2 to 0.3 eV and the second contact has a barrier height of about 0.8 eV.

7. A semiconductor device as claimed in any preceding claim, in which the semiconductor body is of n-type silicon doped with 10¹⁵ impurity atoms per cubic centimeter.

8. A semiconductor device as claimed in any preceding claim, in which each of the first and second contacts is one of an individual, interconnected set of contacts, the two sets of contacts being interlaced, and in which there is an individual high conductivity region provided in the semiconductor body adjacent each contact of the set comprising said first contact.

9. A circuit including a semiconductor device as claimed in any preceding claim and means to apply a bias voltage to the second contact of the device in order to control electrical conduction between the first and third contacts of the device.