US20010013613A1 - Semiconductor device and a method of fabricating material for a semiconductor device - Google Patents
Semiconductor device and a method of fabricating material for a semiconductor device Download PDFInfo
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- US20010013613A1 US20010013613A1 US09/781,498 US78149801A US2001013613A1 US 20010013613 A1 US20010013613 A1 US 20010013613A1 US 78149801 A US78149801 A US 78149801A US 2001013613 A1 US2001013613 A1 US 2001013613A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 71
- 239000000463 material Substances 0.000 title claims description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 230000015556 catabolic process Effects 0.000 claims abstract description 20
- 238000009826 distribution Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 12
- 239000000945 filler Substances 0.000 claims description 8
- 239000011810 insulating material Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 23
- 239000002019 doping agent Substances 0.000 description 11
- 238000001465 metallisation Methods 0.000 description 7
- 230000005684 electric field Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000007493 shaping process Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000002800 charge carrier Substances 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- VIKNJXKGJWUCNN-XGXHKTLJSA-N norethisterone Chemical compound O=C1CC[C@@H]2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 VIKNJXKGJWUCNN-XGXHKTLJSA-N 0.000 description 1
- 229910021339 platinum silicide Inorganic materials 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Abstract
Description
- This invention relates to a semiconductor device and a method of fabricating material for a semiconductor device.
- It is well known in the semiconductor art that the spread of the depletion region of a reverse-biased rectifying junction (and so breakdown voltage of that junction) can be increased by reducing the dopant concentration and increasing the size of a semiconductor region associated with the rectifying junction. However, although this enables the reverse breakdown voltage to be increased, it also increases the resistivity and length of the current path through the device when the rectifying junction is forward biased in the ON condition of the device. This means that the series resistivity of the current path for majority charge carriers through the device increases in proportion to approximately the square of the desired reverse breakdown voltage, so limiting the current handling capability of the device for a given maximum thermal dissipation.
- U.S. Pat. No. 4,754,310 (our reference PHB32740) addresses this problem by providing one of the regions forming the rectifying junction as a zone formed of first regions of one conductivity type interposed with second regions of the opposite conductivity type with the dopant concentrations and dimensions of the first and second regions being such that, when the rectifying junction is reversed biased in operation and the zone is depleted of free charge carriers, the space charge per unit area in the first and second regions balances at least to the extent that the electric field resulting from the space charge is less than the critical field strength at which avalanche breakdown would occur. This enables the required reverse breakdown voltage characteristics to be obtained using interposed semiconductor regions which individually have a higher dopant concentration, and thus lower resistivity, than would otherwise be required so that the series resistivity of the first and second regions and thus the ON resistance of the device can be lower than for conventional devices.
- It is an aim of the present invention to provide another way of improving the trade off between breakdown voltage and on resistance in vertical high voltage semiconductor devices where the word “vertical” should be understood to mean that the main current flow path through the device is between first and second main opposed surfaces of the device.
- According to one aspect of the present invention there is provided a semiconductor device wherein semi-insulative or leakage current paths are provided through a semiconductor region associated with a rectifying junction so that, when the rectifying junction is reversed biased in operation, the electrical potential distribution along the semi-insulative or leakage current paths causes the depletion region within the semiconductor region to spread through the semiconductor region to a greater extent than it would have done without the presence of the semi-insulative or leakage current paths so that the semiconductor region can be fully depleted of free charge carriers to enable the required reverse breakdown voltage to be achieved using semiconductor material that has a lower resistivity than would be required to achieve that breakdown voltage in the absence of the semi-insulating or leakage current paths.
- In one aspect, the present invention provides a semiconductor device having first and second opposed major surfaces, the semiconductor device comprising a semiconductor first region provided between second and third regions such that the second region forms a rectifying junction with the first region and separates the first region from the first major surface and the third region separates the first region from the second major surface, the first region having dispersed therein a plurality of resistive paths each extending through the first region from the second toward the third region and each electrically isolated from the first region, for example by an intervening insulating layer, such that, in use, when a reverse biasing voltage is applied across the rectifying junction an electrical potential distribution is generated along the resistive paths which causes a depletion region in the first region to extend further through the first region to increase the reverse breakdown voltage of the device.
- According to an aspect of the present invention, there is provided a semiconductor device as set out in claim1. The present invention also provides a method as set out in
claim 10. - The present invention thus enables a semiconductor device or material for forming a semiconductor device to be provided which enables the trade off between reverse breakdown voltage and on resistance to be improved in a manner that is different from that proposed in U.S. Pat. No. 4,754,310 and that may, at least in certain circumstances, be simpler and/or more economical to manufacture.
- Other advantageous technical features in accordance with the present invention are set out in the appended dependent claims.
- Embodiments of the present invention will now be described, by way of example, with reference to the accompanying diagrammatic drawings, in which:
- FIG. 1 shows a diagrammatic cross-sectional view through part of a first embodiment of a semiconductor device in accordance with the present invention;
- FIG. 2 shows a diagrammatic cross-sectional view similar to FIG. 1 through part of a second embodiment of a semiconductor device in accordance with the present invention;
- FIG. 3 shows part of the device of FIG. 1 or2 on an enlarged scale to illustrate operation of the device under reverse bias;
- FIG. 4 shows a graph of on-resistance (Ron) against reverse breakdown voltage (Vbv) to illustrate the effect of the present invention; and FIGS.5 to 7 illustrates steps in one example of a method that may be used in manufacturing the semi-conductor device shown in FIG. 1 or FIG. 2.
- It should be noted that (with the exception of FIG. 4) the Figures are diagrammatic, relative dimensions and proportions of parts having been shown exaggerated or reduced in size for the sake of clarity and convenience. The same reference signs are generally used to refer to corresponding or similar features in the different embodiments.
- Referring now to FIG. 1, this shows a semiconductor device1 in the form of a pn-n rectifier or diode. The semiconductor device 1 comprises a monocrystalline
silicon semiconductor body 10 having first and second opposedmajor surfaces semiconductor body 10 comprises a first relatively lowly dopedsemiconductor region 11 of one conductivity type, n-conductivity type in this example. Typically, the dopant concentration within the semiconductorfirst region 11 is 1016 atom cm−3. The semiconductorfirst region 11 is separated from the firstmajor surface 10 a by a semiconductorsecond region 12 of the opposite conductivity type (P conductivity type in this example) so that apn junction 13 is formed between the semiconductor first andsecond regions second region 12 will have a dopant concentration of 1019 atoms cm−3. - The
first region 11 is separated from the secondmajor surface 10 b by athird region 14 of the same conductivity type but more highly doped (n+ conductivity type in this example) than thefirst region 11. Thesecond region 12 forms an ohmic contact with afirst metallisation layer 15 forming one electrode of the diode while thethird region 14 forms an ohmic contact with asecond metallisation layer 16 forming the other electrode of the diode. - The structure of the diode1 described so far forms a conventional pn-n diode. However, in contrast to a conventional pn-n diode, the diode 1 shown in FIG. 1 has a plurality of electric
field shaping regions 20 extending through thefirst region 11 from thesecond region 12 to thethird region 14. - In the embodiment shown in FIG. 1, each field shaping region comprises a
layer 21 of semi-insulating or highly resistive material deposited in acorresponding opening 17 extending from the firstmajor surface 10 a through the second andfirst regions third region 14. The resistive orsemi-insulating layer 21 may be, for example, a layer of polycrystalline silicon doped with oxygen and/or nitrogen so as to have, for example, a resistivity of from about 107 to about 109 ohm cm or may be a layer of silicon nitride having a resistivity of, for example, from about 107 ohm cm to about 109 ohm cm. Thesemi-insulating layer 21 is separated from the walls of the opening 17 by alayer 22 of an insulating material, typically silicon dioxide. Typically, thesemi-insulating layer 21 will have a thickness of 0.5 μm (micrometers) while theinsulating layer 22 will have a thickness of, for example, 30 nm (nanometers). To provide a planar firstmajor surface 10 a for themetallisation 15, theopening 17 is filled with afiller material 23 formed of an appropriate insulating material such as TEOS (Tetraethylorthosilicate). - Typically, the
first region 11 will have a thickness of from 3 to 30 μm and, when viewed in plan looking down on the firstmajor surface 10 a, theopening 17 will be in the form of a continuous trench having a regular grid or mesh-likestructure bounding areas 11 a which are square, hexagonal or circular and arranged in a regular matrix or array so that theresistive paths 21 form a continuous grid-like region. As another possibility, a stripe-like geometry may be adopted. Typically, there will be many thousands ofareas 11 a in a device. In an embodiment, theareas 11 a bounded by the grid-like opening 17 may be square when viewed looking down on the firstmajor surface 10 a and may be arranged in a square matrix so that the width D of eacharea 11 a is the same as the width W of theopening 17 and is, for example, 2 or 4 micrometers. The product of the dopant concentration [n−] and width D of theareas 11 a of the n−region 11, that is D*[n−], should be about 2×1012 cm−2 atoms as set out in U.S. Pat. No. 4,754,310. - FIG. 2 shows another example of a
semiconductor diode 1 a in accordance with present invention. Thesemiconductor diode 1 a shown in FIG. 2 differs from that shown in FIG. 1 in that thesecond region 12 is not a semiconductor region but is a Schottkymetal region 120 which forms a Schottkyjunction 130 with the first region. The Schottkymetal region 120 also forms at least part of theelectrode 15. Theregion 120 may be formed of, for example, a silicide such as platinum silicide. - FIG. 3 shows part of the
diode 1 or 1 a on an enlarged scale to illustrate the effect of providing the field shaping regions or resistive paths. For the sake of this illustration, thefirst region 11 is shown unhatched. When the rectifyingjunction resistive paths 21 causing a linear electrical potential drop along theresistive paths 21 so that the vertical electrical field near the interface between theinsulating layer 22 and thefirst region 11 is substantially constant. FIG. 3 illustrates the change in the extent of the depletion region DR with increasing reverse biasing voltage across the rectifyingjunction 13 with the solid lines d1 to d3 illustrating the extent of the depletion region DR and the dash lines e1 to e3 illustrating what the extent of the depletion region would have been in the absence of theresistive paths 21. As shown by the line d1, at relatively low reverse biasing voltages, theresistive paths 21 cause the depletion region DR to extend towards thethird region 14. As the reverse biasing voltage is increased and thus the electrical potential difference along theresistive paths 21 increases, the portions of the depletion region adjacent to theresistive paths 21 expand until, as shown by the line d3, the depletion regions merge so that thefirst region 11 is substantially entirely depleted of free charge carriers. If the pitch between adjacentresistive paths 21 is sufficiently small (typically 2 to 4 micrometers for a dopant concentration in the first region of 1016 atoms cm−3), the electrical field will be constant nearly everywhere before the critical field for avalanche breakdown is reached in thefirst region 11 so allowing the same reverse breakdown voltage characteristics to be achieved with a dopant concentration in thefirst region 11 that is much higher than would be possible without thefield shaping regions 20. A pn-n diode having a reverse breakdown voltage of 400V (a 400V pn-n diode) can be achieved using a 2 μm pitch (W=D=2 μm) and a dopant concentration in thefirst region 11 of 1016 cm −3. In contrast, to achieve a 400V pn-n diode with a conventional structure (that is without the field shaping regions 20) would require a dopant concentration in the n− or first region of 7×1014 cm−3 resulting in a much higher resistivity in the on state. - FIG. 4 shows a graph of on-resistance (Ron) in milli Ohms per millimeter squared against reverse breakdown voltage (Vbv) in volts. In FIG. 4 the line A shows the theoretical silicon1D limit while lines B and C show the limits that can be achieved by a silicon diode in accordance with the present invention with a pitch (W or D in FIG. 1) of 4 micrometers and, in the case of line B, a
first region 11 thickness of 30 micrometers and, in the case of line C, a first region thickness of 5 micrometers. At least for certain combinations of first region thickness and required reverse breakdown voltage, the present invention enables an improved trade off between on resistance and breakdown voltage to be achieved which is similar to that which can be achieved using the invention disclosed U.S. Pat. No. 4,754,310 without needing the balancing of the dopant concentrations required by U.S. Pat. No. 4,754,310. - FIGS.5 to 7 illustrate cross-sectional views of part of a semiconductor body to illustrate steps in one method of manufacturing a semiconductor diode 1 as shown in FIG. 1 or
semiconductor diode 1 a as shown in FIG. 2. Initially asemiconductor body 10 is provided consisting of a n+ conductivity type substrate for forming thethird region 14. An n-conductivitytype epitaxial layer 110 is grown on thesubstrate 14 for forming thefirst region 11. A masking layer 30 (for example a silicon dioxide or silicon nitride layer or a resist layer) is provided on the surface of theepitaxial layer 110 and patterned using conventional photolithographic techniques to definewindows 31 in themasking layer 30. An anisotropic etching process is then carried out as is known in the art to define theopening 17 extending through theepitaxial layer 110 into thesubstrate 14 to produce the structure shown in FIG. 5. - The
masking layer 30 is then removed using conventional masking layer removal techniques and, after cleaning of the exposed surface, athermal oxide layer 220 is grown on the exposed silicon surface as shown in FIG. 6. Thethermal oxide layer 220 is then subjected to an anisotropic etching process to leave the oxide only on theside walls 17 a of theopening 17 so as to form the insulating layers 22. Alayer 210 of semi-insulating or resistive material, in this case oxygen doped polycrystalline silicon or semi-insulating silicon nitride, is then deposited using known chemical vapour deposition techniques. A filler material such as, for example, TEOS is then deposited over thesemi-insulating layer 210 to form alayer 230 having a relatively planar exposed surface. Thelayers layer 230 at the same rate as the material of thelayer 210 to produce the structure shown in FIG. 2 but without the metallisation layers 120 and 16. Where the pn-n diode 1 is being manufactured, the conductivity type impurities are then introduced through the firstmajor surface 10 a to form thesecond region 12. As another possibility the implantation may be carried out before etching theopening 17. Metallisation is then deposited in known manner to form theelectrodes layers surface 10 a, theSchottky metal 120 is deposited on thesurface 10 a and theelectrode metallisation 16 is provided on thesurface 10 b as shown in FIG. 2. - In the embodiments described above, the
resistive paths 21 are separated from thefirst region 11 by the insulating layers 22. The thickness of the insulatinglayer 22 is determining by the required ruggedness and speed of the device and therefore depends upon the magnitude of the electric field within the device during switching transients. As set out above, typically the insulatinglayer 22 may have a thickness of 30 nm. The insulatinglayer 22 serves to achieve a linear potential drop or difference along theresistive paths 21 because it inhibits or at least reduces the possibility of conduction between theresistive paths 21 and thefirst region 11. However, theresistive paths 21 will still serve to increase the spread of the depletion region towards thethird region 14 even in the absence of the insulatinglayers 21 and, although the electrical potential along the resistive paths will be less linear without the insulatinglayers 22, the effects of the present invention may be achieved without the insulating layers, especially in the case where the semi-insulating material is oxygen doped polycrystalline silicon (SIPOS). - The
filler material 23 is provided to enable a substantially planar surface to be provided onto which thesubsequent metallisation 15 can be deposited. Where such a planar surface is not essential, then it may be possible to omit the filler material. Also, thediode 1 or 1 a could be designed so that the relative dimensions of theopenings 17 and the thicknesses of theresistive paths 21 are such that the material of theresistive paths 21 substantially fills theopening 17 so that there is no need for any filler material. Having awider opening 17 facilitates deposition of material into the opening whereas having anarrower opening 17 means that a filler material may not be necessary and it should be possible to achieve a lower on resistance because there will be a wider path through the n−first region 11. - It will, of course, be appreciated that the present invention may also be applied where the conductivity types given above are reversed and that semiconductor materials other than silicon may be used such as germanium or germanium silicon alloys.
- In the above described embodiments, the opening17 forms a continuous trench having a grid-like structure. However the situation may be reversed so that the
areas 11 a form a grid-like structure and a plurality ofdiscrete openings 17 are provided. - In the above described examples, the resistive paths are provided by a semi-insulating material such as oxygen doped polycrystalline silicon or silicon nitride. However other materials with similar resistance characteristics may be used.
- From reading the present disclosure, other variations and modifications will be apparent to persons skilled in the art. Such variations and modifications may involve equivalent and other features which are already known in the design, manufacture and use of semiconductor devices, and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any novel combination of features disclosed herein either explicity or implicitly or any generalisation thereof, whether or not it relates the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to any such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.
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GB0003184.9 | 2000-02-12 | ||
GBGB0003184.9A GB0003184D0 (en) | 2000-02-12 | 2000-02-12 | A semiconductor device and a method of fabricating material for a semiconductor device |
GB0003184 | 2000-02-12 |
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US6436779B2 US6436779B2 (en) | 2002-08-20 |
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EP (1) | EP1192663A2 (en) |
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JP2019091822A (en) * | 2017-11-15 | 2019-06-13 | 株式会社東芝 | Semiconductor device |
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GB2089119A (en) | 1980-12-10 | 1982-06-16 | Philips Electronic Associated | High voltage semiconductor devices |
GB2151844A (en) * | 1983-12-20 | 1985-07-24 | Philips Electronic Associated | Semiconductor devices |
US4611384A (en) * | 1985-04-30 | 1986-09-16 | Gte Laboratories Incorporated | Method of making junction field effect transistor of static induction type |
US4974050A (en) * | 1989-05-30 | 1990-11-27 | Motorola Inc. | High voltage semiconductor device and method |
US6184555B1 (en) * | 1996-02-05 | 2001-02-06 | Siemens Aktiengesellschaft | Field effect-controlled semiconductor component |
US6303969B1 (en) * | 1998-05-01 | 2001-10-16 | Allen Tan | Schottky diode with dielectric trench |
DE19820956A1 (en) * | 1998-05-11 | 1999-11-18 | Daimler Chrysler Ag | Insulated gate bipolar transistor with lateral component for retaining electric field strength |
DE19848828C2 (en) * | 1998-10-22 | 2001-09-13 | Infineon Technologies Ag | Semiconductor device with low forward voltage and high blocking capability |
-
2000
- 2000-02-12 GB GBGB0003184.9A patent/GB0003184D0/en not_active Ceased
-
2001
- 2001-01-26 WO PCT/EP2001/000830 patent/WO2001059844A2/en active Application Filing
- 2001-01-26 JP JP2001559067A patent/JP2003523086A/en not_active Withdrawn
- 2001-01-26 EP EP01915163A patent/EP1192663A2/en not_active Withdrawn
- 2001-02-12 US US09/781,498 patent/US6436779B2/en not_active Expired - Lifetime
Cited By (6)
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US6777780B2 (en) | 2001-08-07 | 2004-08-17 | Koninklijke Philips Electronics N.V. | Trench bipolar transistor |
CN103383968A (en) * | 2012-05-06 | 2013-11-06 | 朱江 | Interface charge compensation Schottky semiconductor device and manufacturing method for same |
CN103594493A (en) * | 2012-08-15 | 2014-02-19 | 朱江 | Trench-structure charge compensation Schottky semiconductor device and preparation method thereof |
CN103594494A (en) * | 2012-08-16 | 2014-02-19 | 朱江 | Charge-compensation schottky semiconductor device and manufacturing method thereof |
CN105529369A (en) * | 2016-03-08 | 2016-04-27 | 中国电子科技集团公司第二十四研究所 | Semiconductor cell structure and power semiconductor device |
CN110828561A (en) * | 2018-08-08 | 2020-02-21 | 英飞凌科技奥地利有限公司 | Si layer for oxygen insertion to reduce contact implant out-diffusion in vertical power devices |
Also Published As
Publication number | Publication date |
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WO2001059844A2 (en) | 2001-08-16 |
WO2001059844A3 (en) | 2002-01-10 |
GB0003184D0 (en) | 2000-04-05 |
US6436779B2 (en) | 2002-08-20 |
JP2003523086A (en) | 2003-07-29 |
EP1192663A2 (en) | 2002-04-03 |
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