Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/14—Handling requests for interconnection or transfer
  • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
  • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
  • G06F13/374—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a self-select method with individual priority code comparator
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
  • H04L12/40—Bus networks
  • H04L12/407—Bus networks with decentralised control
  • H04L12/413—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]

Definitions

• This invention relates to a data communication network and method of communication therein, and has particular application to a local area network which provides communication between a plurality of data processing stations located within a moderately—sized, geographical area, e.g. a multi-story office building.
• a passive communication medium suc ⁇ i as a coaxial, twisted pair or fibre optic cable provides a common serial data channel to inter ⁇ connect the data stations.
• Each data station may, for example, comprise a micro- or minicomputer, a memory disc system, a printer, an intelligent or non-intelligent video display unit or an interface to a public communi ⁇ cations network.
• a transmitting station transmits frames or packets of data of predetermined format in accordance with a standarized protocol over the data channel. The station for which the transmission is intended recognizes the address in a data frame and receives the data.
• a network architecture including higher levels of control software is provided for ef- ficient control of the network.
• the Ethernet system has certain disadvantages since in busy periods to avoid blocking of the channel it is necessary, after a certain number of attempts at retransmission, to reschedule the transmission at a higher level of control in the network architecture.
• a further disadvantage is the requirement for reformatting the data package whenever retransmission is attempted.
• the channel is jammed for a relatively long period whenever a collision occurs.
• a method of communication in a data communication network on a common data channel between data stations wherein each of the data stations wishing to transmit data monitors the data channel to ascertain whether other data transmissions are currently taking place on the channel, characterized in that, in order to contend for use of the channel, each data station, having ascertained that data transmissions on the channel have ceased, initiates transmission of transmission request signals during a sequence of con ⁇ secutive time periods in each of which the data station either transmits or does not transmit a transmission request signal on the channel according to a predeter ⁇ mined code assigned j_.o that data station, the data station monitoring the channel during said sequence and aborting contention for use of the channel if it finds that another data station is transmitting a transmission request signal while the first mentioned data station is not transmitting such a signal.
• a data communication network comprising a plurality of data stations, and a common data channel connecting said data stations, each said data station having a transmitter and a receiver, character- ized in that each said data station includes channel contention means for initiating transmission request signals in a sequence of consecutive time periods in each of which the data station either transmits or does not transmit a transmission request signal according to a predetermined code assigned to that data station, and further includes contention resolving means for determining during said sequence whether any other data station is transmitting a transmission request signal while the first mentioned data station is not transmit ⁇ ting such a signal, said contention resolving means including means for aborting the contention upon such determination.
• a method and means of resolving data channel contention are provided which can resolve contention in a shorter time than known arrangements employing random time intervals, thereby avoiding the requirement for network control at a higher level in busy periods.
• all data stations contending for channel use initiate transmission requests, and are thereby synchronized in operation. This permits the resolution of contention by each data station monitoring the chan ⁇ nel for transmission request signals while the data station -is not transmitting such a signal.
• each station is assigned a predeter- mined code for transmitting a sequence of requests in said time periods which can ensure that each data station has a air opportunity to gain channel control thereby alleviating the problem associated with priority systems of certain stations being unable to gain control of the signal path.
• each data station is assigned a unique cyclic code, and during a series of channel contentions, each station starts a succeeding channel contention sequence at a position in the cyclic code determined by the position at which channel contention previously ceased. This can ensure that two contending stations have statistically an equal chance of gaining channel control.
• O PI ⁇ In less busy periods when the data channel may be unusued, means are provided responsive to long periods with no transmission on the channel for initiating a contention cycle immediately after a request for trans- mission is made within the data station, and synchroni ⁇ zation with other data stations is unnecessary.
• Each station is preferably equipped with a directional coupler between the transmitter and receiver and data channel.
• the contention resolving means of each data station may detect the condition of only itself transmitting a request signal in a said time period, in which condition the data station is imme ⁇ diately permitted use of the channel. If, however, the station detects a transmission request signal in a time period when the station is not transmitting a request signal, then the station immediately aborts contention. This provides very fast transmissions over the data channel. It should be understood that the channel may be used for transmission to a plurality of stations at the same time-
• the channel contention se ⁇ quence may be carried out for a predetermined time, say one cycle of the cyclic code, and the data station may detect whether any transmissions are detected during any time period when the data station is not transmitting a transmission request signal. If no transmissions are detected, then channel use is permitted at the end of the predetermined time.
• said transmission request signal comprises a burst of pulses followed by a time interval at least as long as the echo time of the data channel, i.e.
• Fig. 1 is a block diagram of a data station of a data communication network made according to this invention and coupled to a coaxial cable, forming a common data channel of the network;
• Fig. 2 is a more detailed block diagram of the receiver, transmitter and directional coupler of the data station shown in Fig. 1;
• Figs. 3A, 3B, 3C, and 3D are waveform diagrams;
• Fig. 4 is a more detailed block diagram of the station of Fig. 1;
• Figs. 5A, 5B, 5C, 5D, 5E, and 5F taken together as shown in Fig. 5G constitute a circuit diagram of a contention controller included in the data station of Fig. 1;
• Figs 6A and 6B are a schematic representation and truth table respectively of a J-K flip-flop used in the circuit of Figs. 5A - 5F; Figs. 7A and 7B taken together are a flow chart describing the operation of a reception control unit of a contention controller of Figs. 5A - 5F; and Fig. 8 is a flow chart describing the oper ⁇ ation of a slot generator of the contention controller of Figs. 5A - 5F.
• a data station 1 of a communication network com ⁇ prising a local area network is coupled to a data channel 2 formed by a suitably terminated coaxial cable having for this example a maximum length of 3.4 Km, the channel 2 serving as a common serial data channel connecting the data station 1 to eight other similar data stations in the present embodiment, although there could be up to a maximum of about three hundred and forty stations, for example.
• the data station 1 includes a controller 3 for receiving and formatting information to be transmitted over the network in the standard frames or packets of data.
• the controller 3 may be a programmed commercially available microcomputer.
• a chan ⁇ nel contention controller 4 is provided.
• the controller 4 is connected to a receiver 5 and to a transmitter 6, which are coupled to the data channel 2 by a directional coupler 7 and an electrical connector 8.
• the coupler 7 normally prevents transmissions by the transmitter 6 from being detected by the receiver 5.
• each data station of the local area network carries out a channel contention sequence prior to data transmission by transmitting transmission request signals in a se ⁇ quence of consecutive time periods each having a length corresponding to 64 timing pulses, wherein in each time period the data station either transmits or remains silent (i.e. does not transmit) according to a predeter- mined code assigned to that data station.
• a channel contention sequence prior to data transmission by transmitting transmission request signals in a se ⁇ quence of consecutive time periods each having a length corresponding to 64 timing pulses, wherein in each time period the data station either transmits or remains silent (i.e. does not transmit) according to a predeter- mined code assigned to that data station.
• OMPI transmission request signal occurring in a single time slot is shown in Fig. 3D, this comprising an initial silent period a. having a duration of eight timing pulses to ensure that the channel is settled or to allow for synchronization errors, followed by a pulse burst b of sixteen timing pulses and a period of silence c_ of forty timing pulses which is greater than twice the longest delay in the network (30 pulses).
• the entire time period or slot is of a duration of 64 timing pulses, these pulses being provided by a data timing generator 62 (Fig. 2) included in the transmitter 6.
• a data sta ⁇ tion can distinguish between regular data and a trans ⁇ mission request signal since regular data has a minimum bit length of 32 bits.
• a data station like 1 is prevented from trans ⁇ mitting.
• Each station wishing to transmit detects the end of transmission and initiates, in synchronism with the other stations wish ⁇ ing to transmit, a sequence of consecutive time periods in each of which each station either transmits or remains silent.
• each such station will detect the transmission of the other during the same time period and will be unable to obtain use of the data channel. It will be appreciated that because " of propagational delays, there will be a time differential between the initiation of the trans ⁇ mission request signals at the data stations and also a delay in the receipt of a request signal by another
• the time period is sufficiently long to accommodate these differentials.
• the transmitting station will detect the absence of other transmission request signals on the data channel and will thereupon gain use of the channel.
• the shortest data frame is longer than a single signal burst of a transmission request. If several stations are in contention for the data channel 2, there may appear at each station multiple overlapping transmission request signals due to propagation delays, and as a result there could be a risk that a valid data frame may be simulated by such multiple signals. How ⁇ ever, such a simulated data frame is not received in the controller 3. Thus, contention can be resolved only when finally a single transmission request signal appears. At this stage there is no longer any danger of data frame simulation and the station is set to the reception expected state. With the station in the reception expected state, when the length of a received transmis- sion is detected to be about the length of a data frame, the station will change its reception expected state into a transfer state.
• Each station is assigned a unique cyclic code for the contention sequence, according to the following table.
• each station transmits a sequence of transmission request signals in a series of 8 consecutive time periods or slots, the left hand bit designating the first slot and the right hand bit desig ⁇ nating the last slot.
• each time period or slot corresponds to 64 timing pulses.
• a bit "1" indicates the issuance of a transmission request signal and a bit "0" indicates the absence of a trans ⁇ mission request, signal.
• the first opportunity to transmit occurs during the fourth slot (marked slot number 3), and further opportunities occur during the sixth, sev ⁇ enth and eighth slots. If, for example, stations 1 and 2 wish to transmit immediately following a data trans ⁇ mission, then these two stations initiate their first slot.
• station 1 If station 1 still desires to transmit over the network at the end of the data transmission by station 2, then it will initiate a further contention cycle, but starting at slot six of the code, which is the slot immediately following the slot at which the previous contention was aborted. Because station 1 is arranged to transmit transmission request signals in slots six, seven and eight, station 1 will now have a greater chance of gaining use of the channel.
• no assigned code has more than three consecutive inactive slots.
• means are provided so that once a data station has detected a period of inactivity on the data channel corresponding to four consecutive slots, it knows that no other station is seeking use of the channel 2 and so it can immediately begin a request cycle.
• the directional couplers 7 in the remote stations would not be able to discriminate a received transmission request signal (having a very low signal strength) from a transmitted transmission request signal leaking to the receiver 5 from the transmitter 7 of the same station.
• Such stations cannot therefore participate in the contention scheme described above since they are unable to detect silence in a time slot when they are the only stations to issue a transmission request signal.
• Such stations are pro- vided with a cyclic code similar to those in Table 1 for issuing transmission requests when transmission is desired.
• a station transmits transmission request signals for about one cycle of the code, and the arrangement is such that the station gains use of the data channel only if no transmission request signal from another station is detected during any of the silent periods of the cycle.
• the station automatically reverts to the second mode of resolving contention when it is too remote from the other stations to discriminate received signals from transmitted signals.
• Table 2 shows the relation between the number of slots in a cycle of a cyclic code and the number of unique cyclic codes, that is to say the number of sta ⁇ tions having an equal chance of gaining use of the data channel.
• the transmitter 6 (Fig. 2) transfers data into the data channel 2 under control of a master timer signal MT, a data to be transmitted signal DT, and a transmitter control signal TC.
• the master timer signal MT (Fig. 3A) appears on a line 61 and is derived from the data timing generator 62 which includes a crystal clock of 1 MHz.
• the signal MT is used as a clock signal in the data frames to be transmitted and for control of the contention controller 4.
• the signal MT defines the base band frequency of the data channel 2.
• the signal MT is transmitted to a data and timing encoder 63 which combines the signal MT with the data to be transmitted signal DT (Fig. 3B) which appears on a line 64.
• the combining takes place under control of the transmitter control signal TC which appears on a line 65 to provide a phase encoded data signal DS (Fig. 3C) for transmission on a line 66.
• the signals are combined to provide the phase encoded data signal DS which has a positive trans ⁇ ition for a binary one data signal and a negative trans ⁇ ition for a binary zero data signal.
• a level conversion unit 67 is provided for leveling the signals DS to adequate voltages to control the directional coupler 7.
• a transmission enabling unit 68 inhibits the directional coupler 7 when the signal TC is off.
• the directional coupler 7 (Fig. 2) comprises a bridge arrangement with the data channel 2 forming one arm of the bridge and a balancing resistor 71 forming an adjacent arm of the bridge, the connection between the adjacent arms being grounded.
• OMPI bridge are formed by the emitter-collector paths of a monolithic transistor array 72, the transistor bases being controlled by the transmission enabling unit 68 via lines 73.
• the transistor array 72 comprises first and second PNP transistors 721 and 722 having their bases connected together and their emitters connected to a source of positive potential, and third and fourth NPN transistors 723 and 724 having their bases connected together and their emitters connected to a source of negative potential.
• the first and third transistors 721 and 723 form a complementary pair constituting one arm of the bridge and the second and fourth transistors 722 and 724 form another complementary pair constituting another arm of the bridge.
• the transistors are switch- able between one state in which transistors 721 and 722 are switched off and transistors 723 and 724 are switched on in the active state with a high emitter-collector impendance, and another state in which transistors 723 and 724 are switched off and transistors 721 and 722 are switched on in the active state with the same emitter- collector impedance as the impedance of transistors 723 and 724 in the active state.
• An operational amplifier 74 is connected by way of resistors 75 across a diagonal of the bridge. In operation, for transmission, signals are transmitted to the data channel 2 by switching the transistor array 72 to provide a signal voltage across the channel and ground.
• the transmitter signals appearing at the inputs to the amplifier 74 are of equal magnitude, and there is no signal detected by the receiver 5. For reception of signals transmitted by other stations which appear across the channel between ground and the positive input to the amplifier 74, these signals are amplified and fed to the receiver 5.
• the receiver 5 With the construction of the directional coupler 7 (Fig. 2) described above, it is possible for the receiver 5 to detect signals 28 dB. smaller than signals transmitted at the same time by the transmitter 6.
• the receiver 5 comprises a filter 51 for eliminating out-of-band noise for both high and low frequencies.
• a compromise-frequency equalizer is provided to compensate for the linear amplitude distortion of the cable and to minimize inter-symbol interference, that is to say interference due to oscillations preceding and following the leading and trailing edges respectively of a pulse.
• a zero-crossing detector 52 provides a received carrier signal RC on a line 53 which is high when zero crossings are detected above a predetermined threshold, which threshold is defined to ensure the receipt of signals from remote stations when attenuation may be appreciable but to avoid detection of erroneous zero crossings owing to noise and interference. Only when regular zero crossings are detected does the received carrier signal RC go high.
• a zero crossing time recovery unit 54 discriminates insignificant transitions ( f_ Fig. 3C) from significant transitions (i.e. transitions indicating binary data levels). This is effected by a timer which is started at a detected transition and has a timing interval greater than half a data cycle such that a following insignificant transition will not activate the timer and hence will not be detected.
• the unit 54 also provides on a line 55 a timing reference signal TR for the received signal.
• a received data latch circuit 56 buffers in a latch detected significant transitions to provide a received data signal RD on a line 57, representing the data received by the receiver.
• the contention controller 4 (Fig. 4) is com ⁇ prised of three main parts; a reception control unit 410 for distinguishing received data frames from received transmission request signals; a slot generator 412 for generating transmission request signals; and a trans ⁇ mission control unit 414 for enabling data transmission.
• the reception control unit 410 (Fig. 4) serves to distinguish a data signal from multiple overlapping transmission request signals.
• the unit 410 provides a reception expected signal RE on a line 416 to an AND gate 418 to enable the gate 418 to transmit a received data timing signal RT to the controller 3 on a line 420, thereby enabling the controller 3 to receive the received data signal RD on the line 57.
• the controller 3 (Fig. 4) provides a request signal RQ on a line 422 to the trans ⁇ mission control unit 414.
• a direct access signal DA on a line 424 overrides the action of the contention con ⁇ troller 4 to provide immediate access to the data channel 2 for the data station. This may be necessary where, for example, the station is a host computer which con ⁇ trols all other stations at a higher level or where full duplex communications occur between two stations as will be described later.
• a transmitted data signal TD (Fig. 4) on a line 426 is applied to one input of an OR gate 428, and a ready signal RY from the transmission control unit 414 enabling readiness for transmission is applied to a second, inverting input of the gate 428.
• a burst period signal BP (Fig. 4) for a trans- mission request signal is provided on a line 430 to an OR gate 432 together with the ready signal RY on a line 434.
• the signals BP or RY provide the transmitter control signal TC on the line 65.
• the ready signal RY on the line 434 is also applied to an AND gate 436 together with the master timing signal MT to provide a transmitter timing signal TT on a line 438 to the con ⁇ troller 3 for formatting data packets.
• a transfer state signal TS (Fig. 4) is pro ⁇ vided on a line 440 from the reception control unit 410 to the slot generator 412 and to the transmission control unit 414 to inhibit operation of the slot generator 412 when data is transferred from the receiver 5 and to
• OMPI assist in the operation of the transmission control unit 414.
• a soliciting period signal SP (Fig. 4) on a line 442 is generated by the transmission control unit 414 to initiate a contention sequence in the generator 412.
• a next slot timing signal NS (Fig. 4) on a line 444 and an active slot control signal AS on a line 446 are generated by the generator 412 for control of transmission requests.
• the circuit diagram of the contention con ⁇ troller 4 is shown in more detail in Figs. 5A, 5B, 5C, 5D, 5E, and 5F and a basic unit of the circuit, a J-K flip-flop, is shown in Fig. 6A, with a truth table for the flip-flop being shown in Fig. 6B.
• the flip-flop is chosen so that the circuit may easily be implemented in large scale integration.
• the terminals of the flip-flop are J and K input terminals, a Q output ter- minal, a clock terminal, and preset and clear terminals.
• the flip-flop is clocked by a downward edge transition.
• the Q output of the flip-flop shown in Fig. 6A is set high when a high signal is applied to the J input ter ⁇ minal and is set low when a low signal is applied to the J input terminal.
• the Q output remains the same, and when high signals are applied to both the J and K input terminals the output is toggled.
• any terminals shown unconnected are held high, unless they are marked "L" in which case they are held low.
• 5A and 5D includes a 0-31 counter comprising five flip- flops 450, 452, 454, 456, 458, which counter is enabled via an OR gate 468 whenever the RC signal is present on the line 53, the output of the OR gate being coupled to
• a flip-flop 462 is controlled by the counter 450-458 and serves to enable the counter via the OR gate 468.
• a flip-flop 464 is also controlled by the counter 450-458 to provide the reception expected signal RE on the line 416 when data transmissions are anticipated.
• the purpose of the reception control unit 410 is to distinguish a block of multiple overlapping trans ⁇ mission request signals from regular data. This is achieved by measuring the length of the received signals and by virtue of the fact that the received multiple transmission request signals are shorter at each suc ⁇ cessive slot in the contention procedure, ending in the receipt of a single transmission request signal, after which regular data can be expected and detected.
• Regu ⁇ lar data has a minimum length of 32 bits, while the pulse burst of a single transmission request signal has a length of 16 bits. A signal of less than 8 bits is considered as noise and no action will be taken on such a signal.
• the reception expected signal RE is gener ⁇ ated after 32 clock pulses.
• FIGs. 5A and 5D are determined by the flip-flop 464 and the 0-31 counter 450-458.
• the output of the flip-flop 464 is low, filtering of noise and transmission request signals is performed.
• the output of the flip-flop 464 is high, the received data timing signal RT is transmitted to the controller 3.
• the output of the flip-flop 464 is high and the counter 450-458 reaches position 31 while the signal RC is high, the transfer state signal TS is generated.
• the 0-31 counter 450-458 (Fig. 5A £. 5D) is clocked by MT pulses on the line 61 via an OR gate 461.
• the first eight steps of the counter are enabled by the OR gate 468 whenever the RC signal appears on the line 53, the output of the OR gate 468 being coupled to the clear terminals of the flip-flops 450, 452, 454.
• the flip-flop 462 is clocked by the output of the flip-flop 454, and the J input of the flip-flop 462 is controlled by the inverted output of the flip-flop 458.
• the flip- flop 464 is clocked by the output of the flip-flop 462 for operation in the toggle mode.
• the Q outputs of the flip-flops 450-458 (Figs. 5A & 5D) together with the signal RC are connected as inputs to an AND gate 460, the output of the AND gate 460 being coupled to the inputs of the OR gate 461 and an AND gate 479.
• the Q outputs of the flip-flops 458, 456, and the signal RC are connected to the inputs of a NAND gate 466, the output of which serves to clear the flip-flop 462.
• the Q outputs of the flip-flops 458, 462 and the signal RC are coupled to the inputs of the OR gate 468, the output of which serves to enable the flip- flops 450-454.
• the direct access signal DA on the line 424 is coupled via an inverter 472 to the preset ter ⁇ minal of the flip-flop 464 and is coupled via an OR gate 476 to the clear terminal of the flip-flop 464.
• a silence signal S on a line 478 is coupled to an invert ⁇ ing input of the OR gate 476.
• the counting of the unit 410 begins as soon as transmissions are received by the receiver 5 when the signal RC goes high. This forces the output of the OR gate 468 high, to enable an initial counting operation by the flip-flops 450, 452, 454 which are clocked by MT pulses via the gate 461 up to a count of 8.
• the flip-flops 450, 452, 454 which are clocked by MT pulses via the gate 461 up to a count of 8.
• OMP which describe the operation of the reception control unit 410
• @and ( ) indicate connectors in the flow chart and a number in parentheses like (802) in the specification indicates a step or location.
• the con- tinuous operation of the circuit 410 is considered first at (802) which indicates the count C of the counter 450- 458. If C ⁇ 7 and the signal RC is high (804) then the receipt of a MT clock pulse (806) increments the counter (808). If, however, the signal RC goes low (804), then the counter is cleared (810).
• the purpose of the initial count is to test receipt of a transmis.sion request signal. If the count is less than 8 and the signal RC goes low, this indi ⁇ cates transients on the line. If, however, the signal RC is high for the count of 0-8 this probably indicates the detection of a transmission request signal (see Fig. 3D).
• the counting continues (822) while C ⁇ 24 (820) as shown in Fig. 7A.
• C ⁇ 24 820
• the signal RC is low (826) this indicates that a single transmission request signal, or a short multiple request signal, has been received which is unable to simulate regular data.
• the counter is incremented (828) up to C ⁇ 31 (824). If, however, the signal RC is high, this may indicate mul ⁇ tiple transmission request signals and the NAND gate 466 is enabled to reset the flip-flop 462 (830).
• the flip-flop 462 is reset (844), and the signal RE is not generated.
• the next MT clock pulse (848) resets the counter 450-458 (842). Assuming the signal RE has been generated, when the signal RC again goes high this probably indi ⁇ cates the reception of a data frame.
• the output of the flip—flop 464 Since the output of the flip—flop 464 is high, the output of the AND gate 479 goes high to provide a trans ⁇ fer state signal TS (850) on the line 440 (Figs. 4 and 5A) .
• the signal TS inhibits operation of the transmitter until the signal RC goes low (852), when the entire data frame is received.
• the flip-flop 464 is reset (856) to terminate the signal RE, and the counter 450-458 is reset (842).
• the received data frame is received in the controller 3 and is subject to the various procedures of the protocol such as address recognition, cyclic redun ⁇ dancy check, etc. In some circumstances the operation of the reception control unit 410 can be overriden. If the signal DA (Fig. 5C) goes high on the line 424 then the
• OMP flip-flop 464 (Fig. 5D) is immediately set via the OR gate 476 to provide the reception expected signal RE.
• the silence signal S on the line 478 is employed to reset the flip-flop 464 should the flip-flop previously have been set by the signal DA or should the flip-flop 464 have been set by a contention action, but no data transfer occurred.
• the signal DA may be employed where full duplex operation is required. Thus a station can transmit a data frame to another station while the other data station transmits a data frame to the first station.
• the provision of the bridge directional coupler 7 permits full duplex operation.
• contention controller 4 (Fig. 4)
• the slot generator 412 and the transmission control unit 414, the purposes of which are to carry out channel contention cycles and to enable data transmission, respectively.
• the slot generator 412 comprises a 0-63 slot timer or counter comprising six flip-flops 502-512 which are incremented by the master timer MT pulses provided on the line 61 from the transmitter 6.
• a NOR gate 514 coupled to the clear terminals of the flip-flops 502-512 clears the counter when the transfer state signal TS on the line 440 is high or the ready signal RY on the line 434 is high.
• the Q output of the flip-flop 506 is coupled to an inverting input of a NOR gate 516 (Fig.
• the Q outputs of the flip-flops 508, 510, 512 are coupled to non— nverting inputs of the gate 516 to provide a next slot signal NS on the line 444.
• the Q output of the flip-flop 510 is coupled to an input of an AND gate 518 and the Q output of the flip-flop 512 is coupled to an inverting input of the AND gate 518 to provide the burst period signal BP on the line 430.
• the output of the NOR gate 516 (Fig. 5D) provides a next slot signal NS on the line 444 to an input of an AND gate 520 (Fig. 5E) for the purpose of clocking a slot sequence counter comprising flip-flops 522-526.
• the other input to the AND gate 520 is con ⁇ trolled by the soliciting period signal SP on the line 442.
• the next slot signal NS is also employed to clock a silence control counter comprising flip-flops 528-532, a soliciting period counter comprising flip-flops 534- 538, and a chain of flip-flops 540, 542, 544 (Fig. 5C) which provide transmission control signals.
• the slot sequence counter 522-526 serves to allot sequentially eight defined slots (such as are shown in Table 1) to a station like 1.
• the counter 522-526 controls a multiplexer comprising six inverters 550 (Fig. 5E), eight AND gates 552 (Fig. 5B), an OR gate 554 and a final AND gate 558.
• the multi ⁇ plexer serves as a translator between a set of input signals and one output signal.
• the AND gates 552 are each controlled by 3 binary coded signals representing a number from 0 to 7, this number being different for each gate, and by a respective input line 556 (Fig. 5B) which is connected to either a low or a high voltage represen- ting one element of the cyclic contention code.
• the eight input lines 556 are connected to low or high voltages as represented in Table 1 by "0"s and "l”s for a specific station number. There is always one number presented by the slot sequence counter to the set of eight AND gates 552 so that one of the AND gates 552 is enabled to transmit to the OR gate 554 the signal defined by its respective input line 556. Each gate 552 repre ⁇ sents a different number, the uppermost gate 552 as shown in Fig. 5B representing 0 and the lowermost gate 552 representing 7. Since the slot information is needed only during the soliciting period, the signal SP (Fig. 4) from the transmission control unit 414 enables the final AND gate 558 of the multiplexer to output the signal applied to it from the OR gate 554.
• An active slot is represented by an input line 556 connected to a high voltage and the output for an active slot is also a high voltage. The output of the gate 558 represents the
• OMPI active slot signal AS on the line 446 during the soli ⁇ citing period This signal is applied to an AND gate 560 together with the burst period signal BP on the line 430 to provide a transmission request signal on a line 562 to the OR gate 432.
• the transmission control unit 414 operates with the aid of two counters, the silence control counter comprising the flip-flops 528-532 (Fig. 5E) and the soliciting period counter comprising the flip-flops 534, 536 and 538.
• the function of the silence control counter 528-532 is to indicate at the end of each slot that silence on the data channel 2 was not interrupted during this slot and to indicate that during the last four slots silence on the data channel 2 was not interrupted.
• the silence control counter 528-532 is continuously active except during data transfer.
• the operation of the silence control counter 528-532 (Fig. 5E) is under the control of the trailing edge clock pulse NS on the line 444 (see also Fig. 4) which is connected to the output of the gate 516 (Fig. 5D) .
• the counter 528-532 (Fig. 5E) is adapted to be cleared whenever the received carrier RC signal from the receiver 5 appears on the line 53 connected via an inverter gate 564 to the clear terminal of " each of the flip-flops 528, 530, 532.
• the counter 528-532 can increment from 0 to 5 and is then blocked for further incrementing. In all positions the counter 528-532 can be cleared by the received carrier RC signal.
• the K input of the flip-flop 528 is controlled by the inverted Q output of the flip-flop 532 in order to block the counter 528-532 at its position 5.
• Position 0 of the counter 528-532 indicates that in the current slot period, silence is not maintained.
• Positions above 0 of the counter 528-532 indicate that in the current slot period, silence is not yet interrupted.
• Positions above 3 indicate that in the previous three slots and in the current slot, silence is not yet interrupted.
• Position 5 finally indicates that at least in the four previous slots and in the current slot, silence is not yet inter ⁇ rupted.
• the positions above 0, above 3 and position 5 are provided as outputs. Positions above 0 are indi- cated by an OR gate 566 (Fig.
• Position 5 of the counter 528-532 is detected by an AND gate 572 controlled by the Q outputs of the flip-flops 528 and 532, the AND gate 572 providing the silence signal SL on the line 478.
• the soliciting period counter 534-538 determines the maximum soliciting period within which a station must have gained the use of the data channel 2. Normally, a station will have gained use of the data channel 2 when all eight slots have been used sequentially. A station can detect that it is to abort channel contention by listening during a passive slot, and it can detect that use of the data channel 2 has been gained by listening during an active slot. How- ever, when a station is situated very remotely from other stations its receiver must be adapted to receive very weak signals. Under these circumstances it may happen that the station detects its own transmission request signals leaking through the directional coupler 7. In this situation the soliciting period counter 534- 538 indicates after eight slots that the station has gained the use of the data channel 2.
• the operation of the soliciting period counter 534-538 (Fig. 5E) is controlled by the trailing edge clock pulse NS on the line 444, and the counter 534-538 is adapted to be cleared whenever a soliciting period signal SP on the line 442 (see also Fig. 4) disappears, the line 442 being connected to the clear terminals of the flip-flops 534, 536, 538.
• the soliciting period counter 534-538 is enabled whenever the SP signal is high.
• the counter 534-538 is a 0-7 counter which indi- cates in position 7 that 7 slots are already used and that an eighth slot is in progress. Position 7 is detected by an AND gate 576 connected to the outputs of the flip-flops 534-538, the gate 576 providing a last slot signal LS on a line 578 connected to the output of the AND gate 576.
• the transmission control unit 414 (Figs. 4, 5B " , and 5C) contains an arrangement of gates coupled to the flip-flops 540-544 (Fig. 5C) and responsive to control signals from the remainder of the contention controller 4 and controller 3 for ensuring that the flip-flops 540-544 produce transmission control signals.
• the direct access signal DA (Fig. 5B) on the line 424 is applied via an inverter 580 to the preset terminal of the flip-flop 540 (Fig. 5C) and via an input of an OR gate 582 (Fig. 5B) to the clear terminal of the flip-flop 540.
• the request signal RQ on the line 422 is applied to an input of the OR gate 582, to an input of an AND gate 584 (Fig. 5B) which is connected to the J input of the flip-flop 544, and to an inverting input of an OR gate 586 (Fig. 5B) which controls the K input of - ⁇ the flip-flop 544.
• the silent slot signal SS (Fig. 5E) on the line 568 is applied to an input of a contention arbi ⁇ tration EXCLUSIVE NOR gate 588 (Fig. 5B) and to an input of an AND gate 590.
• the active slot signal AS on the line 446 is also applied to an input of the AND gate 590 and the XNOR gate 588.
• the output of the XNOR gate 588 is connected via the OR gate 586 to the K input of the flip-flop 544 (Fig. 5C)
• the output of the AND gate 590 is connected via an OR gate 592 to the J input of the flip-flop 540.
• the last slot signal LS (Fig. 5E) on the line 578 is applied to an input of the OR gates 586 and 592 (Fig.
• the RC signal on the line 53 (Fig. 5D) is applied to the OR gate 586 (Fig. 5B) .
• the TS signal on the line 440 (Fig. 5A) is applied via an inverter gate 594 (Fig. 5B) to the preset terminal of the flip-flop 542 (Fig. 5C), and the Q output of the flip-flop 542 is applied to its K input and to an input of an OR gate 596 (Fig. 5B) .
• the silence expected signal SE (Fig. 5E) on the line 570 is also applied to the OR gate 596 (Fig. 5B) , and the output of the OR gate 596 is applied to an input of the AND gate 584.
• the request signal RQ (Fig. 5B) going high: a) while the data channel is already occupied with data transmission, or b) where the data channel is unoccupied.
• the signal TS (Fig. 5A) will be high, disabling the slot timer 502-512 (Fig. 5A) and setting the flip-flop 542 (Fig. 5C) high.
• the output of the AND gate 584 (Fig. 5B) will go high, providing a high input to the J input of the flip-flop 544 (Fig. 5C). In this state, no transmission by the station is possible.
• the signal RC on the line 53 goes low, forcing the signal TS low so that the slot timer 502-512 (Fig. 5A) is enabled to initiate a contention operation for use of the channel.
• FIG. 8 which describes the oper ⁇ ation of the slot timer
• (B) indicates a connector in the flowchart, and a number in a parenthesis in the specification indicates an operation, step, or situation.
• the slot timer 502-512 is cleared (906) when the ready signal RY on the line 434 is high (902) or the transfer state signal TS on the line 440 is high (904).
• the slot timer 502-512 reaches position 63 (908) it will at
• next MT clock pulse progress to its zero position (928) .
• slot timer 502-512 is in a position less than 63 (908) a next MT clock pulse (910) will increment the slot timer (912).
• the NOR gate 516 (Fig. 5D), which is controlled by the flip-flops 506, 508, 510, 512 causes next slot signal NS to go high (916) at the slot timer position 4 (914), but provides a trailing edge next slot pulse NS at the slot timer position 8 (918) .
• the slot timer 502-512 counts 8 clock pulses before the next slot pulse NS is produced so as to ensure that the data channel is silent for a period of 8 pulses before production of the NS pulse.
• the AND gate 518 (Fig. 5D), which is controlled by the flip- flops 510 and 512 is enabled to produce burst period signal BP (924) during the slot timer positions 16-31 (922).
• Enabling of the gate 520 permits the slot sequence counter 522-526 to increment.
• the output of the gate 558 will either go high providing signal AS (on line 446) representing an active conten ⁇ tion slot in which a transmission request signal is transmitted, or will go low if a silent slot occurs, i.e. a slot in which no transmission request signal is transmitted.
• the gate 560 (Fig. 5E) is enabled so that upon the slot timer 502-512 reaching position 16 the burst period signal BP (Fig. 5D) goes high and appears on the line 562, whereby the transmitter control signal TC appears on the line 65.
• the signal BP remains high until the slot timer 502-512 reaches position 32. During this period of sixteen timing pulses a pulse burst (Fig. 3D) of a transmission request signal appears on the data channel 2. For the remainder of the slot interval the signal BP is low. There is thus provided a transmission request signal of the form shown in Fig. 3D in a time period or slot.
• the station will generate a sequence of slots, in each of which a transmission request signal will either be transmitted or not transmitted, according to the cyclic code.
• the receiver 5 (Fig. 4) cannot detect a transmission request signal emitted by the transmitter 6, by virtue of the directional coupler 7.
• the signal RC goes high on the line 53 thereby resetting the silence control counter 528-532 (906) whereby the silent slot signal SS (Fig. 5E) on the line 568 goes low.
• the outputs of the XNOR gate 588 (Fig. 5B) and the AND gate 590 therefore go low.
• the signal RY disables via the gate 514 (Fig. 5A) further operation of the slot timer 502-512 and provides the signal TC (Fig. 5F) on the line 65 so that a data frame can be transmitted via the line 64 as the signal DT.
• the flip-flop 544 (Fig. 5C) is reset so that the signal SP goes low to abort the contention sequence.
• the signal AS (Fig. 5B) on the line 446 going low indicating a silent slot
• the silence control counter 528- 532 (Fig. 5E) is reset and the silent slot signal SS on the line 568 goes low.
• the presence of two low inputs to the XNOR gate 588 (Fig. 5B) causes the output to go high, thereby resetting the flip-flop 544 (Fig. 5C) and causing the signal SP to go low at the next clock pulse so as to terminate the contention operation in favor of the other competing data stations.
• the slot timer 502-512 (Figs. 5A & 5D) is reset by the signal RY (Fig. 5C) (902) (Fig. 8) or the signal TS (Fig. 5A) (904) (Fig. 8) and the soliciting counter
• Fig. 5E is reset when the signal SP (Fig. 5C) goes low.
• the slot sequence counter 522-526 (Fig. 5E) is not reset, and at the next contention sequence the sequence will begin at the next position of , the slot sequence counter 522-526, i.e. the next posi ⁇ tion in the cyclic code.
• the flip-flop 540 (Fig. 5C) may also be set to provide the signal RY in the case of the signal DA on the line 424 going high, thereby overriding the conten- tion sequence.
• data transmission may also be required for condition (b) where the data channel is unoccupied.
• the slot timer 502-512 and the silence control counter 528- 532 will be incremented by the next slot pulses NS appearing on the line 444 regardless of whether a con ⁇ tention operation occurs.
• the silence expected signal SE (Fig. 5E) on the line 570 will be set after four consecutive periods of silence and thereafter will remain set. Since as shown in Table 1 no station has more than three consecutive periods of silence in the cyclic contention codes, setting of the signal SE shows that no other data station is contending for channel control.
• the AND gate 584 (Fig. 5B) is enabled to set the flip-flop 544 (Fig. 5C) to provide the soli ⁇ citing period signal SP and initiate a channel contention sequence.
• the gate 572 (Fig. 5E) is enabled to provide the silence signal SL on the line 478.
• the signal SL is used to reset the flip-flop 464 (Fig. 5D) to terminate the reception expected signal RE. This may be necessary where the signal RE is set in anticipation of data transfer but no transfer occurs.
• the sensitivity of the recei ⁇ ver must be set in order to detect signals where the signal loss may be as high as 40 dB. Since the sensi ⁇ tivity of the directional coupler 7 is 28 dB., the receiver having a higher sensitivity will detect trans ⁇ missions from the transmitter 6 leaking through the directional coupler. Thus, in a contention sequence where the station 1 wishes to transmit, the signal RC will go high when the transmitter 6 makes a transmission request signal, thereby resetting the silence control counter 528-532, so that the signal SS (Fig. 5E) goes low.
• the soliciting period counter 534-538 in a contention sequence will provide the signal LS (Fig. 5E) on the line 578 after seven time slots in which the signal SP is active. In other words the signal LS will be provided after seven slots in which contention is not resolved in favor of other data stations.
• the signal LS is operative to reset the flip-flop 544 (Fig. 5C) , thereby terminating the SP signal, and to set flip-flop 540, thereby pro ⁇ viding the RY signal on the line 434 to enable data transmission.
• the signal LS may be provided at an earlier slot when it is certain that contention can always be resolved earlier. A same number of active slots used in all stations provides such a condition. In this case the output of flip-flop 534 need not be connected as an input to gate 576.

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• 1983
  • 1983-03-23 EP EP19830901510 patent/EP0105337A1/de not_active Withdrawn
  • 1983-03-23 WO PCT/US1983/000417 patent/WO1983003507A1/en not_active Application Discontinuation
  • 1983-03-28 CA CA000424696A patent/CA1212740A/en not_active Expired

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