EP0103336A2 - Arrangement de circuit adapté à générer des critères d'alarme en réponse à la détection d'erreur dans des messages échangés entre une paire d'unités fonctionnelles - Google Patents

Arrangement de circuit adapté à générer des critères d'alarme en réponse à la détection d'erreur dans des messages échangés entre une paire d'unités fonctionnelles Download PDF

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Publication number
EP0103336A2
EP0103336A2 EP83201281A EP83201281A EP0103336A2 EP 0103336 A2 EP0103336 A2 EP 0103336A2 EP 83201281 A EP83201281 A EP 83201281A EP 83201281 A EP83201281 A EP 83201281A EP 0103336 A2 EP0103336 A2 EP 0103336A2
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EP
European Patent Office
Prior art keywords
bits
unit
output
input
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP83201281A
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German (de)
English (en)
Other versions
EP0103336A3 (fr
Inventor
John W. Israel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Italtel SpA
Original Assignee
Italtel SpA
Italtel Societa Italiana Telecomunicazioni SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Italtel SpA, Italtel Societa Italiana Telecomunicazioni SpA filed Critical Italtel SpA
Publication of EP0103336A2 publication Critical patent/EP0103336A2/fr
Publication of EP0103336A3 publication Critical patent/EP0103336A3/fr
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1497—Details of time redundant execution on a single processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Definitions

  • the present invention relates to a circuital arrangement adapted to detect the presence of errors in the message exchanged between a pair of transceiving functional units and to generate alarm criteria when detection gives a positive result signalling that the error is to be ascribed to the transmitting unit or to the receiving unit.
  • Prior art comprises circuital arrangements designed to detect the presence of errors in the message exchanged between a pair of functional units which provide the presence of means, disposed in the transmitting sections, and adapted to associate a prefixed number of cyclic redundance bits with the bits of each message destined to be transmitted, the said cyclic redundance bits being computed according to a predetermined polynomial arrangement.
  • the said known arrangements further comprise means which are disposed in the receiving sections and are designed to detect the presence of errors in the received message through the test of the redundance bits; should said test detect the presence of errors, an alarm criterion is generated.
  • a similar circuital arrangement presents a drawback, since it is adapted to generate an alarm criterion without being able to give any information about the unit affected by said malfunction, the localization of the fault results to be therefore difficult.
  • Purpose of the present invention is to provide a circuital arrangement able to detect the presence of errors and to also inform whether the malfunction is to be ascribed to the transmitting section or to the receiving section.
  • Another aim is that to perform such a detection without causing delays in the transit time of the signals exchanged between said pair of units.
  • the object of the present invention consists of a circuital arrangement wherein the transmitting section of each functional unit is equipped with means designed to compute the cyclic redundance bits on the ground of the information bits of each message according to a prefixed polynomial. arrangement, and further adapted to send the information bits, together with the associated cyclic redundance bits, to the receiving section of the communicating functional units by means of a control unit.
  • the receiving section of said functional units comprises means designed to compute the cyclic redundance bits on the ground of the received messages and to send them to the control unit.
  • This unit is adapted to compute the cyclic redundance bits on the ground of the information bits in transit, to compare them with the cyclic redundance bits extracted from the message emitted by said transmitting section and to generate a first alarm criterion in case of non-identity in the compared quantities.
  • the control unit further computes the cyclic redundance bits, compares them with the cyclic redundance bits computed by the receiving section and generates a second alarm criterion, if non-identity in the compared quantities is detected.
  • the activation of the first alarm criterion and of the second alarm criterion therefore indicates a malfunction in the transmitting section and in the receiving section of said functional units.
  • Both the control unit and the transmitting and receiving section of said functional units are so arranged as to generate the cyclic redundance bits without causing any delay on the messages in conformity with the above mentioned purpose.
  • FU and FU 2 are used to indicate a pair of functional units, e.g. consisting of either a pair of processing units or a processing unit and a peripheral unit, which are designed to exchange messages comprising 24 information bits and 8 cyclic redundance bits.
  • the message transmission from unit FU to unit FU is performed serially by means of a wire indicated with MD, while the exchange of messages in the opposite direction is performed in a similar way by means of a wire indicated with mD.
  • unit FU is formed by a processing unit and that unit FU, is formed by a peripheral unit of FU 1 ; in this case a transfer cycle of a message is initiated by unit FU which generates a signal S which is received by a timing unit provided in a control unit CB.
  • This unit also receives from unit FU a signal B whose logic level indicates the transmission way of the message, and supplies the transmitting unit with a sequence of 32 timing impulses while supplying the receiving unit with a sequence of 24 timing impulses.
  • unit FU receives 32 timing impulses by means of a wire indicated with CK 1 and sends the 32 bits of the message to unit CB by means of wire MD.
  • Unit CB is adapted to extract from the message received at its input the 8 cyclic redundance bits computed by unit FU and is further adapted to compute the cyclic redundance on the ground of the 24 information bits of the message passing through it.
  • a first comparison circuit allocated in unit CB is adapted to generate a first alarm criterion A , in case it detects the non-identity between the cyclic redundance bits computed by FU and those computed by'unit CB, thus signalling the presence of a malfunction in unit FU .
  • unit FU 2 which is equipped with means designed to compute 8 redundance bits on the ground of the 24 information bits of the message received at its input, said means being further adapted to transfer said bits to unit CB.
  • a second comparison circuit allocated in unit CB is designed to generate a second alarm criterion A , in case it detects the non-identity between the cyclic redundance bits computed by unit FU 2 and those computed on the message in transit, thus signalling the presence of a malfunction in unit FU . 2
  • FIG. 2 is a detailed diagram of unit CB according to.figure 1, which provides the presence of a timing unit TM; in response to the reception of said signal S, the said unit provides at its first output the sequence 24 CK of timing impulses and at its second output the sequence 32 CK.
  • the input of unit CB further receives said signal B which reaches the control input of a first multiplexer MX comprising three sections.
  • the first section is connected to the outputs MD and mD of units FU and FU 2
  • the second section is connected to the outputs 24 CK and 32 CK of unit TM
  • the third section is connected to the same outputs of unit TM, said outputs having their position reversed with respect to that of the second section.
  • the output CK of the third section is designed to send the timing impulses to unit FU
  • the output CK 2 of the second section is designed to send the timing impulses to unit FU 2 .
  • signal B will provide such a level that unit MX renders available at the output of the first section the messages present on wire MD, whereas at the output of the second and third section it renders available the sequence of impulses 24 CK and 32 CK, respectively.
  • unit FU In response to the reception of the impulse sequence 32 CK, unit FU sends the 32 bits of a message on wire MD; such bits are sent to unit FU 2 simultaneously reaching the output of unit MX , to which there is connected a cyclic redundance generator RG .
  • the input of unit RG receives the impulses 24 CK so that is provides for computing 8 cyclic redundance bits on the ground of the 24 information bits emitted by unit FU and applies them to the first input of a comparison circuit CC 1 .
  • Wire MD also reaches the input of a first shift register SR 1 providing a capacity of 8 bits and its input receives a sequence of 32 timing impulses so that at the end of said sequence it has stored the 8 cyclic redundance bits computed by unit FU and applies them to the second input of unit CC 1 .
  • This unit is arranged to activate its output A when it detects the non-identity of the signals available at its inputs.
  • Unit FU 2 receives the 32 bits of the message together with the sequence 24 CK and starting from the 17th impulse of said sequence, computes the 8 cyclic redundance bits, as it will be described below with reference to figure 3, and sends this sequence to unit CB by means of wire mD.
  • Unit CB comprises a second shift register SR , whose input receives the data available on wire mD, as well as said sequence 24 CK, so that during the first 16 timing impulses it stores. bits providing a random value, while from the 17th to the 24th impulse it stores the cyclic redundance bits computed by unit FU .
  • the outputs of unit SR are applied to the first input of the second comparison circuit CC 2 , whose second input receives the outputs of unit RG 1 and generates an alarm criterion A , if it detects the non-identity of the quantities available at its inputs, thus signalling the presence of malfunctions in unit FU .
  • FIG. 3 illustrates the elements of unit FU 2 relevant to the invention. Said elements are not described in detail, since unit FU can utilize elements similar to those of unit FU , as specified in the following description.
  • Unit FU provides the presence of a register which is used to store both the input data and the output data and consists in fact of three shift registers SR , SR 4 and SR , each providing a storage capacity of 8 bits with both serial and parallel load input.
  • serial load input of register SR 3 is connected to the output of a multiplexer MX 2 , whose first input receives wire MD and whose second input receives the output of a cyclic redundance generator RG .
  • Unit FU 2 receives said signal B which is applied to both the control input of unit MX 2 and the control input of an additional multiplexer MX 3 , the first input of which receives the output of a third cyclic redundance generator RG 3 and the second input of which receives the output of register SR .
  • signal B provides such a level that the output of MX 2 generates the bits available on wire MD, while MX 3 emits on wire mD the bits available at the output of unit RG and the input-output register receives the sequence of impulses 24 CK, which determine the serial storage of the information bits generated by unit FU 1 .
  • unit RG 3 sends bits providing a random value on wire mD, while during the 8 bits of said sequence it generates as many cyclic redundance bits computed on the ground of the received bits and such a redundance is sent to register SR 2 by unit CB.
  • signal B provides such a level that multiplexer MX of unit CB emits the sequence of impulses 32 CK on wire CK 2 and the outputs of multiplexers MX 2 and MX 3 respectively send the bits available at the output of unit RG 2 and those available at the output of register SR S .
  • unit MX 3 provi des at its output the first 8 information bits of the message to be transmitted, which has been shifted in the register, thus emptying unit SR . 3
  • unit RG 2 has computed the 8 cyclic redundance bits and has transferred them into register SR 3 through unit MX 2 .
  • timing impulses of sequence 32 CK determine the transfer on wire mD of the remaining 16 information bits and of the 8 redundance bits, which had been previously stored in unit SR 3 .
  • Figure 3 also illustrates an embodiment of units RG and RG 3 which, in conformity with the above specified polynomial arrangement, consists of a first and a second exclusive OR and of an inverting circuit.
  • unit FU is formed by a unit designed to communicate with only one of units FU 2
  • FU 1 can be realized as shown in figure 3; if on the contrary unit FU must communicate with a plurality of units FU 2 , as illustrated in figure 4, it is convenient to utilize a further register (non illustrated) which is formed by as many units SR , SR 4 and SR .
  • a register is thus utilized to store the output data and it will be consequently connected to a unit similar to unit RG 2 , while another register to be used for storing the input data will be consequently connected to a unit similar to unit RG .
  • the prevision of a double register is due to the need to not limit the operative speed by means of an element which is utilized both as an input and an output device when the functional unit must communicate with a plurality of units.
  • figure 4 shows a connection diagram of said units in which there are displayed the additional devices that unit CB must provide in this case.
  • Unit FU is connected to all units FU 2 through wire MD, but only init FU , which is designed to exchange messages at the considered instant, receives a sequence of timing impulses through wires CK .
  • Wires CK 2 available at the output of unit MX 1 are applied to the input of a signal distributor DS which is addressed by a binary configuration emitted by unit FU 1 on wires AD.
  • unit FU 2i which receives the timing impulses, is adapted to receive or transmit messages.
  • Wires mD, through which units FU transmit the messages towards unit FU 1 are applied to the input of a multiplexer MX 4 which is also addressed through wires MD.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Emergency Alarm Devices (AREA)
  • Alarm Systems (AREA)
EP83201281A 1982-09-13 1983-09-06 Arrangement de circuit adapté à générer des critères d'alarme en réponse à la détection d'erreur dans des messages échangés entre une paire d'unités fonctionnelles Withdrawn EP0103336A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US417370 1982-09-13
US06/417,370 US4520481A (en) 1982-09-13 1982-09-13 Data-handling system for the exchange of digital messages between two intercommunicating functional units

Publications (2)

Publication Number Publication Date
EP0103336A2 true EP0103336A2 (fr) 1984-03-21
EP0103336A3 EP0103336A3 (fr) 1985-08-28

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP83201281A Withdrawn EP0103336A3 (fr) 1982-09-13 1983-09-06 Arrangement de circuit adapté à générer des critères d'alarme en réponse à la détection d'erreur dans des messages échangés entre une paire d'unités fonctionnelles

Country Status (5)

Country Link
US (1) US4520481A (fr)
EP (1) EP0103336A3 (fr)
BR (1) BR8304622A (fr)
DE (1) DE103336T1 (fr)
YU (1) YU184283A (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0280013A1 (fr) * 1987-01-29 1988-08-31 International Business Machines Corporation Dispositif pour vérifier le bon fonctionnement d'un générateur de code de contrôle
EP0535435A2 (fr) * 1991-10-03 1993-04-07 Motorola, Inc. Circuit et procédé de réception et transmission d'information de contrôle et d'état
US6912088B2 (en) 2000-07-12 2005-06-28 Thorlabs Gmbh Polarization mode dispersion emulator

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6151253A (ja) * 1984-08-20 1986-03-13 Nec Corp 誤り訂正回路
US5734826A (en) * 1991-03-29 1998-03-31 International Business Machines Corporation Variable cyclic redundancy coding method and apparatus for use in a multistage network
US5411654A (en) * 1993-07-02 1995-05-02 Massachusetts Institute Of Technology Method of maximizing anharmonic oscillations in deuterated alloys
US8166351B2 (en) * 2008-10-21 2012-04-24 At&T Intellectual Property I, L.P. Filtering redundant events based on a statistical correlation between events
US7936260B2 (en) * 2008-11-05 2011-05-03 At&T Intellectual Property I, L.P. Identifying redundant alarms by determining coefficients of correlation between alarm categories

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3735351A (en) * 1971-06-29 1973-05-22 Hydril Co Remote station address verification using address conditioned encoding

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3273119A (en) * 1961-08-21 1966-09-13 Bell Telephone Labor Inc Digital error correcting systems
US3439329A (en) * 1965-05-05 1969-04-15 Gen Electric Electronic error detection and message routing system for a digital communication system
DE2759106C2 (de) * 1977-12-30 1979-04-05 Siemens Ag, 1000 Berlin Und 8000 Muenchen Schaltungsanordnung zum Codieren oder Decodieren von Binarinformationen

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3735351A (en) * 1971-06-29 1973-05-22 Hydril Co Remote station address verification using address conditioned encoding

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0280013A1 (fr) * 1987-01-29 1988-08-31 International Business Machines Corporation Dispositif pour vérifier le bon fonctionnement d'un générateur de code de contrôle
EP0535435A2 (fr) * 1991-10-03 1993-04-07 Motorola, Inc. Circuit et procédé de réception et transmission d'information de contrôle et d'état
EP0535435A3 (en) * 1991-10-03 1994-06-22 Motorola Inc A circuit and method for receiving and transmitting control and status information
US6912088B2 (en) 2000-07-12 2005-06-28 Thorlabs Gmbh Polarization mode dispersion emulator

Also Published As

Publication number Publication date
EP0103336A3 (fr) 1985-08-28
DE103336T1 (de) 1984-07-05
YU184283A (en) 1986-04-30
BR8304622A (pt) 1984-04-24
US4520481A (en) 1985-05-28

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