EP0096027B1 - Circuit integre a l'echelle de tranche formant un labyrinthe de branchements - Google Patents

Circuit integre a l'echelle de tranche formant un labyrinthe de branchements Download PDF

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Publication number
EP0096027B1
EP0096027B1 EP82900118A EP82900118A EP0096027B1 EP 0096027 B1 EP0096027 B1 EP 0096027B1 EP 82900118 A EP82900118 A EP 82900118A EP 82900118 A EP82900118 A EP 82900118A EP 0096027 B1 EP0096027 B1 EP 0096027B1
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EP
European Patent Office
Prior art keywords
cell
cells
data
register
integrated circuit
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP82900118A
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German (de)
English (en)
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EP0096027A1 (fr
Inventor
John Terence Chamberlain
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Unisys Corp
Unisys Ltd
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Burroughs Corp
Unisys Ltd
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Priority to DE8585104574T priority Critical patent/DE3177079D1/de
Publication of EP0096027A1 publication Critical patent/EP0096027A1/fr
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G01R31/318511—Wafer Test

Definitions

  • the present invention relates to an integrated circuit memory comprising a plurality of self-testing shift register cells operable in response to a controller to execute a test and connect routine to form a long chain, shift register branched labyrinth across the face of the integrated circuit and thereafter to store data in the long chain and to access that data via a secondary, parallel, fast chain.
  • the wafer is generally of the order of 6 cm in diameter and may contain many hundreds of circuits. It is the practice thereafter to cut the wafer to free each individual circuit, and to individually package each circuit.
  • Integrated circuit packaging is area and volume inefficient. The package, because of clearances required for headers and leads, is many times the area and thickness of the individual circuit. The larger the circuit which can be accommodated, the more efficient the packaging becomes. As a limit, the packaging becomes most efficient when the entire wafer can be accommodated as a single circuit.
  • Manufacturing tolerances mean that only a proportion of the surface of any wafer is correctly processed during integrated circuit manufacture. Areas not correctly processed yield non-working components. The likelihood of an entire wafer being fabricated as a single, working circuit is so low as to render any attempt to make such a device impractical.
  • Such methods include common electrical connections to each of the elements, undesirable because a failure in the common structure renders the entire wafer inoperable. Also included are methods where elements test and connect to adjacent elements of the wafer 10 across boundaries therebetween, but where the proportion of working elements which are ignored by the test routine is unacceptably high.
  • Such whole-wafer integrated circuits are notably employed for use in data storage as memories.
  • the individual elements contain shift registers which are connected, whenever that element is tested and found to be working, as part of a long shift register configured from the tested and working elements on the wafer. Problems exist in the slowness of data deposition or aquisition in such a structure.
  • a whole wafer integrated circuit is vulnerable to fabrication or operational faults which cause the power supply to individual elements therein to be short circuited. It is known to employ fusible links to isolate such elements and allow the others to continue functioning. The incorporation of fusible links introduces yet another source of possible failures, and does not allow the minimisation of the power requirement of the wafer by switching off individual elements that might not be required to be incorporated in the operation of the wafer.
  • an integrated circuit suitable for use as a memory and for fabrication as a whole-wafer device, comprising a plurality of individual elements having the minimum of common circuitry, where the elements may be tested and incorporated into the operation of the wafer in a manner which allows for the incorporation of a high proportion of all functional elements, where the coupling of power to an element is selectable, and wherein data may be deposited or retrieved rapidly.
  • European Patent Application EP-A-0 080 834 published 08.06.1983 by the same applicants discloses a wafer scale integrated circuit of very large proportions wherein a plurality of cells may be caused to be tested and incorporated into the operation of a large scale data processing function if the test is passed, any cell which has passed the test and been incorporated resisting approaches from neighboring cells to participate in the test.
  • the present application differs therefrom in permitting each cell which has passed said test and has been incorporated simultaneously with every other cell which has passed said test and been incorporated offering to test a neighboring cell and, every neighbouring cell which has not been incorporated simultaneously accepting an approach and being tested with every other neighbouring cell receiving the approach and not having been incorporated.
  • European Patent Application EP-A-0 080 834 allows for only one cell at a time to offer an approach to a neighbouring cell.
  • the present application allows forthe growth of a branched labyrinth of cells in a short time by permitting incorporation of a plurality of cells at each test cycle, whereas European Patent Application EP-A-0 080 834 allows only one cell to be connected and incorporated at a time.
  • the present application by providing that all cells offering an approach to a neighbouring cell do so in the same direction and on each occasion of offering swing that direction around, allows for the growth of a branched labyrinth which is efficient in picking up working cells on the wafer.
  • United Kingdom Patent 1,377,859 discloses a wafer scale integrated circuit wherein a plurality of integrated circuit cells are provided in a tesselation on a wafer. Simple spiral growth is disclosed wherein growth is permitted by addition only to the tip cell of the spiral.
  • the present application discloses a wafer scale integrated circuit wherein all cells which have been incorporated into the operation of the circuit simultaneously offer the test to a neighbouring cell and any neighbouring cell which has not been incorporated into the operating circuit simultaneously with every other neighbouring cell which has not been incorporated into the operation of the circuit accepts that approach, is tested and is incorporated if working.
  • the present application thus discloses a manner of growth of an integrated circuit array on a wafer scale integrated circuit of greater speed than that disclosed in United Kingdom Patent 1,377,859 where growth is only permitted by addition of one cell at a time.
  • the present application allows the addition of many cells at a time into the working of the circuit.
  • United Kingdom Patent Application GB-A-2,006,522 discloses a multicellular electronic circuit where individual data processing cells may be connected in the manner disclosed in United Kingdom Patent 1,377,859 described above, but with the difference that electrical connections are provided across the boundaries of the electronic circuit such that topologically speaking, the cells rather than being on a flat surface are effectively on the surface of a cylinder or of a toroid.
  • United Kingdom Patent 1,377,859 the present application seeks to provide improvement over United Kingdom Patent Application GB-A-2,006,522 by providing an integrated circuit wherein a plurality of new cells may be incorporated into the operation of the circuit at each testing cycle as opposed to the one cell at a time growth disclosed in GB-A-2,006,522.
  • the present invention consists in an integrated circuit comprising a plurality of functionally testable cells, each of said plurality of cells being coupled simultaneously to receive a common control signal, each of said plurality of cells which is not in receipt of functional coupling being operable, in response to an approach from a neighbouring cell to accept said functional coupling therefrom and to undergo a functional test and, if said functional test is passed, to have said functional coupling confirmed and maintained, but if said functional test is failed, to have said functional coupling removed; where each cell in receipt of said functional coupling and having had said functional coupling confirmed is operable to provide said approach to a selected neighbouring cell and where each cell already in receipt of said functional coupling is operative to resist said approach by failing to accept said functional coupling from more than one neighbouring cell at a time; said integrated circuit being characterised by every cell in receipt of said functional coupling and having had said functional coupling confirmed being operable, simultaneously with every other cell in receipt of said functional coupling and having had said functional coupling confirmed, in response to said common command signal to select a
  • EP-A-0 172 311 published on 26.02.1986 which has the particular description and figures in common with those of the current application.
  • the claims of EP-A-0 172 311 relate to an integrated circuit comprising a data storage element of the type described herein with particular reference to figures 4 and 20.
  • coupling is defined as coupling for the transfer of data and/or control signals.
  • an integrated circuit comprises a plurality of cells preferably on the same wafer.
  • the cells are preferably provided with a common control signal to which each cell is operable to respond by executing a functional test, cells which have already passed the test being operable to initiate the test in any neighbouring cell in a selectable direction provided the neighbouring cell has not already undergone the test, and to functionally link to the neighbouring cell if the neighbouring cell passes the test.
  • the selected direction of test preferably rotates by fixed increments or decrements after each functional test cycle.
  • the cells are preferably square, in which case the direction of test preferably decrements or increments by 90°.
  • the cells preferably test and interconnect to form a branched labyrinth structure over the surface of the wafer.
  • the testing preferably starts at an input port.
  • the tests are preferably conducted under instruction from a controller, connected at the input port.
  • the cells are preferably identical.
  • the cells are preferably interconnectable to form a chain shift register memory looping once around the labyrinth.
  • Each cell preferably comprises a state machine for conducting the functional test supervision.
  • the cells preferably comprise a switching matrix at each boundary edge to each neighbouring cell.
  • the matrix preferably allows that signals pass in and out of the cell when instructed in a first manner, allows signals to loop around the cell when instructed in a second manner, and allows a form of coupling required fortesting when instructed in a third manner.
  • the chain shift register memory preferably comprises a data storage chain in parallel with a data access chain and a control character chain, together with cross-over switches operable to cross-over the data in the data storage chain and the data access chain whenever the register in the control character chain which is associated with a switch contains a predetermined character.
  • the individual registers in the data access chain and the control character chain are preferably only one bit long.
  • the chain shift register memory preferably comprises a data comparison element for comparing the output of each data storage register with the output of its associated data access register and activating the cross-over switch when a data match is found and a predetermined character is in the associated control register to provide a content addressable feature.
  • the supply of power to each cell is preferably dependent upon whether or not that cell is functionally coupled to another.
  • a full size silicon wafer 10 has fabricated thereon a plurality of square, contiguous, memory storage cells 12 in regular array arranged in a square tessellation.
  • the site which should be occupied by one of the cells 12 is left blank to make a coupling port 14.
  • Each cell 12 is operable to test a selectable one of its bordering neighbours, with the exception of the edge cells 16, which have one or more sides unbounded by a neighbour, and cannot therefore test in those directions.
  • Figure 2 shows, in schematic form, the interconnections between cells 12 on the wafer 10.
  • Each of the cells 12 is coupled, along its boundary edges, with each of the four bordering cells. There. are seven connections between bordering edges.
  • a fast in line 20 conveys rapid transit data into each cell 12.
  • a control in line 22 conveys control characters into the cell 12.
  • a slow in line 24 conveys slow, shift register contained stored data between cells 12.
  • a bidirectional control line 26 is used for cells 12 to signal to neighbouring cells 12 along their boundaries during testing.
  • a slow out line 28 conveys slow, shift register stored data out of each cell.
  • a control out line 30 conveys control characters out of each cell.
  • a fast out line 32 conveys rapid transit data out of each cell 12.
  • every cell 12 on the wafer 10 is coupled to a power line 34, for providing D.C.
  • FIG. 3 shows the coupling port 14.
  • One edge of the coupling port 14 is provided with pads for connecting the wafer 10 to the outside world. These pads are connected by gold wire bonding in the manner normal for integrated circuit manufacture, to external connections on the wafer enclosure. The pads connect to a first cell 40 which cannot test in the direction of the pads just as the edge cells 16 cannot test into the void.
  • a fast out pad 320 carries rapid transit data out of the wafer 10.
  • a control out pad 300 conveys control characters out of the wafer 10.
  • a slow out pad 280 conveys slow, shift register stored data out of the wafer 10.
  • a power in pad 340 conveys power to each cell 12 on the wafer 10 via the power line 34.
  • a clock input pad 360 provides an input for the common clock line 36.
  • a command input pad 380 provides an input to the function line 38.
  • a command line pad 260 allows a command line signal to be linked to the first cell 40.
  • a slow in pad 240 couples slow data into the wafer 10.
  • a control in pad 220 couples control characters into the wafer 10.
  • Figure 4 shows details of the individual cell 12 in the polycellular array on the wafer 10.
  • Each cell 12 has four sides, hereinafter referred to by the points of the compass, North N, South S, East E and West W.
  • Each of the boundaries N, E, S, W is provided with a signal switching matrix, 50N, 50E, 50S and 50W respectively, hereinafter collectively referred to as 50(NESW).
  • the matrices 50 are interconnected by four data storage shift registers 52NE, 52ES, 52SW and 52WN respectively, the first letter suffix indicating the matrix 50 of origin and the second letter of the suffix indicating the matrix 50 of destination.
  • the length of the shift registers 52 is immaterial to the operation of the present invention. In the particular case of the preferred embodiment they are 360 bits long.
  • the shift registers 52NE, 52ES, 52SW and 52WN represent the data storage capacity of the cell 12.
  • the matrices 50(NESW) are similarly interconnected by four single bit fast registers 54NE, 54ES, 54SW and 54WN respectively, the letter suffices having the same meaning as before.
  • four single bit control registers 56NE, 56ES, 56SW and 56WN are interconnected between the matrices 50(NESW) with the letter suffices yet again indicating the same information.
  • a state machine 58 controls the matrices 50(NESW) via connect signals on connect command couplings, one to each matrix 60N, 60E, 60S and 60W respectively, and cross-over signals on cross-over couplings 62N, 62E, 62S and 62W respectively.
  • the state machine 58 is responsive to and operable to provide signals on the command lines 26N, 26E, 26S and 26W,'these being the lines used to signal between adjacent state machines 58 in the polycellular array.
  • the power line 34 is coupled to every element in the cell 12, via the state machine 58, the clock line 36 is coupled to every element in the cell 12, and the function line 38 is coupled to the state machine 58.
  • Each of the matrices 50(NESW) contains a comparison element for bit-by-bit comparisons of incoming and outgoing data.
  • the detection of an error in the comparison is signalled to the state machine 58 via the error couplings 64N, 64E, 64S and 64W.
  • the state machine is responsive to the contents of the control shift registers 56NE, 56ES, 56SW and 56WN and is coupled thereto via the control couplings 66NE, 66ES, 66SW and 66WN respectively.
  • That matrix couples the output of the incoming slow register 52WN, 52NE, 52ES or 52SW respectively as the input to the outgoing slow register 52NE, 52ES, 52SW or 52WN respectively, couples the output of the incoming fast register 54WN, 54NE, 54ES or 54SW respectively as the input to the outgoing fast register 54NE, 54ES, 54SW or 54WN respectively, and couples the output of the incoming control register 56WN, 56NE, 56ES or 56SW respectively as the input to the outgoing control register 56NE, 56ES, 56SW or 56WN respectively.
  • the state machine 58 further provides, to the matrices 50N, 50E, 50S an.d 50W, a test signal via the test connectors 68N, 68E, 68S and 68W respectively.
  • a matrix 50N, 50E, 50S or 50W is in receipt of the test signal it responds by coupling the output of the incoming control register 56WN, 56NE, 56ES or 56SW respectively as the input to the outgoing control register 56NE, 56ES, 56SW or 56WN respectively and as the input to the control out line 30N, 30E, 30S or 30W respectively, couples the output of the incoming fast register 54WN, 54NE, 54ES or 54SW respectively as the input to the outgoing fast register 54NE, 54ES, 54SW or 54WN respectively and as the input to the fast out line 32N, 32E, 32S or 32W respectively, and couples the output of the incoming slow register 52WN, 52NE, 52ES or 52SW respectively as the input to the outgoing slow register 52NE, 52ES, 52SW or 52WN respectively,
  • FIGS 5A through 5F show the coupling function of the North matrix 50N in schematic form, it being understood that the other three matrices 50E, 50S and 50W function in the same manner.
  • Figure 5A shows the situation where the matrix 50N is in receipt of neither the cross-over instruction, the connect instruction nor the test signal.
  • Figure 5B shows the situation where the matrix 50N is in receipt of neither the connect instruction nor the test signal but is in receipt of the cross-over command.
  • Figure 5C shows the situation where the matrix 50N is in receipt of the connect command.
  • Figure 5D shows the situation where the matrix 50N is in receipt of both the connect command and the cross-over command.
  • Figure 5E shows the situation when the matrix is in receipt of the test signal.
  • Figure 5F shows the situation where the matrix 50N is in receipt of both the test signal and the cross-over command.
  • FIG. 6 shows, in schematic detail, the inter-coupling across the Northern edge N of the cell 12, it being understood that the intercoupling across the three remaining edges E, S and W is the same.
  • a flip-flop, the CON F/F 51 N is set by the application of either the test command or the connect command and an establish connection signal on the connector 93.
  • the output of CON F/F 51 N is used to maintain the permanent coupling across the boundary N to the adjacent matrix 50S, consistently with Figures 5C and 5D, when either the test command or the connect command is removed by state machine 58 after determining that such a permanent connection should be established.
  • the flip-flop 51 N is reset by a master reset signal on the connector 95.
  • the fast out line 32N couples to the fast in line 20S' of the adjacent cell.
  • the control out line 30N couples to the control in line 22S' of the adjacent cell.
  • the slow out line 28N couples to the slow in line 24S' of the adjacent cell.
  • the command line 26N couples to the command line 26S' of the adjacent cell.
  • the fast out line 32S' of the adjacent cell couples to the fast in line 20N.
  • the control out line 30S' of the adjacent cell couples to the control in line 22N.
  • the slow out line 28S' of the adjacent cell couples to the slow in line 24N.
  • Figure 7 shows the manner in which the Northern matrix 50N detects and signals errors to the state machine 58, it being understood that the other three matrices 50E, 50S and 50W function in the same manner.
  • a first exclusive or gate 72 monitors the data arriving on the incoming fast in line 20N and going to the outgoing fast out line 32N. If the two data bits so presented are not the same, an error is indicated and the first exclusive or gate 72 provides a logically true output.
  • a second exclusive or gate 74 monitors the data going out on the outgoing slow out line 28N and the data arriving on the incoming slow in line 24N and provides a logically true output if the data bits so delivered are not the same.
  • the output of the first and second exclusive or gates 72 and 74 are logically combined by an or gate 76 whose output provides a logically true error indication on the error coupling 64N in the event of either data mismatch as described.
  • Figure 8 shows, in schematic form, the elements and intercouplings of the state machine 58.
  • the state machine 58 comprises a logic network 80 which is control and next state logic under the command of a three bit state counter 82.
  • the state counter 82 and the logic element 80 together form a sequential logic state machine having eight main states designated 0 to 7 inclusively and six subsidiary states 0' to 5' inclusively.
  • a command decoder 84 receives the clock signal from the clock line 36 and the common command signal from the function line 38 and decodes them in a manner explained below to provide a master reset signal MR, a first global signal G1 and a second global signal G2, all three used for the control of the state machine 58.
  • a two bit direction counter 86 provides a two binary digit, steering output to a selection gate 88.
  • the selection gate, 88 in response to the output of the counter 86 steers the common command line 90 onto a selected one of the command lines 26N, 26E, 26S or 26W, steers the common connect line 92 onto a selected one of the connect lines 60N, 60E, 60S or 60W, and steers the common test line 94 onto a selected one of the test lines 68N, 68E, 68S or 68W.
  • the direction counter 86 is incremented by a G1 signal when the state machine 58 is in state 0 and rest by the MR signal.
  • a 4 bit latch 96 receives the contents of the control registers 56WN, 56NE, 56ES and 56SW via the control couplings 66WN, 66NE, 66ES and 66SW and latches them, in response to a G2 signal, to the cross-over couplings 62N, 62E, 62S and 62W respectively, the latch 96 being reset with its outputs zero by a MR signal.
  • the logic element 80 receives and is responsive to the error indications on the error couplings 64N, 64E, 64S and 64W.
  • the logic element 80 is operable to set and reset, and respond to the states of a complete flip-flop 98, an active ftip-fiop-100 and a fault flip-flop 102.
  • the selection gate 88 is also responsive to the state of the active flip-flop 100 in determining the direction in which to steer its input signals.
  • the switch 104 is also operable, in response to a switch command from the logic element 80 via the switch coupling 108, to selectably remove or supply power to the cell 12.
  • the state machine 58 responds to the global commands G1, G2 to test adjacent cells and incorporate them into a memory system should they prove working.
  • the first cell 40 is tested by a controller whose details are given below, and if found good, is accepted into the system and itself becomes a tester for the next cell 12.
  • the direction of test is rotated by 90° at each stage, so that the labyrinth of connected cells develops branches.
  • Figures 9A to 9L illustrate the action of the interconnect method on a perfect wafer 10 having no non-functional cells thereon.
  • the direction of test is indicated by the arrow 112 next to the labyrinth 110: It is assumed that the interconnections to the outside world on the coupling port 14 are on its south side and that the rotation of direction follows the order SWNE repeatedly from figure 9A to 9L. It is seen that the labyrinth grows at a rate which increases with size, and all cells are incorporated.
  • the controller 120 firstly tests in the south direction and incorporates a first cell A, as shown in figure 9A. Having incorporated the first cell A the controller 120, as shown in figure 9B, commands the first cell A to test in a westerly direction whereupon the first cell A incorporates by linking thereto, a second cell B. In figure 9C the controller 120 commands the first and second cells A, B to test in a northerly direction. The first cell A tries to test the hole 14, but obtains no response. The second cell B picks up a third cell C.
  • Figure 9D shows the controller 120 commanding the first, second and third cells A, B, C to test in an easterly direction. The third cell C tries to test the hole 14 but cannot do so.
  • the second cell B is inhibited from testing the first cell A, because it has already undergone the test, but the first cell A picks up a fourth cell D.
  • Figure 9E shows the controller 120 commanding all incorporated cells A, B, C, D to test in a southerly direction.
  • the third cell C tries to but cannot test the second cell B as the second cell is already incorporated.
  • the first, second and fourth cells each pick up one fifth cell E.
  • Figure 9F shows the controller 120 commanding all of the incorporated cells A, B, C, D, E to test the adjacent cell in the westerly direction.
  • FIG. 9G shows all incorporated cells testing in a northerly direction and all cells free to do so picking up three sixth cells G.
  • all cells thus far incorporated at each stage test firstly in an easterly direction then in a southerly, westerly, northerly and again in an easterly direction respectively, incorporating seventh cells H, then eight cells J, ninth cells K, tenth cells L and eleventh cells M wherever the cell adjacent to another is free to be incorporated. This process may be continued until the entire wafer 10 is used up. Cells 16 at the edge of the tessellation obviously cannot link other than into the tessellation.
  • Figure 10 shows the labyrinth growth of figure 9A to 9K taken to a total of 20 stages. The pattern of interconnection so obtained is apparent.
  • Figure 11 shows the result of a 20 stage growth cycle, executed in the same manner as the growth cycle of figure 10, but on a wafer with defective cells which are rejected for incorporation and indicated by crosses. It is seen that all good cells around the defective cells are incorporated. That is not to say that patterns of defective cells do not exist which prohibit the incorporation of some working cells, but in general a very high percentage of working cells will be picked up.
  • the command decoder 84 generates the global signals G1, G2 and the master reset MR signal from the clock signal and the function signal in the manner indicated by table 1 below.
  • the clock signal is a 50% mark to space ratio repetitive clock of fixed period.
  • the decoder 84 operates on the clock signal by means of gates and binary dividers to generate two separate 2-phase clock signals, C1 and C2 each of which comprises every alternate logically true portion of the clock signal, in a manner well known in the art. Such division leaves an indeterminacy as to which of the Cl and C2 signals occurs first. A method is therefore provided to rectify this deficiency, as shown in Table 1.
  • the state counter 82 operates in a simple Gray code. If the outputs of the counter 82 are indicated by A1, A2 and A3, then the counter operates as indicated in table 2 below.
  • the direction counter 86 operates in the manner indicated by table 3 below.
  • ACTIVE 100 When ACTIVE 100 is set the particular cell is a tester and the test coupling 68 is activated in the appropriate direction. Otherwise, with ACTIVE 100 reset, the cell is subject to testing and connect coupling 60 is activated.
  • Figure 12 shows the manner of connection of the wafer 10 when employed as a memory.
  • the wafer 10 is coupled, via the pads of figure 3 on the coupling port 14, to a controller 120.
  • the controller 120 is operable to execute a test and grown sequence of commands to the wafer 10 and thereafter to supervise the deposition and retrieval of data in the now established and tested memory.
  • the controller 120 is mutually coupled to a host system, such as a data processor 122.
  • the controller 120 provides indication to the host 122 when the memory has been tested and established enabling the host 122 to commence to use it.
  • the size of the memory to be established is either defined by the host 122 signalling to the controller 120, or is a predetermined feature of the controller 120.
  • the controller 120 issues the operational signals, the first Global signal, hereinafter referred to as G1, the second Global signal, hereinafter referred to as G2 and the Master reset signal, hereinafter referred to as MR to the wafer 10, coded on clock and function lines and between issuing signals runs in test patterns of fast data, slow data and control characters to test the overall memory loop for errors and in particular to test those cells 12 which are first being coupled into the overall circuit.
  • the checking for errors takes place partly within the controller 120 and partly within the cells 12 themselves.
  • the controller 120 looks and behaves just like a cell 12 already incorporated into the circuit.
  • the controller when testing the first cell 40, behaves just as the first cell 40 behaves when testing a following cell 12, after the first cell 40 has been incorporated into the circuit.
  • cells are distinguished by the state of the ACTIVE flip-flop 100, those cells 12 where it is set being tester cells and cells 12 where it is not set and adjacent in the direction of test to a tester cell being subject cells.
  • the controller 120 first issues the master reset signal MR to all cells 12 on the wafer, so resetting all counters and latches and putting the state machine 58 into state 0.
  • This master reset (MR) is used only when testing the first cell 40, the state machine usually being set into state 0 by a G1 signal being applied when it is in state 7, as described below.
  • the controller 120 then issues, with the state machine in state 0, a G1 signal, which has the effect of incrementing the direction counter 86 and setting the state machine 58 into state 1.
  • the G1 signal is gated by the state machine 58 such that it reaches the direction counter 86 only when the state machine 58 is in state 0.
  • the gated G1 signal is called the ROTATE signal.
  • the effect of incrementing the direction counter is to swing the direction of test by ninety degrees.
  • Figure 13 shows the effect, in schematic form, of the action take by the controller 120 while the state machine 58 is in state 1.
  • the controller then issues a G2 signal to all of the cells 12, which has the effect of coupling all of the contents of control registers 56WN, 56NE, 56ES and 56SW, already filled with all ones, to the cross-over connections 62N, 62E, 62S and 62W respectively, and so setting all of the matrices 50N, 50E, 50S and 50W into the cross-over mode.
  • Figure 14 shows the situation achieved, in terms of fast and slow register 52, 54 interconnection, by this last operation.
  • Every cell 12 is in the condition indicated, whether it be a tester or a subject.
  • the one bit long fast registers 54 hereinafter described without their former suffix
  • the slow registers 52 hereinafter also described without their suffix, form two chains passing between the slow in SI line from the incoming matrix to the slow out line SO back to the incoming matrix, and between the fast in line FI from the incoming matrix to the fast out line FO back to the incoming matrix. If the slow registers are n bits long, then the total length of each path is 2n+2 bits.
  • the controller 120 then administers identical patterns to the fast in pad 200 and to the slow in pad 240, the patterns consisting of pseudo-random sequences each 2n+2 bits long so that the signal at SI is the same as the signal at SO and the signal at FI is the same as the signal at FO. The controller 120 does this until it sees the patterns returning and knows that it has filled the fast 54 and slow 52 registers.
  • Each state machine 58 watches the output of the input matrix error lines 64N, 64S, 64E or 64W. It takes at least 2n+2 clock cycles before any match on any cell can be obtained.
  • the error line 64N, 64S, 64E or 64W hereinafter referred to without its suffix as 64, must show an initial fault indication, in response to which the logic element should set the fault flip-flop 102. If the fault flip-flop 102 is not set, the cell 12 is incapable of detecting errors and is therefore inhibited from passing into state 2 of the state machine 58 as it is incapable of testing neighbouring cells.
  • the cell is frozen in state 1, in which frozen state the logic element 80 commands the switch 104 to remove power from the registers.
  • the fault flip-flop 102 is set, and there is no output on the error line 64, the subject cell 132 is allowed to pass to further tests. If the fault flip-flop 102 is not set the subject cell 132 is incapable of acting as a tester and is therefore of no further use.
  • the controller 120 After filling the fast registers 54 and the slow registers 52 with the 2n+2 bit long pattern.
  • the controller 120 issues a G1 signal which has the effect of sending all subject cells 132 where the fault flip-flop 102 is set into state 2 and powering down and freezing in state 1 all subject cells where the fault flip-flop 102 is not set. The act of passing into state 2 resets the fault flip-flop 102.
  • state 2 the data integrity of the registers 52, 54 and cross-over switching function of the matrices 50 is tested.
  • the controller 120 keeps the 2n+2 bit long data pattern circulating all the time. At least one data pattern is allowed to pass through each subject cell 132.
  • the controller 120 then runs in a pattern of alternate 1s and Os into the control register 56 and strobes the G2 signal to latch the matrices 50 into the connection configuration shown in figure 15, the paths still being 2n+2 bits long. This action, since it maintains the paths at the same length, does not introduce an indication of error.
  • the controller Having allowed at least one 2n+2 bit long data pattern to pass through each subject cell 132, the controller then runs in a pattern of alternate Os and 1s into the control registers 56 and issues another G2 signal to flip the connections of figure 15, i.e. cross-over where straight through previously and vice versa, still maintaining a path length of 2N+2 bits and therefore not inducing an indication of error. Having allowed at least one complete data pattern to pass through each subject cell 132, the controller runs all zeros into the control registers 56 and issues a G1 signal, which has the effect of sending all subject cells where there has not been an error, i.e.
  • state 3 the error line 64 is disabled by logic element 80 from setting fault F/F 102, and the complete flip-flop 98 is tested.
  • the controller 120 issues a G2 command which latches the zeros of the control registers 56 to the matrices 50 and has the effect of setting the complete flip-flop 98 whose output is ignored by virtue of the state machine 58 being in state 3.
  • the flip-flops 98, 100 should initially have been reset by the Master reset signal MR.
  • the function of the complete flip-flop 98 is to inhibit all further testing and labyrinth growth (when set other than in state 3).
  • the function of the Active F/F 100 is to make a good tested (subject) chip into a tester, in which condition it continues to test its neighbours until Complete is set.
  • the controller When Active is set, the chip does not respond to testing and connection signals. It is only necessary to test the complete flip-flop 98, since a failure of the active flip-flop 100 to reset on MR ensures that no testing will have taken place in the subject cell 132.
  • the controller having set all of the matrices 50 into the straight through mode, so that the path length between the slow incoming line Si and the slow outgoing line SO is 4N bits long and the path length between the fast incoming line FI and the fast outgoing line FO is 4 bits long, runs 4 bit repeating patterns into the fast in pad 200 and 4N bit long repeating patterns into the slow in pad 240 until it knows that the registers 52, 54 are full by the reappearance of the 4N bit long patterns on the slow out pad 280.
  • the controller then issues a G1 signal which has the effect of sending all subject cells 132 where the complete flip-flop 98 is set into state 4 and freezing, and powering down any subject cells 132 where the complete flip-flop 98 is not set.
  • the act of entering state 4 causes the complete flip-flop 98 to be reset and the error line 64 is enabled to set fault F/F 102.
  • the controller 120 keeps the wafer 10 in state 4 until a complete data pattern of 4N bits has passed through the slow registers 52.
  • the controller 120 then applies a G1 signal which has the effect of sending all subject cells 132 which have not experienced a fault, i.e. wherein the fault flip-flop 102 is not set, into state 5, and freezing and powering down all subject cells 132 where the fault flip-flop is set.
  • the controller next issues a further G1 signal which has the effect of sending all newly tested cells into state 6 provided that the CON flip-flop 51 is set. If the CON flip-flop is not set the newly tested cell is frozen in state 5 and is powered down.
  • tester cells 130 drop the signal on their command lines 26 and the newly tested subject cells 132 raise a signal on their command lines 26 in the direction of the tester cells 130.
  • the controller 120 then applies the G1 signal to take all cells into state 7.
  • the tester cells 130 apply the establish signal on connector 93 which, in conjunction with the test command signal 68 sets the CON F/F 51 in the direction towards the subject cells 132 to confirm the connection established in the subject cells in state 5, provided that the Fault F/F's 102 in the tester cells are not set, and also provided that the said subject cells have raised the required signal on their command lines 26 in state 6.
  • the controller 120 then applies yet another G1 signal to send the state machine 58 back to state 0.
  • the controller 120 makes the decision if further growth is required. If further growth is required, a G1 signal is applied to the wafer 10 and it continues on a new cycle in the growth phase. If no further growth is required, the controller 120 sets the complete flip-flop 98 in every single cell 12 on the wafer 10, and thus inhibits all further testing and growth, by sending a G2 signal while state machines 58 are in state 0.
  • the controller 120 then signals to the host 122 that the memory that has been established is adequate and changes to an operational mode for servicing the data access of the memory in response to host commands.
  • controller 120 may scrap the established memory by issuing the master reset MR signal and starting again from another edge of coupling port 14. Repeated failure will result in shutdown.
  • the operation of the state machine 58 is shown and further described by the state diagram of figure 16.
  • the transitions of the state machine 58 when in a subject cell 132 are indicated by solid line, and when in a tester cell 130 are shown by dotted line.
  • Table 4 given hereinafter lists and explains the symbols used in figure 16.
  • Eight main states 0 to 7 are shown, corresponding to the three bit count of the state counter 82.
  • Five default states 1' to 5' are entered and maintained in the event of a functional test being failed in any of main states 1 to 5 respectively.
  • the termination of growth state 0' is entered from state 0 by the controller 120 issuing a G2 signal instead of a G1 signal, whereafter the incorporated cells 12 are used as a data store for the host 122.
  • Table 5 summarises the actions of the state machine 58 in a subject cell 132 as the state machine 58 moves between the states indicated in figure 16.
  • Table 6 summarises the actions of the state machine 58 in a subject cell 132 in each of the states of figure 16.
  • Table 7 summarises the actions of the state machine 58 in a tester cell 130 as the state machine moves between the states allowed to it in figure 16, and table 8 summarises its actions when in those states.
  • Table 9 summarises the actions of the controller 120 taken when the state machine 58 is in each state to test the data transfer properties of each cell 12 and to cycle the state machine 58 between states.
  • the controller 120 has no direct feedback indicative of the state that any of the state machines 58 are in, but assumes that the state machines 58 respond to its sequence of input signals G1, G2, MR.
  • the invention has so far been described with reference to having connections to the controller 120 on one edge only of the coupling port 14. It is advantageous to employ connections to two, three or four edges on the coupling port 14 so that the controller 120, when faced with a failure to establish a sufficiently large memory, may try again by starting at an alternative face.
  • Figure 17 shows the layout, in physical terms, of the memory established by the controller 120, when the memory is finalised in a state corresponding to the growth point indicated in figure 9F.
  • the data path 138 wends a labyrinthine route between the cells 12 starting at and ending at the coupling port 14. The same is true no matter what the size of the established memory.
  • the data path 138 comprises a fast data path consisting of the fast registers 54 connected in series, a slow data path consisting of the slow shift registers 52 connected in series, and a control path, consisting of the control registers 56 connected in series, all three paths running in parallel and all series connections being established through the matrices 50. It is to be noted that the path 138, topologically speaking, may be represented as a single loop.
  • Figure 18 shows a portion of the data path 138 stretched out into the topologically equivalent straight line.
  • the chain of fast registers FA, FB, FC, FD are the one bit long fast shift registers 54WN, 54NE, 54ES, 54SW of figure 4, but, as will be appreciated from figure 17, the actual coupling need not be in any particular order.
  • the chain of slow registers SA, SB, SC, SD are the N-bit long shift registers 52WN, 52NE, 52ES and 52SW of figure 4. Once again, they need not be in any particular order and sequential members in the chain may be on adjacent cells 12.
  • the chain of 1 bit long control shift registers CA, CB, CC and CD are the control registers 56WN, 56NE, 56ES and 56SW of figure 4.
  • the cross-over matrices MA, MB, MC and MD are part of the switching matrices 50N, 50E, 50S and 50W and they too are subject to the same indeterminacy of order.
  • the latches LA, LB, LC and LD are individual elements in the 4 bit latch 96 of figure 8 and are operable, in response to the second global signals G2, to latch the state of the control registers CA, CB, CC and CD to the matrices MA, MB, MC and MD, which respond to a latched logical 1 signal by going into the cross-over mode and in response to a latched logical 0 signal go into the straight through mode.
  • the individual registers are physically associated, with the elements FA, SA, MA, LA, and CA being in the same quadrant of the same cell 12, FB, SB, MB, LB and CB being similarly associated, as are FD, SD, MD, LD and CD and FC, SC, MC, LC and CC.
  • Figure 19A shows the addressing of a record in the chain 138.
  • the slow registers SA, SB, SC and SD are shown as containing between them, all of four data records R1, R2, R3 and R4 and part of a fifth data record R5.
  • the records R1, R2, R3, R4 and R5 are each 1 bit shorter than the slow registers SA, SB, SC and SD.
  • the first register SA contains all of the first record R1 and one bit of the second record R2.
  • the second slow register S2 contains all but one bit of the second record R2 and two bits of the third record R3.
  • the third slow register SC contains all but 2 bits of the third record R2 and three bits of the fourth record R3.
  • the fourth slow register SD contains all but 3 bits of the fourth record R4, and four bits of the fifth record R5. This one-bit-at-a-time overspill continues up the chain 138.
  • the slow registers SA, SB, SC, SD are each N bits long, it will take a maximum of N clock cycles to bring any particular record into a position to be accessed.
  • the first record R1 is to be accessed.
  • the controller 120 has been filling the control line with zeros prior to the first record R1 reaching the first matrix MA. All of the matrices MA, MB, MC and MD are in the straight through position.
  • Figure 19B shows the situation at the next clock pulse.
  • the controller 120 has previously calculated the number of clock pulses required before the first record R1 reaches the end of a slow register SA, SB, SC or SD and has, at the appropriate moment, fed a "1" into the control register chain such that it reaches the control register, in this case the first control register CA, at the same time as the beginning of the first record R1 reaches the output of the corresponding slow register SA.
  • the controller 120 has been keeping track of all of the records by clock pulse counting as they shift along the chain 138, and feeding the records back into the beginning of the chain 138 as they fall out of the end of the chain 138 at the coupling 'port 14.
  • the controller 120 selects, as the slow register from which to access a particular record, that slow register, in this example the first slow register SA, the output of which the particular record, in this case the first record R1, will reach in the minimum number of clock pulses.
  • the controller 120 has, at the same time that it started sending the 1 into the control registers chain, started sending a serial bit representation of a replacement record R1' into the chain of fast registers such that the first bit of the replacement record R1' reaches the first fast register FA at the same instant that the 1 reaches the first control register CA and the beginning of the first record R1 reaches the output of the first slow register SA.
  • a succeeding record, R0 has begun to enter the first slow register SA.
  • All records R1, R2, R3, R4, R5, RO have moved up one bit place.
  • the controller 120 having positioned the first record R1 at the output of the first slow register SA, the 1 on the control register C1 and the first bit of the replacement record R1' on the first fast register F1, then applies a second global signal G2 which has the effect of latching a zero into all matrices save the first matrix MA, which, being in receipt of a latched 1, changes to the cross-over mode.
  • the first matrix MA sends the first record R1 into the second fast register FB and the output of the first fast register FA into the second slow register SB.
  • the first record R1 is thus sent, one bit for every successive clock pulse, into the fast chain, and thereon, at speed, to the coupling port 14, where it is extracted by the controller 120 for transmission to the host 122 if required, and the replacement record R1' is sent into the slow chain in place of the first record R1.
  • Figure 19C shows the situation N clock pulses after the commencement of access.
  • the controller 120 has counted clock pulses and, N-1 clock pulses after the commencement of the data exchange, that is, just after the last bit of the first record R1 has passed out of the first slow register SA, has issued another second global signal G2. Since the control chain is filled with zeros the first latch LA latches a zero to the first matrix MA which is thereby set back into the straight through mode. The last bit of record R1 is then in fast register FB, the next-to-last bit in fast register FC, etc.
  • the controller 120 uses the same technique when accessing any other record.
  • controller 120 by manipulating the start-of-record and the end-of-record global signal G2, in conjunction with appropriate bit patterns in the control register chain, may read in and out an indefinitely and selectably long string of data, being many records, portions of records, and even portions contained within a record.
  • Figure 20 shows how, by the addition of a data comparison facility between the fast and slow chains of figure 18, the memory is made both random access and content addressable.
  • global signal G2 is used, in conjunction with 1's on the control register chain, to set switches 50 to cross-over mode.
  • global signal G1 can be used to place all cells in content addressable mode (state 0") in which state suitable signals on the control line can be used to set switches to cross-over mode when appropriate.
  • Global signal G1 is used to return all cells to state 0' (random access) from state 0" when required.
  • Comparison gates 150X, 150Y compare the contents of the fast register 54X, 54Y with the first bit in the slow register 52X, 52Y.
  • the comparison gate 150X, 150Y gives a logically true signal at its output if there is a difference between its inputs.
  • the output of the comparison gate 150X, 150Y is coupled as a conditional reset input to a data selection flip-flop 152X, 152Y.
  • the data selection flip-flop 152X, 152Y is also responsive to the initiating signal from the state machine 58X, 58Y on the initiating coupling 156X, 156Y and the enabling signal from the state machine 58X, 58Y on the enabling coupling 154X, 154Y.
  • the flip-flop 152X, 152Y is set by the initiating signal from the state machine 58X, 58Y becoming logically true, and is reset whenever the enabling signal from the state machine 58X, 58Y is logically true and the comparison gate 150X, 150Y sees a data mismatch.
  • the flip-flop 152X, 152Y stays reset or set despite data mismatches if the enabling signal becomes false.
  • flip-flop 152 On entering the content-addressable state (after G1 signal) flip-flop 152 is reset and the state machine 58 is responsive to pairs of bits on the control line i.e. the bit currently in register 56 and the immediately following bit (seen as the input 56).
  • the state machine 58 is responsive to pairs of bits on the control line i.e. the bit currently in register 56 and the immediately following bit (seen as the input 56).
  • initiating line 156 is raised to set flip-flop 152 (and dropped on the following clock cycle) and enabling line 154 is also raised to enable data/key comparison to be made by gate 150.
  • a subsequent '10' bit pattern on the control line will reset the enabling line 154, disabling data comparisons so that mismatches have no effect on flip-flop 152.
  • Data comparison is again enabled by another '10' bit pattern, so providing a masking function.
  • a '11' bit pattern on the control line will cause the state machine 58 to set the matrix 50 to the cross-over mode if, and only if, the flip-flop 152 is set.
  • the timing of the '11' bit pattern by the controller 120 is such that the desired matched record, or part thereof, is correctly provided as output onto the fast line 54.
  • a subsequent '11' pattern returns all matrices 50 to straight-through mode and resets all flip-flops 152 ready for another comparison sequence.
  • the data records RA, RB, RC, RD as shown in Figure 20 are still one bit shorter than the slow registers 52X, 52Y.
  • the controller 120 runs a literal, a serial data word, which is to be matched against the data in the slow registers 52X, 52Y and so on, as a key match, into the fast line in synchronism with a mask sequence of pairs of 1s and Os into the control line. Whenever a 10 pair reaches the control register 56X, 56Y the data comparison is alternately enabled and disabled.
  • figure 20 shows the first bit of record RA entering slow register 52X, record RB occupying the remainder of slow register 52X, and slow register 52Y containing record RC and the last bit of record RD.
  • the literal, or key, to be matched against the data records is input to the fast registers, with its first bit in register 54X currently being compared with the first bit of record RA.
  • the control register 56X contains a '1' with the following bit (the input to 56X) being a '0', causing flip-flop 152X to be set by initiating signal 156X and enabled by line 154X. If the key and record comparison shows a match (logically false output from gate 150X) flip-flop 152X remains set.
  • the second bit of record RA enters slow register 52X and the first bit of record RB enters slow register 52Y.
  • the first bit of the comparison literal moves on to fast register 54Y and is compared with the first bit of record RB via gate 150Y.
  • Flip-flop 152Y is set and enabled by the '1' now in control register 56Y and the '0' in control register 56X. If there is a mismatch between the literal and RB, flip-flop 152Y will be reset, otherwise it will remain set.
  • the second bit of the literal in fast register 54X is compared with the second bit of record RA and flip-flop 152X either remains set if the bits match, or is reset by a mismatch.
  • the comparison process can be disabled at any time by the propagation of a '10' bit pair along the control line, and subsequently re-enabled by another '10' bit pair, allowing selected fields of the comparison literal to be masked.
  • the data records and the comparison literal continue to move along the slow and fast lines, respectively, with the result that the literal is compared bit-by-bit with each and every data record (subject to any required masking) in the time taken for the literal to completely traverse the length of the fast line.
  • the '11' bit pair propagates along the control line ready to set a matrix to cross-over mode wherever a data match is indicated and synchronised to the arrival of the first bit of the matched record at the end of the appropriate slow register. Assuming that record RA matched and is output, when the last bit of RA is transferred to the fast line another '11' bit pair on the control line resets all flip-flops 152 unconditionally, ready for another comparison and data output sequence.
  • the cells 12 need not necessarily be square.
  • the cells may be of any shape, which provides a tessellation and provided with coupling on every edge. It will also be apparent that the cells 12 may be adapted to comprise data processing elements of any kind.
  • many wafers 10 may be provided accessed together to provide a parallel data word memory. There can be more than one coupling port 14.
  • the wafer 10 may have coupling means provided at its edges.
  • the state machine 58 which normally receives power at all times, may have its power supply made conditional upon the raising of the signal on the command line 26, by an adjacent tester cell 130.
  • Many data chains 138 may be provided on one wafer 10 by growth from more than one port 14 or edge coupling means.
  • a wafer may be divided into several, mutually exclusive areas of cells 12, each area accessed from its own port 14.

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Claims (15)

1. Circuit intégré (10) comprenant un certain nombre de cellules (12, 16) pouvant être testées fonctionnellement (en utilisant 58, 72, 74, 76), chacune de ces différentes cellules (12, 16) étant couplée simultanément aux autres pour recevoir un signal de commande commun (36, 38), chacune de ces différentes cellules (12, 16) n'étant pas en train de recevoir un couplage fonctionnel (via 50), pouvant fonctionner, en réponse à une approche (via 26) par une cellule voisine (12, 16) pour accepter le couplage fonctionnel (via 50) avec celle-ci, et pour subir un test fonctionnel (surveillé par 72, 74, 76 et 58), ce couplage fonctionnel (via 50) étant confirmé (par 51) et maintenu si le test fonctionnel est passé avec succès (pas de signal en 64), mais ce couplage fonctionnel (via 50) étant supprimé (par suppression du signal en 26), si le test fonctionnel n'est pas passé avec succès (indiqué par un signal 64); dans lequel chaque cellule (12,16) recevant le couplage fonctionnel (via 50) et dont le couplage fonctionnel a été confirmé (via 51) peut fonctionner pour réaliser cette approche (via 26) avec une cellule voisine déterminée (12, 16), et dans lequel chaque cellule (12, 16) recevant déjà le couplage fonctionnel (via 50) fonctionne pour résister à cette approche (via 26) en n'acceptant pas le couplage fonctionnel (via 50) avec plus d'une seule cellule voisine (12,16) à la fois; circuit intégré caractérisé en ce que chaque celle (12, 16) recevant le couplage fonctionnel (via 50) et dont ce couplage fonctionnel (via 50) a été confirmé (par 51), peut fonctionner, simultanément avec toutes les autres cellules (12, 16) recevant le couplage fonctionnel (via 50) et dont ce couplage fonctionnel (via 50) a été confirmé, en réponse au signal de commande commun (36, 38), pour sélectionner une cellule voisine (12,16), et pour réaliser l'approche (via 26) avec cette cellule, et en ce que chaque cellule (12, 16) ne recevant pas le couplage fonctionnel (via 50) et ayant reçu l'approche (via 26), peut fonctionner simultanément avec toutes les autres cellules (12, 16) ne recevant pas le couplage fonctionnel (via 50) et ayant reçu l'approche (via 25), pour accepter le couplage fonctionnel (via 50) par la cellule voisine (12, 16) réalisant l'approche (via 26), et pour effectuer le test fonctionnel.
2. Circuit intégré selon la revendication 1, caractérisé en ce que chaque cellule (12, 16) recevant le couplage fonctionnel (via 50), dont le couplage fonctionnel a été confirmé (par 51) et réalisant l'approche (via 26), peut fonctionner, à chaque occasion d'offrir l'approche (en 26), pour choisir l'une des différentes cellules (12, 16) en butée avec celle-ci, chacune de ces cellules (12, 16) en butée avec celle-ci, se voyant offrir l'approche (via 26) à son tour.
3. Circuit intégré selon l'une quelconque des revendications 1 et 2, caractérisé en ce que chaque cellule (12, 16) recevant le couplage fonctionnel (via 50), dont le couplage fonctionnel a été confirmé (par 51) et offrant l'approche (via 26), réalise cette approche (via 26) dans la même direction que toutes les autres cellules (12, 16) recevant le couplage fonctionnel (via 50), dont le couplage fonctionnel a été confirmé (par 51) et offrant l'approche (via 26).
4. Circuit intégré selon l'une quelconque des revendications précédentes, caractérisé en ce qu'il comprend un orifice (14) destiné à fournir le signal de commande commun (36, 38) à toutes les différentes cellules (12, 16), et à fournir le couplage fonctionnel à au moins une cellule initiale (12).
5. Circuit intégré selon la revendication 2 ou selon l'une quelconque des revendications 3 et 4 dépendant de la revendication 2, caractérisé en ce que chacune des différentes cellules (12, 16) comprend un compteur de direction (86) initialisé dans un état prédéterminé (via 36, 38) au début du fonctionnement- du circuit intégré (10), et dont le comptage avance ensuite pas à pas (via 36, 38) à chaque occasion de réaliser l'approche (via 26) pour sélectionner une cellule voisine (12, 16) de manière à fournir l'approche à celle-ci.
6. Circuit intégré selon l'une quelconque des revendications précédentes, caractérisé en ce que les différentes cellules (12, 16) sont disposées suivant une mosaïque régulière sur un substrat de plaquette de semiconducteur (10).
7. Circuit intégré selon la revendication 6, caractérisé en ce que chacune des différentes cellules (12,16) est carrée et vient en butée avec un maximum quatre autres cellules des différentes cellules (12, 16).
8. Circuit intégré selon l'une quelconque des revendications 6 et 7, caractérisé en ce que chaque cellule (12, 16) des différentes cellules comprend un certain nombre de matrices de commutation (50) à raison d'une matrice de commutation (50) pour chaque cellule voisine (12,16) avec laquelle chaque cellule (12,16) vient en butée, une matrice de commutation (50) dans chaque cellule (12,16) associée à une cellule voisine déterminée (12, 16), pouvant fonctionner pour assurer le couplage fonctionnel avec cette cellule voisine déterminée (12, 16) en coopérant avec une matrice de commutation (50) placée dans la cellule voisine déterminée associée à chaque cellule (12, 16).
9. Circuit intégré selon la revendication 8, caractérisé en ce que chacune des différentes matrices de commutation (50) comprend un circuit de comparaison de données (74, 76, 72) pouvant fonctionner pour donner l'indication (64) que les caractères de données reçus par chacune des différentes matrices de commutation (50), ne sont pas identiques aux caractères de données fournis par chacune correspondante des différentes matrices de commutation (50).
10. Circuit intégré selon la revendication 8, ou selon la revendication 9 dépendant de la revendication 7, caractérisé en ce que chacune des différentes cellules (12, 16) vient en butée avec quatre cellules voisines (12,16), chacune de ces différentes cellules (12, 16) comprenant quatre éléments de traitement de données (52, 54, 56) montés chacun dans une position intermédiaire entre une paire correspondante, décalée en rotation, de matrices de commutation (50), et en ce qu'une matrice de commutation quelconque (50) dans chacune des différentes cellules (12, 16) peut fonctionner sélectivement soit pour recevoir les caractères de données d'un premier élément de traitement de données (52, 54, 56) et transmettre les caractères de données reçus de ce premier élément de traitement de données (52, 54, 56), à un second élément de traitement de données (52, 54, 56), soit pour faire passer les caractères de données provenant du premier élément de traitement de données (52, 54, 56), à travers une limite de cellules associées (NSEW), et fournir à ce second élément de traitement de données (52, 54, 56) les caractères de données reçus à travers cette limite associé (N, S, E, W).
11. Circuit intégré selon la revendication 10, caractérisé en ce que chacun des différents éléments de traitement de données (52, 54, 56) comprend un registre à décalage de stockage de données à plusieurs bits à entrée série et sortie série (52), un registre à accès parallèle associé (54) destiné à recevoir et à transférer les données au registre de stockage de données (52), et un registre de commande associé (56) destiné à maintenir un caractère de commande destiné à contrôler le transfert des données entre le registre de stockage de données (52) et le registre d'accus (54), cette logique de couplage comprenant un commutateur de traversée (50) pouvant fonctionner en réponse aux caractères contenus dans le registre de commande (56) pour effectuer le transfert entre le registre de stockage de données (52) et le registre d'accès (54).
12. Circuit intégré selon la revendication 11, caractérisé en ce que chacun des différents éléments de traitement de données (52, 54, 56) comprend, en outre, un circuit de commande de commutation de traversée (150, 152, 58) comprenant un verrou (152) et un comparateur de données (150), ce comparateur de données (150) comprenant, bit par bit, la sortie du registre de stockage de données (52) à la sortie du registre d'accès de données (54) et fournissant un signal de sortie indiquant une coïncidence à chaque fois que les sorties sont les mêmes, le verrou (152) pouvant être déclenché à chaque fois qu'un caractère prédéterminé se trouve dans le registre de commande (56), à chaque fois que le comparateur (150) fournit le signal de sortie indiquant une coïncidence, et à chaque fois qu'un second signal de commande commun est fourni (via 58) au verrou (152), le commutateur de traversée (50) pouvant fonctionner pour faire traverser les données entre le registre de stockage de données (52) et le registre d'accès (54) en réponse au déclenchement du verrou (152), ce verrou (152) étant remise à l'état initial et le commutateur de traversée (50)-étant couplé à chaque fois que le caractère prédéterminé se trouve dans le registre de commande (56) et à chaque fois que le comparateur (150) ne fournit pas d'indication d'une adaptation.
13. Circuit intégré selon la revendication 6 dépendant de la revendication 4, ou selon l'une quelconque des revendications 7 à 12 dépendant de la revendication 6, la revendication 6 dépendant de la revendication 4, caractérisé en ce que l'orifice (14) est obtenu par omission d'une cellule (12, 16) dans la mosaïque.
14. Circuit intégré selon l'une quelconque des précédentes revendications, caractérisé en ce que chacune des différentes cellules (12, 16) comprend un commutateur électrique (104) pouvant fonctionner, en réponse au fait que chacune des différentes cellules (12, 16) ne reçoit pas le couplage fonctionnel (via 50), pour couper l'alimentation électrique de puissance d'une partie de la cellule (12, 16).
15. Circuit intégré selon la revendication 14, dépendant de la revendication 10, caractérisé en ce que cette partie de la cellule (12, 16) comprend les éléments de traitement de données (52, 54, 56).
EP82900118A 1981-12-18 1981-12-18 Circuit integre a l'echelle de tranche formant un labyrinthe de branchements Expired EP0096027B1 (fr)

Priority Applications (1)

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DE8585104574T DE3177079D1 (en) 1981-12-18 1981-12-18 Memory element for a wafer scale integrated circuit

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PCT/GB1981/000278 WO1983002163A1 (fr) 1981-12-18 1981-12-18 Circuit integre a l'echelle de tranche formant un labyrinthe de branchements

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Application Number Title Priority Date Filing Date
EP19850104574 Division-Into EP0172311B1 (fr) 1981-12-18 1981-12-18 Elément de mémoire pour des circuits sous forme de pastille
EP19850104574 Division EP0172311B1 (fr) 1981-12-18 1981-12-18 Elément de mémoire pour des circuits sous forme de pastille

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EP0096027A1 EP0096027A1 (fr) 1983-12-21
EP0096027B1 true EP0096027B1 (fr) 1987-03-11

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EP (1) EP0096027B1 (fr)
JP (1) JPS58502123A (fr)
DE (1) DE3175980D1 (fr)
WO (1) WO1983002163A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2244826A (en) * 1990-06-08 1991-12-11 Anamartic Ltd Linking circuit modules

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0080834A2 (fr) * 1981-12-02 1983-06-08 BURROUGHS CORPORATION (a Delaware corporation) Circuit intégré branché en spirale de dimension d'un "wafer"
EP0172311A2 (fr) * 1981-12-18 1986-02-26 Unisys Corporation Elément de mémoire pour des circuits sous forme de pastille

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1377859A (en) * 1972-08-03 1974-12-18 Catt I Digital integrated circuits
US4055754A (en) * 1975-12-22 1977-10-25 Chesley Gilman D Memory device and method of testing the same
GB2006522B (en) * 1977-10-03 1982-01-27 Secretary Industry Brit Wafers having microelectronic circuit chips thereon

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0080834A2 (fr) * 1981-12-02 1983-06-08 BURROUGHS CORPORATION (a Delaware corporation) Circuit intégré branché en spirale de dimension d'un "wafer"
EP0172311A2 (fr) * 1981-12-18 1986-02-26 Unisys Corporation Elément de mémoire pour des circuits sous forme de pastille

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IEEE Journal of solid state circuits, vol. SC-13, no.3, June 1978, pages 339 - 344 *

Also Published As

Publication number Publication date
JPS58502123A (ja) 1983-12-08
EP0096027A1 (fr) 1983-12-21
DE3175980D1 (en) 1987-04-16
WO1983002163A1 (fr) 1983-06-23

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