GB2006522B - Wafers having microelectronic circuit chips thereon - Google Patents

Wafers having microelectronic circuit chips thereon

Info

Publication number
GB2006522B
GB2006522B GB7838588A GB7838588A GB2006522B GB 2006522 B GB2006522 B GB 2006522B GB 7838588 A GB7838588 A GB 7838588A GB 7838588 A GB7838588 A GB 7838588A GB 2006522 B GB2006522 B GB 2006522B
Authority
GB
United Kingdom
Prior art keywords
wafers
circuit chips
microelectronic circuit
microelectronic
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB7838588A
Other versions
GB2006522A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
UK Secretary of State for Industry
Original Assignee
UK Secretary of State for Industry
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by UK Secretary of State for Industry filed Critical UK Secretary of State for Industry
Priority to GB7838588A priority Critical patent/GB2006522B/en
Publication of GB2006522A publication Critical patent/GB2006522A/en
Application granted granted Critical
Publication of GB2006522B publication Critical patent/GB2006522B/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/22Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2884Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147Semiconductor insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386Geometry or layout of the interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118Masterslice integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
GB7838588A 1977-10-03 1978-09-28 Wafers having microelectronic circuit chips thereon Expired GB2006522B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB7838588A GB2006522B (en) 1977-10-03 1978-09-28 Wafers having microelectronic circuit chips thereon

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB4089677 1977-10-03
GB7838588A GB2006522B (en) 1977-10-03 1978-09-28 Wafers having microelectronic circuit chips thereon

Publications (2)

Publication Number Publication Date
GB2006522A GB2006522A (en) 1979-05-02
GB2006522B true GB2006522B (en) 1982-01-27

Family

ID=26264533

Family Applications (1)

Application Number Title Priority Date Filing Date
GB7838588A Expired GB2006522B (en) 1977-10-03 1978-09-28 Wafers having microelectronic circuit chips thereon

Country Status (1)

Country Link
GB (1) GB2006522B (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0028091B1 (en) * 1979-10-18 1983-05-11 Sperry Corporation Fault detection in integrated circuit chips and in circuit cards and systems including such chips
GB2083929B (en) * 1980-08-21 1984-03-07 Burroughs Corp Branched labyrinth wafer scale integrated circuit
WO1983002163A1 (en) * 1981-12-18 1983-06-23 Burroughs Corp Branched labyrinth wafer scale integrated circuit
FR2548443B2 (en) * 1983-06-30 1987-05-07 Telemecanique Electrique IMPROVEMENT TO ELECTRICAL SWITCHES USING AN INSULATING SCREEN WHICH SHEARS THE ARC APPEARING BETWEEN THE CONTACTS
US4703436A (en) * 1984-02-01 1987-10-27 Inova Microelectronics Corporation Wafer level integration technique
EP0436337A3 (en) * 1989-12-22 1992-02-26 Raytheon Company Technique for simplified testing of semiconductor circuits

Also Published As

Publication number Publication date
GB2006522A (en) 1979-05-02

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Legal Events

Date Code Title Description
PE20 Patent expired after termination of 20 years

Effective date: 19980927