EP0089248A2 - Dense mounting of semiconductor chip packages - Google Patents
Dense mounting of semiconductor chip packages Download PDFInfo
- Publication number
- EP0089248A2 EP0089248A2 EP83301503A EP83301503A EP0089248A2 EP 0089248 A2 EP0089248 A2 EP 0089248A2 EP 83301503 A EP83301503 A EP 83301503A EP 83301503 A EP83301503 A EP 83301503A EP 0089248 A2 EP0089248 A2 EP 0089248A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- base plate
- lead pins
- leadless
- packages
- soldered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09709—Staggered pads, lands or terminals; Parallel conductors in different planes
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10727—Leadless chip carrier [LCC], e.g. chip-modules for cards
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10742—Details of leads
- H05K2201/10886—Other details
- H05K2201/10946—Leads attached onto leadless component after manufacturing the component
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3405—Edge mounted components, e.g. terminals
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3447—Lead-in-hole components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/366—Assembling printed circuits with other printed circuits substantially perpendicularly to each other
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
Definitions
- the present invention relates to dense mounting of semiconductor chip packages.
- a module unit of semiconductor devices may be used in order to densely dispose semiconductor devices and in order to obtain a small-sized electronic apparatus.
- Such a module unit comprises a plurality of semiconductor integrated circuit chips and other electronic parts such as condensers mounted on a ceramic base plate, which base plate includes multilayer printed wiring patterns.
- the ceramic base plate can be mounted on a printed board so as to provide various electronic circuits.
- a leadless package (a leadless chip carrier) has been developed in order to dispose semiconductor packages in a small area.
- the leadless package has electrode films formed on its surface instead of lead terminals projecting from side surfaces of the package.
- a plurality of leadless packages are mounted on one main surface of a ceramic base plate, which is mounted on a printed board, so that each leadless package is connected to a circuit pattern formed on the printed board.
- the leadless packages are mounted only on one main surface of the ceramic base plate, from the view point of soldering. These semiconductor devices of the prior art do not use the full area of the ceramic base plate surface, and the printed board surface, as effectively as is made possible by embodiments of the present invention.
- a semiconductor device embodying the present invention comprises: a plurality of leadless packages, each of which comprises a semiconductor chip housed therein and a plurality of electrodes formed on a surface thereof; and a base plate for mounting said leadless packages, which base plate comprises conductor patterns formed on both of the two main surfaces thereof, to which patterns the electrodes of the leadless packages are soldered.
- FIG. 1 An embodiment of the present invention is illustrated in Figs. 1, lA, and lB.
- a ceramic base plate 5, leadless packages 6 and 6', condensers 7 and 7', and lead pins 8 and 8' are illustrated in the drawings.
- Wiring patterns (not shown) are printed on both of the two main surfaces of the ceramic base plate 5 so that electronic parts such as the leadless packages 6 and 6' can be attached thereto.
- the leadless packages 6 and 6' and the condensers 7 and 7' are mounted on both of the two main surfaces of the ceramic base plate 5. Therefore, the number of electronic parts mounted on the ceramic base plate is increased as compared with the prior art.
- Each of the leadless packages 6, 6' houses, for example, a memory IC chip.
- the condensers 7, 7' are used as by-pass condensers. If the memory capacity of the memory IC chip is 64 kbit, then a memory module of 64 kwords x 8 bit or 512 kwords x 1 bit can be constituted in accordance with the illustrated embodiment.
- the lead pins 8 and 8' are attached to each edge of both of the main surfaces of the base plate 5 and project therefrom in parallel with each other and in parallel with the main surface.
- the ceramic base plate 5 is disposed perpendicular to a printed board and is attached thereto.
- the lead pin 8 or the lead pin 8' or both may be cranked so as to form a shoulder 8a or 8a', as is shown in Fig. 2, for increasing the strength of and the stability of the lead pins when the lead pins are mounted on the printed board.
- Electrode pad patterns 10 and 11 are printed on upper and lower main surfaces (Fig. 6) of the ceramic base plate 5 where the leadless package 6 and the condenser 7 are to be mounted.
- Each leadless package 6 comprises a semiconductor chip (not shown) housed therein and a plurality of electrodes formed on the four side surfaces and lower surface thereof (Fig. 6).
- Each electrode pad pattern 10 corresponds to an electrode 6a of the leadless package 6.
- each electrode pad pattern 11 corresponds to an electrode 7a formed at each end of the condenser 7 (Fig. 6).
- Lead pins 8 to be attached to the ceramic base plate 5 are punched from a sheet of metal band so as to constitute a lead frame 9.
- the tip of each lead pin 8 is perpendicularly folded, as is illustrated in Fig. 4.
- the folded tip 15 is soldered to a pad pattern (not shown) printed on a lower side surface of the ceramic base plate 5 in Fig. 4.
- the melting point of the solder used for securing the lead frame to the ceramic base plate 5 is higher than that of the solder used for securing the leadless packages to the ceramic base plate 5 in a subsequent process.
- the length of the folded tip 15 is less than the thickness of the ceramic base plate 5.
- the lead frame 9 is cut along the dash-dot line in Fig. 3 after being soldered to the ceramic base plate 5 so as to form separated lead pins 8.
- Two lead frames 9a and 9b, the tip of each being folded in opposite directions, may be soldered to the ceramicjbase plate 5, as is illustrated in Fig. 5.
- the lead pins of the lead frames 9a and 9b are alternately disposed.
- a perspective view of this arrangement is illustrated in Fig. 6. Due to this arrangement, the stability of the ceramic base plate 5 is enhanced when the plate 5 is mounted on the printed board since the lead pins are disposed in two rows.
- solder paste is coated on the electrode pad patterns 10 and 11 on the upper and lower main surfaces of the ceramic base plate 5 by means of a printing method.
- leadless packages 6 and condensers 7 are mounted on the upper main surface of the ceramic base plate 5.
- the leadless packages 6 and the condensers 7 are adhered to the electrode pad patterns 10 and 11, respectively, with the soldering paste coated thereon.
- the ceramic base plate 5 is turned upside down and placed on an adequate support. Further leadless packages 6' and condensers 7' are mounted on the new upper surface of the ceramic base plate 5. Then the ceramic base plate 5 is heated in a furnace so that the leadless packages 6 and 6' and the condensers 7 and 7' are simultaneously soldered to both of the main surfaces of the ceramic base plate 5.
- another adhesive agent may be coated on a part of the ceramic base plate 5 corresponding to the center portion of each of the parts (the leadless packages and condensers) to be mounted thereon.
- the parts disposed on the upper and lower surface of the ceramic base plate 5 are securely adhered to the ceramic base plate 5 both before and during the heating process for soldering the parts.
- the lead pins 8 are secured to the side surface of the ceramic base plate 5 instead of being secured to the main surface thereof. Therefore, the entire area of each of the main surfaces of the ceramic base plate 5 is effectively used for mounting the parts, as compared with the embodiments of Figs. 1 and 2. Also, such an arrangement of the lead pins 8 ensures that during the process of printing the solder paste onto the electrode pad patterns 10 and 11, the mask for printing the solder paste closely contacts the ceramic base plate surface so that the printed solder paste precisely corresponds to the mask pattern, with the result that short-circuiting between the adjacent electrode pad patterns can definitely be avoided.
- the ceramic base plate 5 which mounts the leadless packages 6 and 6' on both of the main surfaces is mounted on a printed board 12 (Fig. 7A) in such a manner that a lead pin 8 is inserted into a through hole 13 of the printed circuit board 12 and is secured thereto with a solder 14.
- Fig. 7B is a plan view of the printed circuit board 12 on which semiconductor devices of the present invention are mounted. It is preferable to print an identifying number 15 and an index mark 16 on the upper surface of each base plate 5, so that erroneous mounting of the semiconductor device is avoided and each semiconductor device is easily distinguished.
- the distribution or location of the parts mounted on the ceramic base plate 5 is not limited to that illustrated in the drawings. Also, resistances or other electronic parts may be mounted on the ceramic base.
- the use of semiconductor devices embodying the present invention can enable electronic parts to be mounted with a desirably high packaging density, owing to the more efficient use of the mounting surfaces available.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
- The present invention relates to dense mounting of semiconductor chip packages.
- A module unit of semiconductor devices may be used in order to densely dispose semiconductor devices and in order to obtain a small-sized electronic apparatus. Such a module unit comprises a plurality of semiconductor integrated circuit chips and other electronic parts such as condensers mounted on a ceramic base plate, which base plate includes multilayer printed wiring patterns. The ceramic base plate can be mounted on a printed board so as to provide various electronic circuits.
- A leadless package (a leadless chip carrier) has been developed in order to dispose semiconductor packages in a small area. The leadless package has electrode films formed on its surface instead of lead terminals projecting from side surfaces of the package. A plurality of leadless packages are mounted on one main surface of a ceramic base plate, which is mounted on a printed board, so that each leadless package is connected to a circuit pattern formed on the printed board. These leadless packages are used especially when there is a need for dense mounting of semiconductor chip packages. Therefore, the surface of the ceramic base plate should be effectively used for mounting the leadless packages and also the surface of the printed board must be effectively used for mounting the ceramic base plate.
- In semiconductor devices comprising leadless packages according to the prior art, the leadless packages are mounted only on one main surface of the ceramic base plate, from the view point of soldering. These semiconductor devices of the prior art do not use the full area of the ceramic base plate surface, and the printed board surface, as effectively as is made possible by embodiments of the present invention.
- A semiconductor device embodying the present invention comprises: a plurality of leadless packages, each of which comprises a semiconductor chip housed therein and a plurality of electrodes formed on a surface thereof; and a base plate for mounting said leadless packages, which base plate comprises conductor patterns formed on both of the two main surfaces thereof, to which patterns the electrodes of the leadless packages are soldered.
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- Figure 1 is a plan view of a semiconductor device embodying the present invention;
- Figure 1A is a view seen in the direction of the arrow A in fig. 1;
- Figure 1B is a view seen in the direction of the arrow B in fig. 1;
- Figure 2 is a side view of another semiconductor device embodying the present invention and is similar to that of Fig. 1(A);
- Figure 3 is a plan view of part of a preferred embodiment of the present invention, explaining a process of producing the same;
- Figure 4 is a view seen in the direction of the arrow IV in Fig. 3;
- Figure 5 is a side view similar to Fig. 4, of another preferred embodiment of the present invention;
- Figure 6 is an exploded perspective view of the semiconductor device of Fig. 5 showing the assembling process thereof;
- Figure 7A is a sectional view of semiconductor devices embodying the present invention, the devices being secured to a printed board; and
- Figure 7B is a plan view of the semiconductor devices of Fig. 7A.
- Embodiments of the present invention are described hereinafter with reference to the drawings. An embodiment of the present invention is illustrated in Figs. 1, lA, and lB. A
ceramic base plate 5,leadless packages 6 and 6',condensers 7 and 7', andlead pins 8 and 8' are illustrated in the drawings. Wiring patterns (not shown) are printed on both of the two main surfaces of theceramic base plate 5 so that electronic parts such as theleadless packages 6 and 6' can be attached thereto. Also, theleadless packages 6 and 6' and thecondensers 7 and 7' are mounted on both of the two main surfaces of theceramic base plate 5. Therefore, the number of electronic parts mounted on the ceramic base plate is increased as compared with the prior art. Each of theleadless packages 6, 6' houses, for example, a memory IC chip. Thecondensers 7, 7' are used as by-pass condensers. If the memory capacity of the memory IC chip is 64 kbit, then a memory module of 64 kwords x 8 bit or 512 kwords x 1 bit can be constituted in accordance with the illustrated embodiment. - The
lead pins 8 and 8' are attached to each edge of both of the main surfaces of thebase plate 5 and project therefrom in parallel with each other and in parallel with the main surface. Theceramic base plate 5 is disposed perpendicular to a printed board and is attached thereto. - The
lead pin 8 or the lead pin 8' or both may be cranked so as to form ashoulder - Another embodiment of the present invention which is more preferable than the previously mentioned embodiments is described hereinafter with reference to Fig. 3 to 6. A plurality of green sheets of alumina, each of which has printed patterns thereon, are laminated and burned so as to constitute a multilayer
ceramic base plate 5.Electrode pad patterns ceramic base plate 5 where theleadless package 6 and thecondenser 7 are to be mounted. Eachleadless package 6 comprises a semiconductor chip (not shown) housed therein and a plurality of electrodes formed on the four side surfaces and lower surface thereof (Fig. 6). Eachelectrode pad pattern 10 corresponds to anelectrode 6a of theleadless package 6. Also, eachelectrode pad pattern 11 corresponds to anelectrode 7a formed at each end of the condenser 7 (Fig. 6).Lead pins 8 to be attached to theceramic base plate 5 are punched from a sheet of metal band so as to constitute alead frame 9. The tip of eachlead pin 8 is perpendicularly folded, as is illustrated in Fig. 4. The foldedtip 15 is soldered to a pad pattern (not shown) printed on a lower side surface of theceramic base plate 5 in Fig. 4. The melting point of the solder used for securing the lead frame to theceramic base plate 5 is higher than that of the solder used for securing the leadless packages to theceramic base plate 5 in a subsequent process. The length of the foldedtip 15 is less than the thickness of theceramic base plate 5. Thelead frame 9 is cut along the dash-dot line in Fig. 3 after being soldered to theceramic base plate 5 so as to formseparated lead pins 8. Twolead frames 9a and 9b, the tip of each being folded in opposite directions, may be soldered to theceramicjbase plate 5, as is illustrated in Fig. 5. In this arrangement, the lead pins of thelead frames 9a and 9b are alternately disposed. A perspective view of this arrangement is illustrated in Fig. 6. Due to this arrangement, the stability of theceramic base plate 5 is enhanced when theplate 5 is mounted on the printed board since the lead pins are disposed in two rows. After thelead pins 8 are attached to theceramic base plate 5, a solder paste is coated on theelectrode pad patterns ceramic base plate 5 by means of a printing method. After that,leadless packages 6 andcondensers 7 are mounted on the upper main surface of theceramic base plate 5. Theleadless packages 6 and thecondensers 7 are adhered to theelectrode pad patterns ceramic base plate 5 is turned upside down and placed on an adequate support. Further leadless packages 6' and condensers 7' are mounted on the new upper surface of theceramic base plate 5. Then theceramic base plate 5 is heated in a furnace so that theleadless packages 6 and 6' and thecondensers 7 and 7' are simultaneously soldered to both of the main surfaces of theceramic base plate 5. - In order to enhance the adhesiveness of the solder paste before it is heated, another adhesive agent may be coated on a part of the
ceramic base plate 5 corresponding to the center portion of each of the parts (the leadless packages and condensers) to be mounted thereon. Thereby, the parts disposed on the upper and lower surface of theceramic base plate 5 are securely adhered to theceramic base plate 5 both before and during the heating process for soldering the parts. - In the semiconductor device assembled in the above--mentioned manner, the
lead pins 8 are secured to the side surface of theceramic base plate 5 instead of being secured to the main surface thereof. Therefore, the entire area of each of the main surfaces of theceramic base plate 5 is effectively used for mounting the parts, as compared with the embodiments of Figs. 1 and 2. Also, such an arrangement of thelead pins 8 ensures that during the process of printing the solder paste onto theelectrode pad patterns - The
ceramic base plate 5 which mounts theleadless packages 6 and 6' on both of the main surfaces is mounted on a printed board 12 (Fig. 7A) in such a manner that alead pin 8 is inserted into athrough hole 13 of the printedcircuit board 12 and is secured thereto with asolder 14. - Fig. 7B is a plan view of the printed
circuit board 12 on which semiconductor devices of the present invention are mounted. It is preferable to print an identifyingnumber 15 and anindex mark 16 on the upper surface of eachbase plate 5, so that erroneous mounting of the semiconductor device is avoided and each semiconductor device is easily distinguished. - The distribution or location of the parts mounted on the
ceramic base plate 5 is not limited to that illustrated in the drawings. Also, resistances or other electronic parts may be mounted on the ceramic base. - As was indicated above, the use of semiconductor devices embodying the present invention can enable electronic parts to be mounted with a desirably high packaging density, owing to the more efficient use of the mounting surfaces available.
Claims (10)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57042254A JPS58159360A (en) | 1982-03-17 | 1982-03-17 | Semiconductor device |
JP42254/82 | 1982-03-17 |
Publications (3)
Publication Number | Publication Date |
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EP0089248A2 true EP0089248A2 (en) | 1983-09-21 |
EP0089248A3 EP0089248A3 (en) | 1985-12-18 |
EP0089248B1 EP0089248B1 (en) | 1989-05-31 |
Family
ID=12630883
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP83301503A Expired EP0089248B1 (en) | 1982-03-17 | 1983-03-17 | Dense mounting of semiconductor chip packages |
Country Status (5)
Country | Link |
---|---|
US (1) | US4682207A (en) |
EP (1) | EP0089248B1 (en) |
JP (1) | JPS58159360A (en) |
DE (1) | DE3380003D1 (en) |
IE (1) | IE54790B1 (en) |
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DE3430849A1 (en) * | 1984-08-22 | 1986-03-06 | Gerd 7742 St Georgen Kammerer | Method for the three-dimensional expansion of the electrical connection between the connecting contacts of large-scale integrated electronic components and the contact points of an electrical connecting device on a component carrier |
EP0287274A2 (en) * | 1987-04-14 | 1988-10-19 | Radstone Technology plc | Semiconductor hybrid device |
DE4023776A1 (en) * | 1989-08-17 | 1991-02-21 | Vaisala Oy | MULTILAYER CONVERTER WITH BONDED CONTACTS AND METHOD FOR CARRYING OUT THE BONDING |
EP0571092A2 (en) * | 1992-05-19 | 1993-11-24 | Sun Microsystems, Inc. | Single in-line memory module |
EP0605982A2 (en) * | 1992-12-28 | 1994-07-13 | AT&T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL INC. | Multi-chip module board |
EP3928352A4 (en) * | 2019-02-20 | 2022-11-23 | Micron Technology, INC. | Component inter-digitated vias and leads |
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US5280193A (en) * | 1992-05-04 | 1994-01-18 | Lin Paul T | Repairable semiconductor multi-package module having individualized package bodies on a PC board substrate |
US5340772A (en) * | 1992-07-17 | 1994-08-23 | Lsi Logic Corporation | Method of increasing the layout efficiency of dies on a wafer and increasing the ratio of I/O area to active area per die |
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US7468553B2 (en) | 2006-10-20 | 2008-12-23 | Entorian Technologies, Lp | Stackable micropackages and stacked modules |
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- 1983-03-17 EP EP83301503A patent/EP0089248B1/en not_active Expired
- 1983-03-18 IE IE584/83A patent/IE54790B1/en not_active IP Right Cessation
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Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3430849A1 (en) * | 1984-08-22 | 1986-03-06 | Gerd 7742 St Georgen Kammerer | Method for the three-dimensional expansion of the electrical connection between the connecting contacts of large-scale integrated electronic components and the contact points of an electrical connecting device on a component carrier |
EP0287274A2 (en) * | 1987-04-14 | 1988-10-19 | Radstone Technology plc | Semiconductor hybrid device |
EP0287274A3 (en) * | 1987-04-14 | 1989-09-20 | Radstone Technology plc | Semiconductor hybrid device |
DE4023776A1 (en) * | 1989-08-17 | 1991-02-21 | Vaisala Oy | MULTILAYER CONVERTER WITH BONDED CONTACTS AND METHOD FOR CARRYING OUT THE BONDING |
DE4023776C2 (en) * | 1989-08-17 | 2003-07-03 | Vaisala Oy Helsinki | Multilayer semiconductor structure, in particular transducers and methods for forming contact areas on semiconductor regions of such multilayer semiconductor structures |
EP0571092A2 (en) * | 1992-05-19 | 1993-11-24 | Sun Microsystems, Inc. | Single in-line memory module |
EP0571092A3 (en) * | 1992-05-19 | 1994-01-12 | Sun Microsystems, Inc. | Single in-line memory module |
US5465229A (en) * | 1992-05-19 | 1995-11-07 | Sun Microsystems, Inc. | Single in-line memory module |
US5532954A (en) * | 1992-05-19 | 1996-07-02 | Sun Microsystems, Inc. | Single in-line memory module |
EP0605982A2 (en) * | 1992-12-28 | 1994-07-13 | AT&T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL INC. | Multi-chip module board |
EP0605982A3 (en) * | 1992-12-28 | 1994-07-27 | Ncr Int Inc | Multi-chip module board. |
EP3928352A4 (en) * | 2019-02-20 | 2022-11-23 | Micron Technology, INC. | Component inter-digitated vias and leads |
Also Published As
Publication number | Publication date |
---|---|
JPS58159360A (en) | 1983-09-21 |
EP0089248A3 (en) | 1985-12-18 |
IE54790B1 (en) | 1990-02-14 |
EP0089248B1 (en) | 1989-05-31 |
IE830584L (en) | 1983-09-17 |
US4682207A (en) | 1987-07-21 |
DE3380003D1 (en) | 1989-07-06 |
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