Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
  • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
  • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L29/0843—Source or drain regions of field-effect devices
  • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate

Definitions

• This invention relates in general to MOS transistors and, more particularly, to diffused channel MOS power transistors having reduced on-state resistance.
• the device which appears to have the greatest potential in this regard is the diffused channel MOS transistor, especially when designed in the configuration having source and gate electrodes on the front surface and the drain electrode on the back surface.
• That power device can be modeled as a plurality of surface devices in parallel, each one in series with a resistive drift region between the surface drain region and the back surface drain electrode.
• the starting material in which the device is fabricated is the major determinant of the breakdown voltage of the device. As the resistivity of this material is increased, the breakdown voltage increases. But as the resistivity is increased, the resistance of the drift region is also increased. To keep the on-state resistance of the device a constant, as the resistivity is increased the cross-sectional area of the drift region must also be increased. This unfortunately increases the size of the die. The die size cannot be increased without limit, of course, as increased die sizes result in decreased yield and increased cost. Accordingly there existed a need for an improved MOS power transistor which would optimize both high voltage characteristic and current-carrying capability without increasing die size.
• the foregoing and other objects are achieved in the present invention through the use of a reduced resistance region formed at the surface of the device between adjacent source regions.
• the region is localized in extent, reduces a controlling resistance term, and has little influence on the breakdown voltage.
• the device current flows through this reduced resistance region, but the breakdown voltage is determined by bulk properties of the device.
• FIG. 1 illustrates in cross-section a portion of a power MOS transistor in accordance with the invention
• FIG. 2 illustrates in greater detail a portion of the power MOS transistor and the current flow through the device
• FIGS. 3-7 illustrate process steps for fabrication of the improved transistor.
• FIG. 1 illustrates in cross-section a portion of an MOS power transistor 10 in accordance with the invention.
• the transistor is fabricated on a heavily-doped n-type silicon wafer or substrate 12.
• An epitaxial layer 14 is grown overlying substrate 12.
• the epitaxial layer is also n-doped but has a lower doping concentration than does substrate 12.
• the thickness and doping of epitaxial layer 14 are selected to achieve the breakdown voltage design goal. For a 600 volt breakdown voltage, for example, the epitaxial layer is grown to a thickness of about 50 micrometers and has a resistivity of about 15 ohm-cm.
• Channel-forming regions 16 of p-type conductivity are formed at a surface of epitaxial layer 14.
• p-type region 16 Located within p-type region 16 is a more heavily doped p-type region 18 and heavily doped n-type regions 20.
• P-type region 16 and especially that portion as indicated at 22 forms the diffused channel of the MOS transistor.
• N-region 20 forms the source region of that transistor.
• Heavily doped region 18 facilitates the shorting together at the wafer surface of regions 16 and 20 and acts to turn off the parasitic NPN transistor formed by regions 20, 16, and 14, respectively, which would otherwise be in parallel with the MOS transistor formed.
• the shorting together of regions 20 and 16 is similar to the interconnection of source and substrate of a conventional MOS transistor.
• heavily doped region 18 may be considered as optional.
• a gate oxide layer 26 Overlying portions of the upper surface 24 of the semiconductor wafer is a gate oxide layer 26.
• that gate oxide layer is overlaid by a polycrystalline silicon gate electrode 28.
• a layer of aluminum or other interconnecting metal 32 contacts and electrically interconnects at the surface the source region 20 and shorting region 18. This interconnecting layer is electrically insulated from the gate electrode 28 by an oxide or other insulator layer 30.
• Contact is made to heavily doped wafer 12 by a metal contact layer 34.
• the drain region of the MOS transistor is formed by n-type layer 14; contact to the drain is made through wafer 12 and contact 34.
• An MOS transistor is thus formed at the surface of the wafer having source 20, channel 22, gate 28 and drain 14. In series with this MOS transistor is a resistive drift region through the remainder of layer 14 and a low resistance path through the heavily doped substrate 12 to drain electrode 34.
• the same configuration as is shown in FIG. 1 is iterated a number of times to effectively form a plurality of MOS transistors connected in parallel.
• the plurality of transistors have a common gate electrode 28, source electrode 32 and drain electrode 34.
• a potential is applied between drain and source electrodes to reverse bias the channel-drain junction 36.
• a positive potential is also applied between gate and source.
• the channel region 22 is inverted to form an inverted n-type channel 23 through which current flows from drain to source (electrons of course flow from source to the more positive drain).
• the positive potential applied to the gate electrode also accumulates the surface of n-region 14 to form a thin, highly conductive layer 15. This accumulated layer, together with inverted channel 23 effectively forms a continuous, highly conductive layer extending between adjacent source regions 20.
• FIG. 2 illustrates the current flow near the surface in more detail. Current flows as indicated by the arrows 38 from the drain contact (not shown in this view) vertically through the substrate 12 and epitaxial layer 14 and then transversely through the accumulated layer 15 and the inverted channel 23 to the sources 20.
• the resistance of the device would be determined by the resistivity of the material 14 and by the cross-sectional area of that material.
• the cross-sectional area is determined by the location of adjacent regions 16.
• the cross sectional area of this drift region cannot be made arbitrarily large to reduce the on-resistance of the device.
• a wide spacing between regions 16 lowers the on-resistance, but only at the expense of an increased die size.
• Increasing the die size increases the probability of a catastrophic defect and generally increases the die cost.
• the resistivity must be greater than some minimum value in order to insure the necessary desired breakdown voltage for the device.
• a further increase in the on-resistance occurs when the bias between source and drain is increased.
• the bias between source and drain causes the formation of a depletion region on either side of junction 36.
• Line 42 demarks the edge of the depletion region on the n side of p-n junction 36 for a given potential.
• the shape of the depletion region in the vicinity of surface 24 is complicated and not well understood and therefore has not been depicted in the Figure.
• An increase in bias between source and drain causes the edge of the depletion region 42 to spread further into the epitaxial layer 14.
• the two depletion regions from adjacent p-n junctions 36 encroach upon the current carrying path through layer 14 and decrease the cross-sectional area available for current conduction.
• This effect is not unlike the pinch-off of the conducting channel in a JFET. This effect is more noticeable in the lightly doped material used to achieve a high breakdown voltage. Again, while the effect can be minimized by increasing the spacing between adjacent p-regions 16, such a solution increases the die size.
• the breakdown voltage can be maintained and the on-state resistance lowered by increasing the doping in a localized region 44 as shown in FIGS. 1 and 2 located near the surface of the device between adjacent p-type regions 16.
• This region of lowered resistivity is achieved by selectively doping the surface of the wafer to a depth no greater than about the depth of the p-region 16.
• this heavily doped area reduces the resistance of that portion of the device most effected by the pinch-off effect of the depletion spread from junction 36.
• this more heavily doped region does not adversely affect the breakdown voltage of the device.
• FIGS. 3-7 illustrate a sequence of process steps by which a device in accordance with the invention can be fabricated. As illustrated in FIG. 3, the process sequence starts with a heavily doped n-type substrate 12 upon which is grown a more lightly doped n-type epitaxial layer 14.
• An insulating layer 50 is grown or deposited over the upper surface of epitaxial layer 14.
• the insulating layer is patterned to form a plurality of apertures 52.
• P-type dopant is diffused through these apertures using the remaining oxide layer 50 as a diffusion mask.
• the heavily doped p-type regions 54 formed by diffusion through the apertures 52 facilitate the shorting together of source and the external portion of the channel.
• an oxidation step regrows oxide 51 in the apertures 52. As illustrated in FIG. 4 the remainder of oxide 50 and the regrown oxide 51 are patterned and the oxide selectively removed. Oxide is left over the diffused regions 54 and around the periphery of the chip as indicated at 56.
• a thin gate oxide 58 is then grown on the exposed portion of epitaxial layer 14.
• n-type dopant such as phosphorus is ion implanted through the gate oxide and into the surface of epitaxial layer 14.
• the ion implant energy is chosen so that the implant passes through the gate oxide 58 but not through the thicker field oxide 51, 56.
• the implant forms a shallow doped region 60 which will subsequently be redistributed to form the doped region 44.
• the gate oxidation and ion implant steps can, of course, be interchanged and obtain the same result.
• the implant is blocked by the oxide 56 from the peripheral region of the chip to insure that the high breakdown voltage of the device is maintained.
• the plurality of p-type regions 16 in FIG. 1 effectively forms a single p-n junction with the n-type epitaxial layer. It is in the peripheral region that the depletion spread from this p-n junction terminates.
• the resistivity in the epitaxial layer must be kept high in this region.
• a layer of polycrystalline silicon is next deposited over the upper surface of the device.
• the polycrystalline silicon is patterned to form gate electrodes 62 as illustrated in FIG. 5.
• the patterned polycrystalline silicon is used as an ion implant mask; boron ions are implanted through the exposed gate oxide and into the surface of epitaxial layer 14 to form p-doped regions 64.
• the device is subjected to a high temperature thermal redistribution which establishes the junctions as illustrated in FIG. 6.
• Ion implant 64 upon redistribution, forms channel region 16.
• the dose of ion implant 64 is heavy enough to compensate and overdope ion implant 60.
• the dose and subsequent redistribution of ion implant 64 are further selected so that the surface concentration at the surface of epitaxial layer 14, especially in that portion of region 16 which diffuses sideways and extends under gate electrode 62, provides the desired threshold voltage value for the device.
• the dose of ion implant 60 and the Subsequent redistribution are selected to provide the desired lower resistance of the current carrying path through region 44 without adversely affecting the breakdown voltage of the device.
• the final doping distribution in region 44 preferably provides a surface concentration having an equivalent resistivity of about 0.5 ohm-cm.
• the doping decreases in a direction away from the surface to an equivalent resistivity of about 5 ohm-cm or more at a depth of about equal to the junction depth of region 16.
• Regions 16 and 44 preferably have junction depths of about 4 micrometers. After redistribution and considering the overcompenation by ion implant 64, region 44 is localized to areas between adjacent channel region 16. Region 44 is not located at the chip edge under protective oxide 56. That portion of gate oxide 58 which is not covered by polycrystalline silicon is then removed using the polycrystalline silicon as an etch mask as illustrated in FIG. 7.
• Source regions 20 are diffused into portions of the surface exposed after the gate oxide is selectively removed. Source regions 20 are diffused into channel region 16 and extend laterally underneath the polycrystalline gate electrode 62.
• the polycrystalline silicon gate electrode is doped n-type simultaneously with the diffusion of source region 20.
• An oxide or other insulator layer is grown or deposited over the exposed source and gate regions.
• devices are fabricated as illustrated above.
• the device is fabricated with an epitaxial layer about 50 micrometers in thickness and having a resistivity of 15 ohm-cm.
• the device has a gate electrode width of 0.4 micrometers; the gate electrode width determines the spacing between adjacent channels.
• the total device is 4 mm on a side. With that total device size and gate electrode width as constraints, the device is optimized by maximizing channel width since total current carrying capability is proportional to channel width divided by channel length.
• Finished devices exhibit a breakdown voltage in excess of 500 volts.
• the on-state resistance of the device with 5 volts applied between source and drain and the gate at 10 volts above threshold is 2 ohms.
• a geometrically identical device fabricated without the resistance lowering diffusion 44 has a breakdown voltage of 500 volts and an on-state resistance under identical conditions of 3 ohms.
• ion implantation and conventional thermal diffusion can be selectively interchanged, insulators other than silicon dioxide can be employed, and the device can be fabricated as a p-channel rather than n-channel device. Accordingly, it is intended to embrace all such variations and modifications as fall within the scope of the invention.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Ceramic Engineering (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)

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• 1982
  • 1982-02-22 IT IT47840/82A patent/IT1154298B/it active
  • 1982-02-22 WO PCT/US1982/000217 patent/WO1982002981A1/en unknown
  • 1982-02-22 EP EP82901076A patent/EP0077337A1/de not_active Withdrawn

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