EP0070603A1 - Circuit de synchronisation pour un récepteur de télévision - Google Patents

Circuit de synchronisation pour un récepteur de télévision Download PDF

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Publication number
EP0070603A1
EP0070603A1 EP82200901A EP82200901A EP0070603A1 EP 0070603 A1 EP0070603 A1 EP 0070603A1 EP 82200901 A EP82200901 A EP 82200901A EP 82200901 A EP82200901 A EP 82200901A EP 0070603 A1 EP0070603 A1 EP 0070603A1
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EP
European Patent Office
Prior art keywords
line
frequency
signal
circuit
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP82200901A
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German (de)
English (en)
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EP0070603B1 (fr
Inventor
Anthonius Hendrikus H. J. Nillesen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Philips Gloeilampenfabrieken NV, Koninklijke Philips Electronics NV filed Critical Philips Gloeilampenfabrieken NV
Publication of EP0070603A1 publication Critical patent/EP0070603A1/fr
Application granted granted Critical
Publication of EP0070603B1 publication Critical patent/EP0070603B1/fr
Expired legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/12—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/44—Colour synchronisation

Definitions

  • the invention relates to a synchronizing circuit arrangement for a television receiver, comprising a symchronizing-separating stage for deriving line and field synchronizing pulses from a received television signal, an oscillator for generating by means of a crystal a periodical clock signal the frequency of which is substantially higher than the line frequency, a frequency divider circuit connected to the oscillator for deriving a signal of the line frequency by dividing the clock frequency by a divisor and a phase comparison stage for determining the phase deviation between the received line synchronizing pulses and a locally generated reference signal of the line frequency.
  • Such a circuit arrangement is known from the publication "IEEE Transactions on Consumer Electronics", Vol. CE-24, No.3, pages 284 to 290, inclusive, published in August 1978.
  • the clock frequency is nominally 32 times the line frequency.
  • the crystal oscillator is a voltage-controlled oscillator which is continuously readjusted by the output voltage of the phase comparison stage which determines the phase deviation between the line synchronizing pulses and the line flyback pulses originating from a line output stage.
  • the frequency of the oscillator output signal is divided, on the one hand by a constant divisor, namely 32, in order to obtain the drive signal for the (horizontal) line deflection and on the other hand by a second divisor to obtain the drive signal for the (vertical) field deflection, which second divisor depends on the state of the loop for the field synchronization and is continuously readjusted.
  • a constant divisor namely 32
  • a second divisor to obtain the drive signal for the (vertical) field deflection
  • the invention has for its object to provide a synchronizing circuit arrangement of the above-mentioned type, wherein the generated line frequency is not changed immediately on detection of a phase error, and for that purpose the synchronizing circuit arrangement in accordance with the invention is characterized in that the phase comparison stage is implemented for establishing during a predetermined number of line periods the average value of the phase deviation between the input signals applied to it and for supplying the value obtained to a preset stage for adjusting in a time interval subsequent thereto the divisor by which the frequency dividing circuit divides the clock frequency.
  • the invention is based on the recognition of the fact that if the chosen number of line periods.for which the averagephase variation is established is large enough, the average value obtained for a larger number of line periods will hardly deviate therefrom as the phase deviations caused by noise and interferences have an average value which isusually substantially equal to zero.
  • the frequency of the clock oscillator is not controlled but, after an average phase error has been detected, the divisor is changed in one single operation.
  • the circuit arrangement in accordance with the invention may be characterized in that the adjustment of the divisor is effected by changing the duration of a line period.
  • the invention is characterized in that the time interval in which adjustment of the divisor is effected is one line period during the field blanking interval.
  • the phase comparison stage includes a counter for counting clock periods between the instant of occurrence of a line synchronizing pulse and the instant of occurrence of a reference pulse, and that the counter is an up-down counter which is enabled by one of the pulses applied to the phase comparison stage.
  • the circuit arrangement in accordance with the invention may be characterized in that in the event of a phase deviation between the input signals applied to the phase comparison stage, exceeding a predetermined maximum value, the phase comparison stage applies this maximum value to the preset stage during the next line period. This reduces the pull-in period considerably in the event of a large phase deviation.
  • the synchronizing circuit arrangement in accordance with the invention is used in a colour television receiver which receiver comprises a colour killer circuit which operative when insufficient colour synchronizing signal is received then it may advantageously be characterized in that the frequency of the clock signal is a multiple of the colour subcarrier frequency in the colour television standard for which the receiver is suitable.
  • the circuit arrangement may be characterized by a change-over switch which is controlled by the colour killer circuit, and by a second phase comparison stage for establishing the phase deviation between the received line synchronizing signal and a signal derived from the clock signal by means of division and for continuously controlling the oscillator when the colour killer circuit is operative, and also by a change-over switch controlled by the colour killer circuit, the phase comparison stage continuously readjusting the oscillator as a function of the phase deviation established in each line period when the colour killer circuit is operative, the preset stage having then no influence on the divisor by which the frequency divisor circuit divides the clock frequency.
  • reference numeral 1 denotes the input terminal of the circuit arrangement.
  • a video signal which is received and processed in known manner, is present on this input terminal.
  • Said signal comprises video information which, in stages not shown, is further processed for use in a picture tube, and a composite synchronizing signal.
  • the signal on terminal 1 is applied to a synchronizing-separating stage 2 at the output of which the said synchronizing signal is available, and to an anabg- to-digital converter 3.
  • the resultant digital video signal is applied to a processing stage 4 which applies a digital colour synchronizing signal to a phase detector 5.
  • the output signal thereof is smoothed by means of a low-pass filter 6. Via a selection switch 7, the smoothed signal is applied to a quartz crystal-stabilized oscillator 8 for readjusting the frequency and/or the phase thereof.
  • Oscillator 8 generates the sampling signal for the video signal and is applied for that purpose to converter 3.
  • the value 17.72 MHz i. e. four times the colour subcarrier frequency fsc, which is approximately equal to 4.43 MHz (PAL-standard) is taken as the frequency of said signal.
  • the frequency of the signal generated by oscillator 8 is divided by four by means of a frequency dividing circuit 17 and the resultant signal is applied to phase detector 5, in which the phase difference between the two input signals thereof is converted into a voltage which controls oscillator 8.
  • the signal received from circuit 17 gets substantially the-same frequency and phase as the subcarrier with the aid of the control loop formed by the elements 5, 6, 8 and 17 and may consequently be applied to chrominance demodulators, not shown, for generating colour signals.
  • the sampling signal generated by oscillator 8 may be used in different places in the television receiver of which the circuit of Figure 1 is part.
  • the phase of said sampling signal is locked to the colour synchronizing signal and consequently to the line and field synchronizing signals supplied by the transmitter, it can be used to control comb filters with digital delay lines for separating the chrominance signal from the video signal and also for noise reduction circuits.
  • a condition to be satisfied is that the phase deviation between the transmitter line signal and a locally generated line signal does substantially not vary during a field period, not even in the event of a poor signal-to-noise ratio, and preferably that this variation also does not occur between consecutive fields.
  • the phase is kept substantially constant by means of the circuit shown in Fig.
  • the signal generated by oscillator 8 is applied as a clock signal to a counter 9 which derives therefrom in known manner a signal of the line frequency in accordance with the formula for the PAL-subcarrier wave frequency f SC : wherein f H is the line frequency.
  • the resultant signal of the line frequency is inter alia used as a drive signal for a line deflection circuit H, not shown, for deflecting in the horizontal direction the electron beam(s) generated in the picture tube.
  • PAL-counter 9 applies a signal of twice the line frequency 2 f H to a line counter 11.
  • the field synchronizing signal is derived from the composite synchronizing signal from stage 2 by means of a field synchronizing-separating stage 12.
  • the resultant signal is applied to line counter 11.
  • Counter 11 derives a signal f V of the field frequency from the signal 2 f H , which signal of the field frequency is used inter alia as a control signal for a field deflection circuit V, not shown, for deflecting the electron beam(s) in the vertical direction.
  • said signal f V has the proper phase because of the fact that counter 11 comprises means for determining and correcting, in known manner, the phase of the signal generated thereby.
  • the circuit of Fig. 1 comprises a phase counter 13 and a preset stage 14.
  • Phase counter 13 is supplied with the line synchronizing signal produced by stage 2 and the/clock signal generated by oscillator 8, or a signal derived therefrom, for example the signal supplied by circuit 17, and is enabled by the signal of the line frequency produced by PAL-counter 9.
  • counter 13 which is an up-down counter, counts up the number of clock pulses occurring between the starting moment of an enabling pulse and an edge of the line synchronizing signal and thereafter the number of clock pulses which occur between the said edge and the final instant of the enabling pulse is counted.down.So the counting imposition after the enable interval is for a determined line period a measure of the phase deviation between the signal produced by PAL-counter 9 and the received line synchronizing signal. The resultant counting position is stored until the occurrence of the next enabling pulse, at the occurrence whereof the counting operation is continued. After a given number of line periods the counting position of counter 13 is a measure of the sum of the phase deviations which occurred during said line periods. By dividing this counting position by the/humber of lines a number is obtained which corresponds to the average value of the phase deviation during these lines.
  • the sign and the value of the phase deviation between a line synchronizing pulse and a locally generated reference pulse of the line frequency cannot be predicted with certainty for a given line period.
  • the average value of the phase deviation caused by noise and interferences usually becomes substantially zero.
  • This number of line periods must then be sufficiently large to ensure that the average value obtained for a larger number of line periods does not deviate to an appreciable extent from the first-mentioned value. So if the average value of the phase deviation over such a large number of line periods is determined, then a value is obtained which depends with a fairly large degree of certainty on the mutual phase position of the two signals of the line frequency applied to counter 13.
  • Half of thearerage value obtained is applied to preset stage 14 by phase counter 13.
  • this information is converted into information which is ..usable for PAL-counter 9, so that counter 9 gets an initial value.
  • the duration of one period i.e. approximately 64 / us of the signal of the line frequency supplied by counter 9 is prolonged or reduced by, for example, not more than 2 / us. If the phase error measured, expressed in units of time, is less than 2 / us, then this correction which occurs only once is sufficient to obtain the proper phase for the signal supplied by counter 9. This can be verified by means of Fig. 2.
  • a represents an enabling pulse supplied by counter 9 for phase counter 13, while b represents a line synchronizing pulse applied Thereto.
  • clock periods are counted- up hetween the leading edges of pulses a and b and n clock periods are counted down between the leading edge of signal b and the trailing edge of signal a.
  • counter 13 has counted down a total of n-m. If The edge of pulse b is produced in the middle of pulse a, Then the counting position for this line is zero. From Fig.2 it appears that the phase deviation of signal b with respect to this middle instant can be corrected for by shifting the leading edge of signal b to the right by n-m 2 clock periods, that is half the counting position obtained for this line.
  • phase difference between the incoming signal and the reference signal is zero. Only very serious interference occurring in a subsequent measuring interval is capable of producing a phase difference which differs from zero, resulting in a phase error for the duration of the measuring interval following thereafter. It will be obvious that said error will be very small if the duration of the measuring interval is rather long. However, too long a duration has the disadvantage that the phase error becomes visible before the correction is realized. It has been found that a measuring interval to the length of one field period is a good compromise, which has the additional advantage that The correction may then occur during a line period of the field blanking interval following thereafter, that is to say the correction is invisible. In this manner the phase will be incorrect for not more than one field period, i.e. 20 ms for the European standard. Preset stage 14 and counter 13 are also supplied with the signal of the field frequency supplied by counter 11 and stage 14 passes the required correction on to counter 9 during a determined line period of the field blanking interval.
  • the measuring interval has a duration of one field period, i.e. approximately 312 line periods. It has been found that 256 is large enough, that is to say that the average value obtained after 256 line periods would change very little between the 256 th and the 312th period. 256 has the advantage that the division thereby can be effected with digital means in a simple manner, namely by shifting the counting position of counter 13 over 8 bit positions, while a division by 2 is obtained by one further shift.
  • Fig. 1 the signal produced by counter 9 is used as a reference signal for the phase comparison by means of the phase counter 13. It will be obvious that alternatively line flyback pulses present in the line deflection circuit may be used for this purpose. Also in the case of Fig. 1 a second correction loop may be arranged in known manner between line counter 11 and the line deflection circuit, in which loop the line flyback signal is again used as a reference signal. In both cases outlined above the influence of turn-off periods of unequal durations of a switch in thesaid circuit is substantially eliminated.
  • the circuit arrangement of Fig. 1 will still be capable of generating a line signal which is usable. If sach a television signal which may, for example, be received from a television game circuit, then during one field period the phase of the reference signal continuously shifts with respect to the received signal, the reason being that PAL-counter 9 then uses an incorrect divisor.
  • the horizontal lines are shown somewhat shifted with respect to the first lines which are substantially free of phase error because of the correction occurring before the beginning of the field. So the picture is displayed obliquely, either to the left or to the right.
  • an error of not more than 2 / us can be corrected by one non-recurrent correction.
  • the correction will last for a maximum of 16 fields, which is very long. This can be avoided when the phase deviation is not only measured during the "window? a of Fig. 2 but during the entire line period.
  • a different possibility is that after counter 13 has detected an error which exceeds a predetermined value, for example 2 / us, the setting value of PAL-counter 9 is not corrected after one field, but is corrected continuously, that is to say each line, by 2 / us. In these circumstances pull-in has a duration of not more than 16 line periods, whereafter the measured error is less than 2 / us, so that averaging the error is effected, as in the faregoing, over 256 line periods.
  • the oscillator 8 cannot be readjusted in the above-described manner.
  • a colour killing circuit 18 connected to the output of processing stage 4 is made operative in known manner for cutting-off the chrominance portion of the receiver.
  • the signal supplied by circuit 18 is also applied to selection switch 7 and to preset stage 14.
  • the uutput signal of phase counter 13 is converted into a voltage which for every line is a measure of the phase deviation detected by counter 13.
  • counter 9 keeps dividing the frequency of oscillator 8 in accordance with the PAL-formula, the sampling frequency remains coupled to the incoming line signal in the desired manner, so that the digital delay lines used in the chrominance portion for noise reduction realize the proper time delays.
  • phase deviation for example, can be determined by means of an integrator, while the phase deviation itself can be measured with a phase discriminator of a known type.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Synchronizing For Television (AREA)
  • Processing Of Color Television Signals (AREA)
EP82200901A 1981-07-21 1982-07-15 Circuit de synchronisation pour un récepteur de télévision Expired EP0070603B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL8103437A NL8103437A (nl) 1981-07-21 1981-07-21 Synchroniseerschakeling voor een televisie-ontvanger.
NL8103437 1981-07-21

Publications (2)

Publication Number Publication Date
EP0070603A1 true EP0070603A1 (fr) 1983-01-26
EP0070603B1 EP0070603B1 (fr) 1984-11-21

Family

ID=19837818

Family Applications (1)

Application Number Title Priority Date Filing Date
EP82200901A Expired EP0070603B1 (fr) 1981-07-21 1982-07-15 Circuit de synchronisation pour un récepteur de télévision

Country Status (9)

Country Link
US (1) US4488170A (fr)
EP (1) EP0070603B1 (fr)
JP (1) JPS5825773A (fr)
KR (1) KR890000979B1 (fr)
AU (1) AU550803B2 (fr)
BR (1) BR8204182A (fr)
DE (1) DE3261293D1 (fr)
HK (1) HK27386A (fr)
NL (1) NL8103437A (fr)

Cited By (2)

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Publication number Priority date Publication date Assignee Title
FR2685584A1 (fr) * 1991-12-18 1993-06-25 Philips Electronics Nv Dispositif generateur de signal de synchronisation.
WO1994001965A1 (fr) * 1992-07-03 1994-01-20 British Broadcasting Corporation Generateur de signaux de synchronisation

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US4885638A (en) * 1982-03-31 1989-12-05 Ampex Corporation Video device synchronization system
NL8302984A (nl) * 1983-08-26 1985-03-18 Philips Nv Beeldweergeefinrichting met een ruisdetektor.
US5122864A (en) * 1984-07-11 1992-06-16 Canon Kabushiki Kaisha Video signal processing apparatus
DE3471567D1 (en) * 1984-11-02 1988-06-30 Itt Ind Gmbh Deutsche Colour television receiver comprising at least one integrated circuit for processing the composite digital colour signal
US4679005A (en) * 1985-01-23 1987-07-07 Sony Corporation Phase locked loop with frequency offset
US4964162A (en) * 1985-09-09 1990-10-16 Trw Inc. Secure television signal encoding and decoding system
US4694326A (en) * 1986-03-28 1987-09-15 Rca Corporation Digital phase locked loop stabilization circuitry including a secondary digital phase locked loop which may be locked at an indeterminate frequency
US4694327A (en) * 1986-03-28 1987-09-15 Rca Corporation Digital phase locked loop stabilization circuitry using a secondary digital phase locked loop
US4686560A (en) * 1986-05-30 1987-08-11 Rca Corporation Phase locked loop system including analog and digital components
JPH0787596B2 (ja) * 1986-06-20 1995-09-20 株式会社日立製作所 信号処理回路
US4700217A (en) * 1986-08-05 1987-10-13 Rca Corporation Chrominance signal phase locked loop system for use in a digital television receiver having a line-locked clock signal
US4802009A (en) * 1987-07-13 1989-01-31 Rca Licensing Corporation Digitally controlled phase locked loop system
DE68915228T2 (de) * 1988-09-02 1994-12-15 Sanyo Electric Co Phasensynchronisierschaltung in einem Videosignalempfänger und Verfahren zur Herstellung der Phasensynchronisation.
US5062005A (en) * 1989-02-01 1991-10-29 Matsushita Electric Industrial Co., Ltd. Videodisc reproducing apparatus
US5341217A (en) * 1990-03-06 1994-08-23 Martin Marietta Corporation Digital adaptive video synchronizer
US5162910A (en) * 1990-10-03 1992-11-10 Thomson Consumer Electronics, Inc. Synchronizing circuit
US6469741B2 (en) 1993-07-26 2002-10-22 Pixel Instruments Corp. Apparatus and method for processing television signals
JPH0795142A (ja) * 1993-09-20 1995-04-07 Fujitsu Ltd スター型ネットワーク用親局端局装置
US5742191A (en) * 1993-12-08 1998-04-21 Thomson Consumer Electronics, Inc. D/A for controlling an oscillator in a phase locked loop
JP3200658B2 (ja) * 1993-12-10 2001-08-20 三菱電機株式会社 映像信号処理装置及び映像信号記録・再生装置
US5844622A (en) * 1995-12-12 1998-12-01 Trw Inc. Digital video horizontal synchronization pulse detector and processor
US5786866A (en) * 1996-10-15 1998-07-28 Fairchild Semiconductor Corporation Video color subcarrier signal generator
US5796392A (en) 1997-02-24 1998-08-18 Paradise Electronics, Inc. Method and apparatus for clock recovery in a digital display unit
US6380980B1 (en) * 1997-08-25 2002-04-30 Intel Corporation Method and apparatus for recovering video color subcarrier signal
DE19816656C2 (de) * 1998-04-15 2000-08-10 Suedwestrundfunk Anstalt Des O Verfahren zum Erzeugen von Frequenzen
US6028642A (en) * 1998-06-02 2000-02-22 Ati Technologies, Inc. Digital horizontal synchronization pulse phase detector circuit and method

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DE2517046B1 (de) * 1975-04-17 1976-09-16 Siemens Ag Fernsehimpulsgeber
FR2391620A1 (fr) * 1977-05-18 1978-12-15 Sony Corp Generateur de signaux de sy
US4203135A (en) * 1977-01-27 1980-05-13 Sanyo Electric Co., Ltd. External synchronizing signal generating circuit for a color television camera

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NL163694C (nl) * 1972-11-24 1980-09-15 Philips Nv Schakeling voor het opwekken van een stuursignaal voor de rasteruitgangstrap in een televisie-ontvanger, alsmede televisie-ontvanger, daarvan voorzien.
JPS52120615A (en) * 1976-04-03 1977-10-11 Sony Corp Reproduction reference signal generator circuit
US4025951A (en) * 1976-06-09 1977-05-24 Gte Sylvania Incorporated Vertical synchronizing circuit having adjustable sync pulse window
JPS5322351A (en) * 1976-08-13 1978-03-01 Nippon Television Ind Corp Synchronous signal generator
FR2474794A1 (fr) * 1980-01-25 1981-07-31 Labo Electronique Physique Circuit de correction des ecarts de phase entre les signaux de commande de balayage et les signaux de synchronisation lignes dans un recepteur de television

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DE2517046B1 (de) * 1975-04-17 1976-09-16 Siemens Ag Fernsehimpulsgeber
US4203135A (en) * 1977-01-27 1980-05-13 Sanyo Electric Co., Ltd. External synchronizing signal generating circuit for a color television camera
FR2391620A1 (fr) * 1977-05-18 1978-12-15 Sony Corp Generateur de signaux de sy

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2685584A1 (fr) * 1991-12-18 1993-06-25 Philips Electronics Nv Dispositif generateur de signal de synchronisation.
WO1994001965A1 (fr) * 1992-07-03 1994-01-20 British Broadcasting Corporation Generateur de signaux de synchronisation
US5495294A (en) * 1992-07-03 1996-02-27 British Broadcasting Corporation Synchronising signal generator

Also Published As

Publication number Publication date
JPS5825773A (ja) 1983-02-16
US4488170A (en) 1984-12-11
AU8614182A (en) 1983-01-27
KR840001033A (ko) 1984-03-26
HK27386A (en) 1986-04-25
EP0070603B1 (fr) 1984-11-21
AU550803B2 (en) 1986-04-10
BR8204182A (pt) 1983-07-12
KR890000979B1 (ko) 1989-04-15
DE3261293D1 (en) 1985-01-03
NL8103437A (nl) 1983-02-16

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