EP0066013B1 - Système de reconnaissance d'objets, commandé par processeur - Google Patents

Système de reconnaissance d'objets, commandé par processeur Download PDF

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Publication number
EP0066013B1
EP0066013B1 EP81200602A EP81200602A EP0066013B1 EP 0066013 B1 EP0066013 B1 EP 0066013B1 EP 81200602 A EP81200602 A EP 81200602A EP 81200602 A EP81200602 A EP 81200602A EP 0066013 B1 EP0066013 B1 EP 0066013B1
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EP
European Patent Office
Prior art keywords
output
article
circuit
signal
input
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EP81200602A
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German (de)
English (en)
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EP0066013A1 (fr
Inventor
Robertus Josepha Elisa Spoormans
André Gustave Ghislain Pochet
Ludwig Jan Sylvain De Maeyer
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International Standard Electric Corp
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International Standard Electric Corp
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Priority to EP81200602A priority Critical patent/EP0066013B1/fr
Priority to DE8181200602T priority patent/DE3175713D1/de
Priority to AT81200602T priority patent/ATE24247T1/de
Priority to BE2/59716A priority patent/BE893272A/nl
Priority to NZ200726A priority patent/NZ200726A/en
Priority to AU84254/82A priority patent/AU553285B2/en
Priority to ES512826A priority patent/ES512826A0/es
Publication of EP0066013A1 publication Critical patent/EP0066013A1/fr
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Publication of EP0066013B1 publication Critical patent/EP0066013B1/fr
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    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07D—HANDLING OF COINS OR VALUABLE PAPERS, e.g. TESTING, SORTING BY DENOMINATIONS, COUNTING, DISPENSING, CHANGING OR DEPOSITING
    • G07D5/00—Testing specially adapted to determine the identity or genuineness of coins, e.g. for segregating coins which are unacceptable or alien to a currency
    • G07D5/08—Testing the magnetic or electric properties
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07D—HANDLING OF COINS OR VALUABLE PAPERS, e.g. TESTING, SORTING BY DENOMINATIONS, COUNTING, DISPENSING, CHANGING OR DEPOSITING
    • G07D5/00—Testing specially adapted to determine the identity or genuineness of coins, e.g. for segregating coins which are unacceptable or alien to a currency
    • G07D5/02—Testing the dimensions, e.g. thickness, diameter; Testing the deformation

Definitions

  • the present invention relates to an article recognition system including measuring means producing a measurement result varying at least in function of the relative position of said article with respect to said measuring means and of other characteristics of said article, and article sensing means producing a control signal upon a part of said article occupying with respect to said measuring means a predetermined position wherein said article influences said measuring means, said control signal being wble to authorize the evaluation of the result of the measurement then provided by said measuring means.
  • Such an article recognition system and more particularly a coin recognition system, is already known from DE-A-2213376 and partly also from GB-A-1536904.
  • This known system has been particularly designed for discriminating between coins of different diameter and does not provide an optimum result when used for discriminating between coins having a same diameter because during a test generally only a portion of the coin volumes is tested.
  • An object of the present invention is to provide an article recognition system of the above type, but which always provides an optimum discrimination between articles, whether they have the same dimensions or not.
  • said measuring means include register means for periodically storing the last result of a measurement
  • the system further includes a first detection circuit providing said first mentioned control signal, gating means coupled to said register means and controlled by said first control signal and by a selection signal able to selectively allow or inhibit the latching of the last result stored in said register means upon the occurrence of said first control signal, a second detection circuit providing a second control signal for starting the operation of said measuring means and for stopping it when a measured result reaches a limit value, and a processor able to provide said selection signal as well as to enter said latched last result and said limit result in its memory and to process these results.
  • a single measuring means is used either to perform a first test, specifically designed for discriminating between articles of different dimensions, followed by a second one wherein a larger portion of the volume of the articles is tested than in the first test, or to perform the second test alone e.g. in case the articles have the same dimensions.
  • a processor controlled coin telephone system is already known e.g. from the article "N.T. 2000 Coin Telephone Microprocessor Techniques" by D. Adolphs, published in Electrical Communication, Volume 52, N° 3, 1977, pp. 213-218.
  • This coin recognition system forms part of a coin controlled telephone system with a coin box (not shown) including a coin path CP (Fig. 5) which extends along three coin sensing circuits CSC1, CSC3 and CSC2 (Figs. 1 and 5) in succession and further leads to a coin collection box and to a coin refund box via deflector mechanisms (all not shown) able to be operated under the control of the system.
  • This system includes a 1 MHz clock unit CLU (Fig. 2), a signal source SS (Fig. 2), a microprocessor MP (Fig. 2), a memory comprising a data memory DMEM (Fig. 3) and a programme memory (not shown), an input-output circuit IOC (Fig. 3), a control circuit CC (Fig.
  • the above mentioned three coin sensing circuits CSC1 to CSC3 (Fig. 1), a coin detection and measuring circuit cooperating with CSC1 and CSC2 and mainly including a coin detection circuit CDC1 (Fig. 1) and a measuring circuit mainly- comprising comparators COR1, COR2 (Fig. 1), digital-to-analogue converter DAC (Fig. 3) associated with circuit AFC and counters CR1 and CR2 (Fig. 2), a coin sensing and detection circuit including the above mentioned coin sensing circuit CSC3 and a coin detection circuit CDDC (Fig. 1), and an error detection circuit EDC mainly including a counter CR3 (Fig. 2).
  • the microprocessor MP is able to execute a plurality of programmes stored in its programme memory, i.e. clock level programmes and base level programmes. These base level programmes comprise a plurality of task programmes and a supervisory or monitor programme. Each time the processor MP has executed a task programme, control is given back to the monitor programme which amongst other operations then allocates a new task programme.
  • the execution of the base level programmes is periodically interrupted, e.g. about every 9.3 milliseconds, by a clock interrupt signal applied to the interrupt input INT of the microprocessor MP by counter CR3.
  • the microprocessor MP when accepting the request for interrupt activates its control output C04 and executes a clock level programme and thereafter resumes the interrupted base level programme.
  • the data memory DMEM (Fig. 3) is a 256 Wordx8 Bit Static EEPROM memory of the type 1842 manufactured by RCA. It has data terminals Do to D7 connected to like named data terminals of the microprocessor MP and the input/output circuit IOC, address inputs Ao to A7, a programme input PI and an erase input EI.
  • a storage procedure consists of addressing a cell of 8 memory locations by supplying the address thereof to the address inputs Ao to A7, applying the data to be stored to the data terminals Do to D7 and de-activating (logic 0) the programme input PI.
  • a read procedure consists of addressing a cell and activating (logic 1) the programme input Pl. The data then read appear at the data terminals Do to D7. Finally, to erase the contents of the memory it is sufficient to activate the erase input EI for 10 milliseconds with all other terminals de-activated.
  • the input/output circuit IOC (Fig. 3) is an 8-bit Input/Output Port of the type 1852 manufactured by RCA. It has data inputs Bo to B7 connected to data outputs Do to D7 of counter CR2 via terminals Jo to J7 and inverters INV3 to INV10 respectively; data outputs Do to D7 connected to the like named data terminals of MP and DMEM and a clock input CL connected to a like named control output of the coin detection circuit CDDC (Fig. 1), more particularly to the output of the OR-gate OR thereof.
  • Data applied to the data inputs Bo to B7 are strobed into the IOC when the. clock input CL is activated (logic 1) and are latched therein when the activated clock input CL becomes de-activated (1 to 0 transition).
  • the control circuit CC selectively enables the above pulse waveforms of frequency f1, f2 and f3 to be applied to the inputs 11, 12 and 13 of the coin sensing circuits CSC1, CSC2 and CSC3 respectively. It includes NOR-gates NOR1 to NOR3 and inverter INV1. NOR-gate NOR1 has inputs which are connected to the control output C01 of microprocessor MP and to the divide-by-8 output D8 (fed by a pulse waveform of frequency f1) of signal source SS and an output 11 which is connected to input terminal 11 of coin sensing circuit CSC1 (Fig. 1).
  • the control output C01 of MP is also connected via the inverter INV1 to an input of NOR-gate NOR2 the other input of which is connected to the divide-by-4 output D4 (fed by a pulse waveform of frequency f2) of signal source SS.
  • the output 12 of NOR-gate NOR2 is connected to input terminal 12 of coin sensing circuit CSC2 (Fig. 1).
  • NOR-gate NOR3 has inputs which are connected to the divide-by-2 output D2 (fed by pulse waveform of frequency f3) of signal source SS and to the control output C03 of the microprocessor MP.
  • the output 13 of NOR3 is connected to the input terminal 13 of coin sensing circuit CSC3 (Fig. 1).
  • the coin sensing circuit CSC1 (Fig. 1) with input terminal i1 and output terminal 01 includes a transformer Tr with cylindrical sensing coils L1 and L2 (Fig. 4) mounted along the above mentioned coin path CP and at a distance from each other so as to permit the passage of a coin.
  • Input terminal 11 is connected to -V1 via resistors R1 and R2 in series, the latter resistor R2 being shunted by the series connection of filter capacitor C1 and sensing coil L1.
  • Sensing coil L2 is shunted by filter capacitor C2 and by a further filter circuit comprising capacitor C3 in series with resistor R3, the junction point of C3 and R3 forming the output terminal 01 of CSC1.
  • Coin sensing circuit CSC2 with input terminal 12 and output terminal 02 is similar to coin sensing circuit CSC1 and includes a transformer with cylindrical sensing coils L3 and L4 (Fig. 1), the other components being indicated by the same numerals as those of CSC1, however provided with an accent.
  • the coin sensing circuit CSC2 is also mounted along the above mentioned coin path CP and the same is true for coin sensing circuit CSC3 which is located between CSC1 and CSC2 (Fig. 5).
  • the time interval during which the amplitude of the output voltage signal is larger than -2V1 becomes larger than a predetermined time interval T1 (Fig. 5) and this is therefore used by CDC1 as a criterion for indicating that a coin is being sensed, as will be explained later.
  • the above maximum amplitude of the output voltage signal of CDC1 or CDC2 in the absence of a coin is obtained by a suitable choice of the values of R1 and R2 or R'l and R'2.
  • the purpose of filter circuit R3, C3 or R'3, C'3 is to suppress low frequency spurious signals generated in the coils L1, L2 or L3, L4 upon the passage between them of a magnetized coin, i.e. one having north and south poles.
  • the above mentioned coin detection and measuring circuit is used for detecting if a coin is being sensed or not by the coin sensing circuit CSC1 or CSC2 and for measuring the minimum reduced amplitude of the output voltage signal provided by this coin sensing circuit when a coin is being sensed.
  • This detection and measuring circuit includes the above mentioned coin detection circuit CDC1 and a measuring circuit comprising an analogue-to-digital converter with two comparators COR1 and COR2 individually associated to CSC1 and CSC2 respectively, a common digital-to-analogue converter DAC (Fig. 3) with an associated circuit AFC and a common counter comprising CR1 and CR2 (Fig. 2).
  • Each of the comparators COR1 and COR2 (Fig. 1) is of the type pA 339 manufactured by Fairchild and has an output 14 constituted by the collector of an NPN transistor T the emitter of which is coupled to -V2.
  • the non-inverting input of each of these comparators is connected to the output 01, 02 of the corresponding coin sensing circuit CSC1, CSC2 respectively, and the output OT1 of the converter DAC (Fig. 3) is connected to the common inverting inputs of these comparators COR1 and COR2 via the amplifier and filter circuit AFC (Fig. 3).
  • the outputs of COR1 and COR2 are both connected to an input 14 of the coin detection circuit CDC1 which is coupled to counter CR1 (Fig. 2).
  • the circuit CDC1 comprises a parallel circuit constituted by collector resistor R5 and collector capacitor C4 and connected between Vo and the collector outputs of COR1 and COR2 and a series circuit constituted by clamping diode d1 and resistor R4 and connected between -V1 and 14.
  • the junction point of d1 and R4 is connected to the output 04 of CDC1 via inverter INV2.
  • the purpose of CDC1 is to establish the above mentioned predetermined time interval T1 which is for instance equal to 470 microseconds and to produce a deactivated binary output signal at its (normally activated) output 04 for instance when a coin is being sensed by CSC1 or CSC during at least this time interval. This output signal then authorizes the start of a-measuring operation.
  • junction point of d1 and R4 is considered to be activated (logic 1) when its voltage is larger than and de-activated (logic) when its voltage is smaller than this value.
  • Counter CR1 (Fig. 2) together with signal source .
  • SS forms the above mentioned Dual-Up counter and has a clock input CI connected to output D4 of signal source SS, a divide-by-2 output D2 on which appears a square pulse waveform of frequency when the counter is enabled, and a reset input RS which is connected to the output 04 of the coin detection circuit CDC1 and which when activated (logic 1) inhibits the counter CR1.
  • This counter is enabled when this output 04 is de-activated i.e. when a coin is being sensed by CDC1 or CDC2 at least during the above mentioned time interval T1.
  • Counter CR2 (Fig. 2) is a Dual-Up-Counter of the above type but of which the two constituent counters have been interconnected so as to form a counter able to count N' from 0 to 255.
  • This counter CR2 has a clock input CI connected to output D2 of counter CR1 and is therefore fed by a pulse waveform having a frequency f1 when this counter CR1 is enabled, a reset input RS connected to control output C02 of microprocessor MP and outputs Do to D7 which are connected to like named inputs of IOC and DAC via inverters INV3 to INV10 and output terminals Jo to J7.
  • this output signal changes every period off1 i.e. every 64 microseconds.
  • the digital-to-analogue converter circuit DAC (Fig. 3) is an 8-bit Buffered Multiplying DAC of the type AD7523 manufactured by Analog Devices. It has data inputs Do to D7 connected to like named outputs of counter CR2 and output terminals OT1 and RFB which are internally interconnected by a suitable feedback resistance (not shown).
  • the DAC also has a reference input VREF connected to Vo, a ground input GND connected to -V1 and an output OUT2 also connected to -V1.
  • the circuit AFC (Fig. 3) which is connected to output OUT1 of the DAC mainly includes operational amplifier OA which is in fact of the same type as the comparators COR1 and COR2 but is now used as a low frequency operational amplifier.
  • This use and the connection of amplifier OA to the output of the DAC is disclosed in data sheets provided by the manufacturers.
  • the non-inverting input of this amplifier OA is connected to -V1 and its inverting input is connected to its collector output via a parallel circuit comprising filter capacitor C5 and the above mentioned feedback resistance (not shown) in the DAC.
  • This collector output is further connected to Vo via collector resistor R5, to -V1 via filter capacitor C6 shunted by resistor R6 and capacitor C7.
  • Capacitors C5 and C6 are filter capacitors to smoothen the staircase current waveform provided at the output of the DAC and to prevent oscillation or ringing.
  • C7 and R6 constitute a low-pass filter providing a further filtering.
  • the junction point 06 of C7 and R6 is connected to the common inverting inputs of COR1 and COR2.
  • the coin sensing and detection circuit includes coin sensing circuit CSC3 and coin detection circuit CDDC.
  • Coin sensing circuit CSC3 (Fig. 1) with input terminal 13 and output terminal 03 includes a cylindrical sensing coil L5 (Fig. 5) mounted along the above mentioned coin path CP and between CSC1 and CSC2.
  • CSC3 is however so close to CSC2 that even a coin with the smallest diameter able to be processed by the system is simultaneously sensed by CSC2 and CSC3 at least during a certain time interval.
  • Cylindrical coil L5 has a diameter which is considerably smaller than that of coils L1 to L4 in order that the variation of the output signal at terminal 03 should be relatively abrupt. Because of the use of such a small diameter _coil L5 a higher frequency f3 is required to obtain a suitable output voltage signal.
  • Input terminal 13 is connected to one end of a parallel circuit comprising coil L5 and filter capacitor C10 via a lowpass filter circuit comprising resistor R7 and filter capacitor C9, one end of which is connected to -V1, and via coupling capacitor C8 which together with capacitor C10 constitutes a capacitive voltage divider and also prevents DC current flow from input 13 to -V1.
  • the other end of L5, C10 is connected to -V1. Its one end is also connected to the output terminal 03 via a further filter circuit comprising capacitor C11 and resistor R8 one end of which is connected to Vo.
  • This filter circuit C11, R8 serves for suppressing low frequency spurious signals generated by magnetized coins passing along coil L5.
  • the coin sensing circuit CSC3 is able to transform a square pulse waveform at frequency f3 applied to its input 13 into a substantially sinusoidal signal the amplitude of which is function of the influence of a coin on sensing coil L5.
  • the above sinusoidal signal periodically becomes larger than -V1 for a time interval about equal to a whole period.
  • the coin detection circuit CDDC is used for detecting if a coin is. being sensed or not by CSC3 and for providing a corresponding binary output signal at the output of OR-gate OR (Fig. 3). A 1 to 0 transition of the latter signal is used in the case of diameter test for latching the result of the measurement then provided by the coin detection and measuring circuit.
  • the coin detection circuit CDDC (Fig. 1) includes a comparator COR3 which is of the same type as the comparators COR1 and COR2 and a detection circuit CDC2 which is of the same type as CDC1.
  • the inverting input of COR3 is connected to -V1 via resistor R9 and its non-inverting input is connected to the output 03 of CSC3.
  • the collector output or COR3 is connected to an input 15 of the detection circuit CDC2.
  • This circuit CDC2 comprises a parallel circuit constituted by collector resistor R11 and collector capacitor C12 and connected between Vo and the collector output 15 of COR3 and a series circuit constituted by clamping diode d2 and resistor R10 and connected between -V1 and 15.
  • junction point 05 of d2 and R10 is connected to the like named input 05 of an OR-gate OR (Fig. 3) the other input of which is connected to the output C03 of the microprocessor MP.
  • the output CL of OR-gate OR is connected to the like named clock input CL of the input/output circuit IOC.
  • the junction point of d2 and R10 is considered to be activated and de-activated when its voltage is larger and smaller than
  • the purpose of the detection circuit CDC2 is to establish the above mentioned predetermined time interval T2 which is for instance equal to 470 microseconds and to produce at the normally de-activated output 05 an activated binary output signal only when a coin is being sensed by CDC3 during at least this time interval A 1 to 0 transition produced on output 05 at the moment a coin is no longer sensed by SCS3 and when diameter testing is performed (C03 on 0) is used to latch the contents of IOC via OR-gate OR.
  • the outputs G8 and G12 are connected to the clock interrupt input INT of the microprocessor MP via a NAND-gate NAND.
  • the counter-is regularly reset-as will be explained later-a pulse waveform comprising positive pulses having a length of about 9.126 milliseconds separated by very small reset intervals appears at the output INT of this NAND-gate NAND.
  • the counter CR3 is stepped and at a certain moment the interrupt output INT of the associated gate NAND is activated, this signal having no influence on the operation of the microprocessor MP which is for instance executing one of the base level programmes.
  • the signal source SS provides at its outputs D8, D4 and D2 the above square pulse waveforms of frequency f1, f2 and f3 which are applied to NOR-gates NOR1, NOR2 and NOR3 of which only NOR1 is enabled.
  • the square pulse waveform at frequency f2 is also applied to the clock input CI of counter CR1 the operation of which, however, is inhibited as its reset input RS is activated by the activated output 04 of the detection circuit CDC1.
  • NOR-gate NOR1 Due to the NOR-gate NOR1 being enabled a square pulse waveform at frequency f1 is applied to input 11 of coin sensing circuit CSC1.
  • the counter CR2 has been reset its digital output N' is zero so that, via the DAC, a threshold signal or about -2V1 is applied to the inverting input of COR1.
  • a coin such as CN (Fig. 5)
  • it first passes between the sensing coils L1 and L2 of the transformer Tr of coin sensing circuit CSC1 due to which the amplitude of the sinusoidal voltage signal normally varying between a minimum value slightly smaller than -2V1+Vo and a maximum value slightly larger than Vo gradually decreases towards a miminum value and afterwards again gradually increases.
  • Fig. 4 wherein two different time scales are used in the left and right hand parts of the drawing. More particularly when a coin is present the amplitude of this reduced signal becomes larger than -2V1 +Vo for a time interval much larger than the above mentioned predetermined time interval T1.
  • This amplitude reduction and more particularly the minimum amplitude is detected by the coin detection circuit CDC1. Indeed, because a threshold voltage signal having an amplitude equal to or about -2Vl is still being applied to the inverting input of the comparator COR1 the output transistor T thereof remains blocked for a time interval much larger than T1. Thus the capacitor C4 is allowed to discharge to such a value that the junction point of diode d1 and resistor R4 becomes activated and that the output 04 of CDC1 becomes de-activated. Thus counter CR1 is enabled. As soon as this happens a measuring or analogue-to-digital operation is started.
  • this counter CR1 then counts the pulses of the square pulse waveform at frequency f2 applied to its clock input Cl, and at its output D2 it generates a pulse waveform of frequency f1 which is applied to counter CR2.
  • the above mentioned threshold voltage E which substantially linearly increases from about -2V1 towards -V1 with a speed depending on the period of f1, this period being equal to 64 microseconds. This voltage is applied to 'the inverting input of comparator COR1.
  • the processor MP During the execution of the clock interrupt programme the processor MP enters the digital value appearing at the outputs Do-D7 of the input/output circuit IOC in one of its internal registers (not shown).
  • control output C01 to enable NOR-gate NOR2 and to inhibit NOR-gate NOR1.
  • the MP further activates control output C02 to reset counter CR2 and de-activates or activates control output C03 depending on a diameter test having to be performed or not respectively.
  • Coil L5 of CSC3 is so mounted with respect to coils L3, L4 of CSC2 that even a coin with the smallest diameter able to be handled is sensed by CSC2 at the moment the passage of its trailing edge is sensed by CSC3.
  • the coin volume then sensed by CSC2 is proportional to the coin diameter.
  • a measuring operation similar to that described in relation with CSC1 but now using comparator COR2 is started so that the digital result of this operation at the moment the trailing edge of the coin no longer influences the sensing coil L5 is also a measure of this diameter.
  • the microprocessor MP compares the measured digital value N1 successively with the sets of stored digital values of the first series N11 MIN, N11 MAX to N1m MIN, N1m MAX to find out to which set the coin measured belongs. If N1 does not belong to this first series of sets the coin is not accepted as valid and led to the refund box, whereas when it belongs to one of these sets the microprocessor MP successively checks whether or not the measured digital values N2 and N3 belong to the homologue or correlated sets in the second and third series of sets of stored digital values N21 MIN, N21 MAX to N2m MIN, N2m . MAX and N31 MIN, N31 MAX to N3m MIN, N3m MAX. If the coin does not belong to both these related sets it is rejected and led to the refund box, whereas otherwise it is accepted as valid.
  • N11 MIN, N1a; N1b, N1c; and N1d N11 MAX and N21 MIN, N2a; N2b, N2c; and N2d, N21 MAX and to accept a coin as valid only when it belongs to homologue or correlated subranges e.g. N11 MIN, N1a and N21 MIN, N2a.
  • the microprocessor MP grants a request (de-activation of interrupt input IN for a clock interrupt programme it activates its control output CQ4, due to which counter CR3 is then reset by the activation of its reset input RS.
  • the processor MP then ⁇ also subtracts a unit for a value stored in a counter word CR of the memory MEM, this value being at most equal to Np (Fig. 6).
  • the microprocessor MP has finished a clock level programme it resumes the interrupted task level programme and after having executed this programme it executes the monitor programme. Under the control of this programme the value stored in the counter word CR is made equal to the maximum value Np. The latter value has been so chosen'that taking the interrupts into account the resultant value stored in the counter word CR never becomes zero under normal operating conditions.
  • the processor MP enters a programme loop during the execution of a clock interrupt programme, it will in general not be able to react to a request for a clock interrupt, i.e. to a de-activation of its interrupt input INT by the counter CR3.
  • the microprocessor MP will therefore also not activate its control output C04 to reset the counter CR3 and the latter will therefore be able to count further than 9.216 milliseconds.
  • the alarm output G12 which is a general reset output will therefore be activated to reset all the constituent parts of the system (not shown). All operations will then start from the beginning under the control of the processor MP and in most cases the system will then operate correctly because the error is generally a spurious one.
  • the processor MP enters a programme loop during the execution of a base level programme it generally remains able to react to a request for a clock interrupt applied to its interrupt input INT by the counter CR3. However, because no monitior programme is executed the value stored in the counter word CR will not periodically be set to Np but will each time be decreased by 1 and finally reach 0. When this happens the processor MP disables the interrupt input INT so that it is no longer able to react to request for a clock interrupt and that the counter CR3 is not reset. Just as in the above considered case this counter is therefore able to count further until its alarm output G12 is activated.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Coins (AREA)
  • Image Analysis (AREA)
  • Image Processing (AREA)
  • Selective Calling Equipment (AREA)

Claims (12)

1. Système de reconnaissance d'articles comprenant des moyens de mesure (CSC2, CDC2, COR2, DAC, IOC, AFC, CR1, CR2) produisant un résultat de mesure variant au moins en fonction de la position relative du dit article par rapport aux dits moyens de mesure et à d'autre caractéristiques du dit article, et des moyens sensoriels d'article (CSC3, CDDC) produisant un signal de commande (05) lorsqu'une partie du dit article occupe par rapport aux dits moyens de mesure une position prédéterminée dans laquelle ledit article influence lesdits moyens de mesure, ledit signal de commande étant capable d'autoriser l'évaluation du résultat de la mesure alors fournie par lesdits moyens de mesure, caractérisé en ce que lesdits moyens de mesure (CSC2, CDC2, COR2, DAC, IOC, AFC, CR1, CR2) comprennent des moyens registre (CR1/2, IOC) pour emmagasiner périodiquement les derniers résultats d'une mesure et en ce que le système comprend de plus un premier circuit de détection (CDDC) produisant ledit signal de commande premièrement mentionné (05), des moyens de porte (OR) couplés aux dits moyens registre et commandés par ledit premier signal de commande (05) et par un signal de sélection (C03) pouvant autoriser ou empêcher sélectivement la retenue du dernier résultat (N3) emmagasiné dans lesdits moyens registre au moment où ledit premier signal de comman (05) se produit, un second circuit de détection (CDDC) fournissant un second signal de command (04) pour démarrer le fonctionnement des dits moyens de mesure et pour les arrêter lorsqu'un résultat mesuré (N2) atteint une valeur limite, et un processeur (MP) capable de fournir ledit signal de sélection (C03) ainsi que d'entrer ledit dernier résultat retenu (N3) et ledit résultat limite (N2) dans sa mémoire et de traîter ces résultats.
2. Système de reconnaissance d'articles selon la revendication 1, caractérisé en ce que lesdits moyens sensoriels d'article (CSC3, CDDC) comprennent un premier circuit sensoriel (CSC3) fournissant un premier signal de sortie dont l'amplitude varie autour d'un premier niveau de référence (Vo) de telle façon qu'il dépasse périodiquement un deuxième niveau de référence (-V1 ) pour un intervalle de temps plus petit qu'un premier intervalle de temps prédéterminé (T2) en l'absence d'un article et pour un intervalle de temps plus grand que ledit premier intervale de temps prédéterminé (T2) en présence d'un article, et en ce que lesdits moyens sensoriels d'article comprennent de plus ledit premier circuit de détection (CDDC) comprenant un premier comparateur (COR3) avec une première entrée à laquelle ledit premier signal de sortie est directement appliqué, avec une seconde entrée à laquelle ledit deuxième niveau de référence (-V1) est appliqué et avec une sortie (15) couplée à l'entrée d'un premier circuit temporisateur (C12, R11, R10, d2) qui est capable d'établir ledit premier intervalle de temps prédéterminée et qui est démarré et remis à zéro lorsque les sorties du dit premier comparateur (COR3) ont une première et une seconde relation l'une par rapport à l'autre respectivement, ledit premier circuit temporisateur fournissant un deuxième signal de sortie lorsque les entrées du dit premier comparateur (COR3) ont une première relation prédéterminée pour un intervalle de temps plus grand que lëdit premier intervalle de temps prédéterminé (T2) du au fait qu'un article ait été détecté par. ledit premier circuit sensoriel (CSC3), et que ledit premier signal de commande (05) est constitué par une variation prédéterminée du dit deuxième signal de sortie, ladite variation prédéterminée étant produite lorsque le bord arrière du dit article quitte ledit premier circuit sensoriel (CSC3).
3. Système de reconnaissance d'articles selon la revendication 1, caractérisé en ce que lesdits moyens de mesure comprennent un second circuit sensoriel (CSC2) fournissant un troisième signal de sortie ayant une caractéristique électrique qui est fonction au moins du dit matériau, de la position relative du dit article et du dit second circuit sensoriel, et un circuit de détection et de mesure (CDC1, COR2, DAC, AFC, CR1, CR2) couplé au dit second circuit sensoriel et comprenant ledit second circuit de détection (CDC1) pour détecter une modification de ladite caractéristique électrique provoquée dans ledit second circuit sensoriel par la présence d'un article, et un circuit de mesure (COR2, DAC, AFC, CR1, CR2) pour mesure une caractérisqique électrique donc modifiée et produisant ledit résultat de mesure.
4. Système de reconnaissance d'articles selon la revendication 3, caractérisé en ce que ledit circuit de mesure fourni ledit signal de mesure sous forme numérique et inclu un convertisseur analogique-numérique (COR2, DAC, AFC, CR1, CR2) adapter pour convertir ladite caractéristique électrique du dit troisième signal de sortie dans la dite forme numérique après que ledit second circuit de détection (CDC1) ait détecté une modification de ladite caractéristique électrique et air produit ledit second signal de commande (04) pour autoriser le fonctionnement du dit convertisseur analogique-numérique, et en ce que ledit convertisseur analogique-numérique inclus un second comparateur (COR2) avec une première entrée à laquelle ledit troisième signal de sortie est directement appliqué, avec une second entrée et avec une sortie (14) couplée via ledit second circuit de détection (CDC1) avec une entrée de commande (RS) d'un compteur (CR1, CR2) qui emmagasine ledit résultant de mesure sous forme numérique et qui a une sortie couplée avec une entrée d'un convertisseur numérique-analogique (DAC, AFC) ayant une sortie couplée avec ladite second entrée du dit second comparateur (COR2) ledit second circuit de détection (CDC1) fournissant ledit second signal de command (04) à ladite entrée de commande (RS) du dit compteur (CR1, CR2) lorsqu'un article est détecté par ledit second circuit sensoriel (CSC2), ledit second signal de commande autorisant le fonctionnement du dit compteur (CR1, CR2) et du dit convertisseur numérique-analogique (DAC, AFC) qui fourni alors un signal de seuil variant à sa sortie, la sortie du dit compteur (CR1, CR2) étant également couplée avec un registre (IOC) faisant partie des dits moyens registre (CR1/2, IOC) ensemble avec ledit compteur.
5. Système de reconnaissance d'articles selon la revendication 4, caractérisé en ce que ledit second circuit sensoriel (CSC2) fourni ledit troisième signal de sortie dont l'amplitude varie autour d'un troisième niveau de référence (-V1) de telle façon qu'il dépasse périodiquement un quatrième niveau de référence (-2V1) pour des intervalles de temps plus petits qu'un second intervalle de temps prédéterminé (T1) en l'absence d'un article et pour un intervalle de temps plus grand que ledit second intervalle de temps prédéterminé (T1) en présence d'un article, et en ce que ledit second circuit de détection (CDC1) est constitué d'un second circuit temporisateur (C4, R5, R4, d1 ) capable de compter ledit second intervalle de temps prédéterminé (T1) et dont la sortie est couplée à la sortie du dit second comparateur (COR2) et qui est démarré et remis à zéro lorsque les entrées du dit second comparateur (COR2) ont une première et une seconde relation l'une par rapport à l'autre respectivement ledit second circuit temporisateur fournissant ledit second signal de commande (04) lorsque lesdites entrées du dit second comparateur (COR2) ont une première relation prédéterminée pour un intervalle de temps plus grand que ledit second intervalle de temps prédéterminé (T1) du au fait qu'un article ait été détecté, ledit second signal de commande (04) démarrant alors le fonctionnement du dit convertisseur numérique-analogique qui fournit ledit signal de seuil variable variant depuis ledit quatrième niveau de référence (-2V1) vers ledit troisième niveau de référence (-V1) jusqu'à ce que lesdits entrées du dit second comparateur (COR2) ont ladite second relation prédéterminée, ledit compteur fournissant alors ledit résultat de mesure.
6. Système de reconnaissance d'articles selon la revendication 2, caractérisé en ce que ledit premier comparateur (COR3) comprend un premier transistor dont le chemin collecteur- émetteur est couplé entre ladite sortie (15) du dit premier comparateur (COR3) et un troisième niveau de référence (-V2) et en ce que ledit premier circuit temporisateur (C12, R11, R10, d2) comprend un premier circuit parallèle raccordé entre ledit premier niveau de référence (Vo) et ladite sortie du premier comparateur (15) et étant constitué d'un premier condensateur (C12) et d'une première résistance (R11), et un premier circuit série (d2, R10) raccordé entre ledit deuxième niveau de référence (-V1 ) et ladit sortie du premier comparateur (15) et étant constitué d'une première diode (d2) et d'une deuxième résistance (Rl 0), le point de jonction (05) de ladite première diode (d2) et de ladite deuxième résistance (R10) étant couplée aux dits moyens de porte (OR).
7. Système de reconnaissance d'articles selon la revendication 2, caractérisé en ce que ledit premier circuit sensoriel (CSC3) est adapté pour transformer une première forme d'onde carrée variant entre lesdits premier (Vo) et deuxième (-V1) niveaux de référence en un premier signal de sortie substantiellement sinusoïdal qui constitue ledit premier signal de sortie, et comprend au moins un bobinage sensoriel (L5) monté le long d'un chemin suivit par ledit article et faisant partie d'une premier circuit de filtre ayant une entrée (13, - V1) à laquelle ladite forme d'onde carrée est appliquée et aux bornes duquel une troisième résistance (R7), un deuxième condensateur (C8) et un troisième condensateur (C10) qui court-circuite ledit bobinage sensoriel (L5) sont raccordés en série, un quatrième condensateur (C9) court-circuitant la connexion série des dits deuxième (C8) et troisième (C10) condensateurs.
8. Système de reconnaissance d'articles selon la revendication 3, caractérisé en ce que ledit second circuit sensoriel (CSC2) est adapté pour transformer une seconde forme d'onde carrée en une seconde forme d'onde substantiellement sinusoïdale qui constitue lefit troisième signal de sortie, en ce que ladite second forme d'onde carrée varie entre Vo et -V1, alors que ledit second signal sinusoïdal varie autour de -V1 et a une amplitude égale à V1+Vo, et en ce que ledit convertisseur numérique-analogique fournit à sa sortie ledit signal de seuil
Figure imgb0013
où -V1 est ledit troisième niveau de référence, Vo est un cinquième niveau de référence et N est la valeur numérique fournie par ledit compteur (CR1, CR2) au dit convertisseur numérique-analogique (DAC, AFC).
9. Système de reconnaissance d'articles selon la revendication 8, caractérisé en ce que ledit second circuit sensoriel (CSC2) comprend deux premiers bobinages sensoriels (L3, L4) montés sur des faces opposées d'un chemin suivi par ledit article et constituant les enroulements primaire (L3) et secondaire (L4) d'un transformateur qui fait partie d'un second circuit de filtre ayant une entrée (-V1, 12) à laquelle ladite force d'onde carrée est appliquée et aux bornes duquel ledit enroulement primaire (L3), un cinquième condensateur (C'1) et une quatrième résistance (R'1) sont raccordés en série, la connexion série du dit enroulement primaire (L3) et du dit cinquième condensateur (C'1) étant court- circuitée par une cinquième résistance (R'2) et ledit enroulent secondaire (L4) étant raccordée en parallèle avec un sixième condensateur (C'2) aux bornes d'une sortie (-V1, 02) du dit second circuit de filtre, ledit second signal sinusoïdal apparaissant à ladite sortie du dit second circuit de filtre.
10. Système de reconnaissance d'articles selon la revendication 7 ou 9, caractérisé en ce qu'au moins un des dits premier et second circuits sensoriels comprend un premier et un second filtres passes-bas (C10, R8; R'3, C'3 respectivement) pour empêcher des articles magnétisés d'avoir une influence sur lesdits premier et troisième signaux de sortie respectivement, et en ce que ledit second filtre passe-bas (R'3, C'3) comprend la connexion série d'une sixième résistance (R'3) et d'un septième condensateur (C'3) raccordés aux bornes du dit enroulement secondaire (L4) et ladite sixième résistance (R3) étant raccordée aux bornes de ladite sortie (-V1, 02) du dit second circuit de filtre.
11. Système de reconnaissance d'articles selon la revendication 1, caractérisé en ce que ledit processeur (MP) exécute périodiquement des programmes de niveau d'horloge pendant lesquels lesdits résultats sonm entrés et qui s'intercalent avec des programmes de niveau de base pendant lesquels ces résultats sont traités, en ce que ledit processeur comprend de plus un circuit de temporisation (CR3) qui applique périodiquement un signal de requête pour un programme d'interruption d'horloge à une entrée d'interruption (INT) du dit processeur qui en réponse à ce signal et en fonctionnement correct accepte cette requête en appliquant un signal d'acceptation d'interruption à une sortie d'acceptation d'interruption (C04), et en ce que ladite sortie d'acceptation (C04) est raccordées à une entrée de remise à zéro (RS) du dit circuit de temporisation (CR3) qui fournit un signal d'alarme lorsqu'il n'a pas été remis à séro par ledit signal d'acceptation.
12. Système de reconnaissance d'articles selon la revendication 11, caractérisé en ce que ledit processeur (MP) a une mémoire associée (DMEM) qui emmagasine un mot compteur (CR) et est capable de mettre périodiquement ledit mot compteur (CR) à une première valeur prédéterminée (Np) et de modifier ladite valeur chaque fois qu'il accepte une dite requête d'interruption et que ledit processeur après que le contenu du dit mot compteur (CR) ait atteint une second valeur prédéterminée (O) parce qu'il n'a pas été mit pas ledit processeur met hors d'action sa dite entrée d'interruption et par conséquent aussie ladite sortie d'acceptation (C04).
EP81200602A 1981-06-03 1981-06-03 Système de reconnaissance d'objets, commandé par processeur Expired EP0066013B1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
EP81200602A EP0066013B1 (fr) 1981-06-03 1981-06-03 Système de reconnaissance d'objets, commandé par processeur
DE8181200602T DE3175713D1 (en) 1981-06-03 1981-06-03 Article recognition system and processor controlled system
AT81200602T ATE24247T1 (de) 1981-06-03 1981-06-03 Rechnergesteuertes system zum erkennen von gegenstaenden.
BE2/59716A BE893272A (nl) 1981-06-03 1982-05-24 Voorwerpherkenningssysteem en processor gestuurd systeem
NZ200726A NZ200726A (en) 1981-06-03 1982-05-25 Article passage recognition:size and material detection
AU84254/82A AU553285B2 (en) 1981-06-03 1982-05-28 Coin recognition system
ES512826A ES512826A0 (es) 1981-06-03 1982-06-03 "un sistema para reconocimiento de articulos controlado por procesador".

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP81200602A EP0066013B1 (fr) 1981-06-03 1981-06-03 Système de reconnaissance d'objets, commandé par processeur

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EP0066013A1 EP0066013A1 (fr) 1982-12-08
EP0066013B1 true EP0066013B1 (fr) 1986-12-10

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EP (1) EP0066013B1 (fr)
AT (1) ATE24247T1 (fr)
AU (1) AU553285B2 (fr)
BE (1) BE893272A (fr)
DE (1) DE3175713D1 (fr)
ES (1) ES512826A0 (fr)
NZ (1) NZ200726A (fr)

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JPS60262292A (ja) * 1984-06-08 1985-12-25 株式会社田村電機製作所 硬貨検査装置
DK158418C (da) * 1985-11-27 1990-10-22 Standard Electric Kirk Fremgangsmaade til identificering af moenter og apparat til brug ved udoevelse af fremgangsmaaden
ES1011067Y (es) * 1989-07-12 1992-04-01 Jofemar, S.A. Mejoras en la lectura de sensores magneticos en selectores de monedas.
JP3002904B2 (ja) * 1991-04-16 2000-01-24 株式会社日本コンラックス 硬貨処理装置
US5662205A (en) * 1994-11-03 1997-09-02 Coin Acceptors, Inc. Coin detection device
CN117218761B (zh) * 2023-08-07 2024-04-19 广州康艺电子有限公司 一种基于数据分析的验钞机性能测试系统

Family Cites Families (8)

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Publication number Priority date Publication date Assignee Title
US3152677A (en) * 1961-10-02 1964-10-13 Stoner Invest Inc Electronic coin detecting device
CH551056A (de) * 1971-06-11 1974-06-28 Berliner Maschinenbau Ag Verfahren zur pruefung metallischer gegenstaende, insbesondere von muenzen.
DE2213376A1 (de) * 1972-03-20 1973-09-27 Pruemm Geb Heuser Margot Elektronischer muenzpruefer
US3918565B1 (en) * 1972-10-12 1993-10-19 Mars, Incorporated Method and apparatus for coin selection utilizing a programmable memory
JPS5611181Y2 (fr) * 1975-12-02 1981-03-13
US4108296A (en) * 1976-04-08 1978-08-22 Nippon Coinco Co., Ltd. Coin receiving apparatus for a vending machine
FR2359468A2 (fr) * 1976-07-23 1978-02-17 Crouzet Sa Nouveau selecteur de pieces de monnaie pour distributeurs automatiques
US4323148A (en) * 1979-03-12 1982-04-06 Matsushita Electric Industrial Co., Ltd. Coin selector for vending machine

Also Published As

Publication number Publication date
ES8306543A1 (es) 1983-06-16
ATE24247T1 (de) 1986-12-15
EP0066013A1 (fr) 1982-12-08
AU553285B2 (en) 1986-07-10
DE3175713D1 (en) 1987-01-22
ES512826A0 (es) 1983-06-16
AU8425482A (en) 1982-12-09
BE893272A (nl) 1982-11-24
NZ200726A (en) 1985-03-20

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