EP0065571A4 - Gate modulation input circuit with polycrystalline silicon resistors. - Google Patents

Gate modulation input circuit with polycrystalline silicon resistors.

Info

Publication number
EP0065571A4
EP0065571A4 EP19820900203 EP82900203A EP0065571A4 EP 0065571 A4 EP0065571 A4 EP 0065571A4 EP 19820900203 EP19820900203 EP 19820900203 EP 82900203 A EP82900203 A EP 82900203A EP 0065571 A4 EP0065571 A4 EP 0065571A4
Authority
EP
European Patent Office
Prior art keywords
polycrystalline silicon
resistor
photodetector
substrate
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19820900203
Other languages
German (de)
English (en)
French (fr)
Other versions
EP0065571A1 (en
Inventor
William V Backensto
James L Gates
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Hughes Aircraft Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hughes Aircraft Co filed Critical Hughes Aircraft Co
Publication of EP0065571A1 publication Critical patent/EP0065571A1/en
Publication of EP0065571A4 publication Critical patent/EP0065571A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10Integrated devices
    • H10F39/12Image sensors
    • H10F39/15Charge-coupled device [CCD] image sensors
    • H10F39/157CCD or CID infrared image sensors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10Integrated devices
    • H10F39/12Image sensors
    • H10F39/15Charge-coupled device [CCD] image sensors
    • H10F39/157CCD or CID infrared image sensors
    • H10F39/1575CCD or CID infrared image sensors of the hybrid type

Definitions

  • This invention is related to charge transfer devices and, in particular, to gate modulation input circuits for infrared charge coupled device (CCD) imagers.
  • CCD charge coupled device
  • Infrared charge coupled device (CCD) imagers using gate modulation input techniques include a photosensitive detector controlling the potential on a CCD electrode overlying a charge coupled device channel. Modulation of the intensity of incident photons on the detector causes the potential of the CCD electrode to modulate accordingly, which modulates the current of injected carriers in the CCD channel passing beneath the modulated CCD electrode. The resulting modulated CCD current is the video signal representing the image viewed by the detector.
  • CCD charge coupled device
  • the dynamic range of a CCD is determined by the difference between the noise level of the CCD output current (which establishes a minimum current level) and the maximum charge storing capacity of each unit cell (or "bucket”) of the CCD (which establishes a maximum current level), in accordance with well-known principles in the art.
  • each CCD channel in a CCD focal plane array formed on a substrate has a high impedance DC current source comprising a polycrystalline silicon resistor formed monolithically in the substrate and having a resistance on the order of 10 10 ohms.
  • a high input impedance assures uniform DC current levels in all DC channels in the array regardless of processing non-uniformities.
  • the polycrystalline silicon resistor of this invention does not consume a large amount of space and therefore is compatible with the miniaturized monolithic integrated circuit structure disclosed herein.
  • FIG. 1 is a simplified schematic diagram of the present invention.
  • FIGS. 12-40 and 12-42 of The Infrared Handbook referenced above are schematic diagrams of CCD imager gate modulation circuits of the prior art.
  • FIG. 12-42 illustrates the concept of AC coupling of a CCD gate modulation input.
  • a current source is applied to the input diffusion so that a DC current level is constantly maintained in the CCD channel which may be modulated by the detector signal on the modulation gate connected to the detector output.
  • the DC current level may be non-uniform in the various channels.
  • some CCD channels in the array will be saturated with injected charge while other CCD channels may be starved in response to a given input signal, causing severe distortion of the output video signal from the detector array.
  • the problem of non-uniform DC current levels may be solved by increasing the input impedance, through which a voltage is applied to the input diffusion, to be on the order of 10 10 ohms.
  • a CCD gate modulation input circuit 1 is formed in a focal plane array comprising a plurality of such circuits, 1a-1n, on a semiconductor substrate 2 (preferably comprising silicon) with a charge coupled device (CCD) channel 2a.
  • the charge coupled device channel 2a comprises a portion of the substrate 2 which underlies a plurality of clocked CCD electrodes 3 including a gate modulation electrode 3a.
  • An input diffusion 5 of a conductivity type opposite from that of the substrate 2 is formed in the substrate at the beginning of the CCD channel 2a.
  • a DC (or FAT ZERO) level of current is injected beneath the gate modulation electrode 3a from the input diffusion 5 by means of a DC bias voltage source 7 connected through a high input impedance 9 to input diffusion 5.
  • the high input impedance 9 comprises a polycrystalline silicon resistor formed in the semiconductor substrate 1 which is doped to have a resistance on the order of 1 x 10 10 ohms. The high resistance of the polycrystalline silicon resistor 9 guarantees that the DC level of current injected from the input diffusion 5 beneath the modulation gate electrode 3a will be uniform between adjacent CCD channels (not shown) despite the CCD trans impedance non-uniformities.
  • An indium doped silicon detector 11 (of the same class of detectors so those disclosed in The Infrared Handbook referenced above at pages 11-13 through 11-98) is formed on the substrate 1. It is biased by a bias voltage source 13 and has its output connected through a coupling capacitor 15 to the electrode 3a in the manner of AC coupled gate modulation illustrated in The Infrared Handbook referenced above at FIG. 12-42.
  • a reset MOSFET 17 periodically resets the potential of the gate modulation electrode 3a to that of a reset voltage source 18.
  • the polycrystalline silicon load resistor 19 has the additional advantage of rendering the gain of the device independent of processing non-uniformities.
  • the gain between the detector output and the CCD output current of the device of FIG. 1 is the ratio of the resistances of the resistors 9 , 19.
  • the gain ratio R L /R S is easily controlled during fabrication and will therefore be uniform for a plurality of CCD channels (not shown) located on a focal plane array formed on the semiconductive substrate 1.
  • the polycrystalline silicon resistor 9 provides an extremely high input impedance, guaranteeing that the dc current level injected into the plurality of charge coupled devices of the type illustrated in FIG. 1 located on the same semiconductive substrate will be uniform despite processing non-uniformities.
  • the polycrystalline silicon resistor 19 provides an extremely high load impedance for the detector 11 so that the gain between the CCD output current and the photodetector response may be selected in accordance with the resistances of the resistors 9 , 19 thus providing sufficiently high gain to reduce the significance of CCD noise in the output signal and rendering the gain ratio of each device 1 in an array of such devices 1a-1n independent of processing non-uniformities.
  • the output of the detector 11 may be connected directly to the gate modulation electrode 3a (as indicated in dashed line) while the coupling capacitor 15 and the reset MOSFET 16 may be eliminated if AC coupling is not necessary.
  • AC coupling may not be necessary, for example, if background radiation incident upon the detector 11 is of a constant intensity.
  • the voltage source 7 is selected in a manner well-known to those skilled in the art so that the modulation of the signal generated by the detector 11 and superimposed on the DC current level flowing in the CCD does not exceed the dynamic range of the CCD.
  • the bias voltage source 13 of the indium doped silicon detector 11 is preferably on the order of -40 volts.
  • the reset voltage source 18 may be on the order of 2 volts.
  • the detector 11 may be of any type, either intrinsic or extrinsic, disclosed in The Infrared Handbook referenced above between pages 11-13 and 11-98.
  • the gate modulation electrode 3a need not necessarily overlie a charge coulped device but instead may overlie any type of charge transfer device.
  • Gerzberg "A Quantitative Model of the Effect of Grain Size on the Resistivity of Polycrystalline Silicon Resistors," IEE Electron Device Letters, Vol. EDL-4, No. 3, p. 38 et seq. (March 1980).

Landscapes

  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Photometry And Measurement Of Optical Pulse Characteristics (AREA)
EP19820900203 1980-12-01 1981-12-01 Gate modulation input circuit with polycrystalline silicon resistors. Withdrawn EP0065571A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US21149380A 1980-12-01 1980-12-01
US211493 1980-12-01

Publications (2)

Publication Number Publication Date
EP0065571A1 EP0065571A1 (en) 1982-12-01
EP0065571A4 true EP0065571A4 (en) 1985-03-06

Family

ID=22787141

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19820900203 Withdrawn EP0065571A4 (en) 1980-12-01 1981-12-01 Gate modulation input circuit with polycrystalline silicon resistors.

Country Status (4)

Country Link
EP (1) EP0065571A4 (enExample)
JP (1) JPS57502029A (enExample)
IT (1) IT8149780A0 (enExample)
WO (1) WO1982001962A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4689487A (en) * 1984-09-03 1987-08-25 Kabushiki Kaisha Toshiba Radiographic image detection apparatus
NL8501542A (nl) * 1985-05-30 1986-12-16 Philips Nv Ladingsgekoppelde inrichting.
US4896340A (en) * 1985-11-01 1990-01-23 Hughes Aircraft Company Partial direct injection for signal processing system

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3660697A (en) * 1970-02-16 1972-05-02 Bell Telephone Labor Inc Monolithic semiconductor apparatus adapted for sequential charge transfer
DE2501934C2 (de) * 1974-01-25 1982-11-11 Hughes Aircraft Co., Culver City, Calif. Verfahren zum Betrieb eines ladungsgekoppelten Halbleiter-Bauelementes und ladungsgekoppeltes Halbleiter-Bauelement zur Durchführung dieses Verfahrens
JPS5513426B2 (enExample) * 1974-06-18 1980-04-09
US4110776A (en) * 1976-09-27 1978-08-29 Texas Instruments Incorporated Semiconductor integrated circuit with implanted resistor element in polycrystalline silicon layer
US4275407A (en) * 1977-09-01 1981-06-23 Honeywell Inc. Durable insulating protective layer for hybrid CCD/mosaic IR detector array
US4297721A (en) * 1978-11-03 1981-10-27 Mostek Corporation Extremely low current load device for integrated circuit
US4210465A (en) * 1978-11-20 1980-07-01 Ncr Corporation CISFET Processing including simultaneous implantation of spaced polycrystalline silicon regions and non-memory FET channel
US4232221A (en) * 1979-01-22 1980-11-04 The United States Of America As Represented By The Secretary Of The Air Force Method and apparatus for trimming IR/CCD mosaic sensors
US4291328A (en) * 1979-06-15 1981-09-22 Texas Instruments Incorporated Interlevel insulator for integrated circuit with implanted resistor element in second-level polycrystalline silicon

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
INTERNATIONAL ELECTRON DEVICES MEETING, Washington D.C., December 3,4,5 1979; I.E.E.E., Digest of Technical Papers USA); M.N. GURNEE: "Detector/CCD coupling for hybrid focal planes", pages 552-555. *

Also Published As

Publication number Publication date
IT8149780A0 (it) 1981-11-27
JPS57502029A (enExample) 1982-11-11
EP0065571A1 (en) 1982-12-01
WO1982001962A1 (en) 1982-06-10

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Legal Events

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PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

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Designated state(s): DE FR GB

17P Request for examination filed

Effective date: 19821127

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18D Application deemed to be withdrawn

Effective date: 19850701

RIN1 Information on inventor provided before grant (corrected)

Inventor name: GATES, JAMES L.

Inventor name: BACKENSTO, WILLIAM V.