EP0057663B1 - Steuervorrichtung für einen Schrittmotor - Google Patents

Steuervorrichtung für einen Schrittmotor Download PDF

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Publication number
EP0057663B1
EP0057663B1 EP82810023A EP82810023A EP0057663B1 EP 0057663 B1 EP0057663 B1 EP 0057663B1 EP 82810023 A EP82810023 A EP 82810023A EP 82810023 A EP82810023 A EP 82810023A EP 0057663 B1 EP0057663 B1 EP 0057663B1
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EP
European Patent Office
Prior art keywords
coil
signal
control
motor
voltage
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EP82810023A
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English (en)
French (fr)
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EP0057663A2 (de
EP0057663A3 (en
Inventor
Jean-Claude Berney
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Koninklijke Philips NV
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Philips Gloeilampenfabrieken NV
Koninklijke Philips Electronics NV
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Publication of EP0057663A3 publication Critical patent/EP0057663A3/fr
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04C—ELECTROMECHANICAL CLOCKS OR WATCHES
    • G04C3/00—Electromechanical clocks or watches independent of other time-pieces and in which the movement is maintained by electric means
    • G04C3/14—Electromechanical clocks or watches independent of other time-pieces and in which the movement is maintained by electric means incorporating a stepping motor
    • G04C3/143—Means to reduce power consumption by reducing pulse width or amplitude and related problems, e.g. detection of unwanted or missing step

Definitions

  • the present invention relates to control devices for stepping motors.
  • stepper motors the analysis of the voltage induced in the driving coil by the displacement of the rotor makes it possible to know the behavior of the motor when it takes a step.
  • This analysis can be useful both for the realization of motor control and servo-control circuits, in particular those which make it possible to adapt the duration of the driving pulses applied to it to its load, as well as at the level of devices for measuring parameters of this motor such as useful torque, current consumed, etc., or to check its correct operation.
  • Patent application FR-A-2,410,843 recommends a control circuit for controlling stepping motors used in watchmaking.
  • the circuit is provided with an oscillator to generate time base signals. From these signals are deduced control pulses.
  • the motor coil is energized, causing the motor to take a step.
  • the voltage induced in the motor coil is determined to detect whether the motor has actually taken a step. Under these conditions, the motor coil is alternately short-circuited and charged by means of a series resistor. The voltage across the resistor is indicative of the induced voltage.
  • the object of the invention is in particular to provide a control device for a stepping motor capable of supplying, during the duration of the driving pulses which are applied to it, precise information on the voltage induced in the coil by the movement of the rotor.
  • the invention also proposes to provide a control device making the operation of the engine independent.
  • a control device of a stepping motor provided with a coil having two terminals and a rotor performing a rotational movement when the coil is traversed by a current, comprising means for producing, in response to time base signals, motor control pulses, as well as switching means responsive to said control pulses for connecting a first terminal of the coil to a first pole of a DC voltage source and the second terminal from the coil to the second pole of the DC voltage source, or vice versa, characterized in that it comprises means for periodically comparing, during each control pulse, the current in the coil with a constant reference value, means for providing a control signal when the current in the coil is greater than said constant reference value, and means responding to said control signal to control the mo switching yen in order to cut the connection of the coil to the first pole of the DC voltage source and to connect the two terminals to the second pole of said DC voltage source.
  • the control signal includes information on the voltage which, under the effect of the movement of the rotor, is induced in the coil during command pulse.
  • An analysis circuit makes it possible to deduce from this control signal a digital analysis signal representative of said induced voltage.
  • the analysis means can be designed to also provide information on the voltage value across the resistance of the coil. In addition, it is possible to provide the device
  • the various results can then be used to control the motor control so as to reduce the energy consumption, for example by interrupting the driving pulse when the rotor has taken its step or by controlling the duration of the driving pulse in function variations in engine load. It is also possible, for example, to determine if a step has not been taken and to correct this error by sending an additional high-energy driving pulse to force the passage of the rotor.
  • the constant current power supply also has the advantage of to reduce the number of turns of the coil by increasing the diameter of the wire accordingly, or an interesting gain on the price of the coil.
  • the invention also makes it possible to provide a solution to this problem by producing a stepping motor control device in which the means for supplying the motor which comprise switching means for connecting the coil to a supply voltage source and for short-circuiting said coil also comprise means for periodically comparing, during each motor control pulse, the current in the coil with a reference value and supplying a control signal for controlling the switching means, in order to short-circuit the coil when, during a comparison, the current exceeds the reference value and supplying the coil with voltage if the current is less than this value, this until the next comparison, so as to maintain the average value of the current at the reference value for the duration of the control pulses.
  • the reference value can be chosen as a function of the threshold voltage of an MOS transistor, independent of the supply voltage.
  • the voltage across the coil, during the control pulses, is thus composed of a succession of supply periods interspersed with short-circuit periods which form logic information representative of the induced voltage.
  • the signal present at the terminals of the coil can be picked up either by a galvanic link on a motor terminal, or without contact, for example inductively by a pick-up coil and analyzed by circuits external to the control device. This makes it possible to determine the parameters relating to the operation of the engine without any intervention inside the control device, which is particularly advantageous for checks during or at the end of manufacture and during repairs.
  • FIG. 1 represents the equivalent electrical diagram of a bipolar single-phase stepper motor of the Lavet type commonly used in watchmaking
  • FIG. 2 shows the voltage curves of FIG. 1 for driving pulses at constant voltage
  • FIG. 3 shows the curves of the voltages of figure 1 for driving pulses with constant current.
  • This type of motor essentially includes a choke its own, a coil resistance and a voltage generator at the terminals of which appear the voltages of self U L , of resistance U R and the voltage Ui induced in the coil by the displacement of the rotor. The sum of these three voltages is equal to the voltage Ub across the coil.
  • FIG. 2 represents the distribution of the components U L , Ui and U R during the driving pulse.
  • FIG. 4 shows by way of example the diagram of a control circuit of the device according to the invention, circuit making it possible to maintain the current in the coil at a value fixed during the duration of the control pulses of the advance of the motor.
  • a quartz oscillator 10 delivers a 32 kHz signal to the clock inputs a of a frequency divider 11 and of a type D flip-flop, 12, operating as a monostable.
  • the output Q (b) of this flip-flop is connected by a resistor 13 to its reset input (c) and to a capacitor 14 connected against ground.
  • the flip-flop 12 each time the flip-flop 12 goes to the logic state "1", the capacitor 14 charges through the resistor 13 and the reset occurs after a certain delay which is chosen to be of very short value (2 ⁇ s).
  • the flip-flop 12 therefore delivers fine pulses with a duration of 2 ⁇ s at a repetition frequency of 32 kHz when its input D (e) is at "1".
  • the divider 11 delivers signals of frequency 8 kHz on its output b, 4 kHz on its output c, 2 kHz on its output d, 1 kHz on its output e, 64 Hz on its output f, 32 Hz on its output g and 0.5 Hz on its output h.
  • the latter is connected to the clock input a of flip-flop of type D, 15, and through an inverter 17 at the clock input a of another flip-flop of type D, 16.
  • the inputs D (b) of flip-flops 15 and 16 are maintained at state "1" while their reset inputs (c) are connected to the output of an OR gate 18 whose input a is connected to the output g (32 Hz) of the divider 11.
  • the flip-flops 15 and 16 take turns, one on the positive side of the signal O, 5 Hz on the output h of the divider 11, the other on the negative side of this same signal, pulses to control the engine advance. It is the 32 Hz output (g) of the divider which, through gate 18, carries out the reset of flip-flops 15 and 16 and thus determines the duration of the control pulses, ie 16 ms.
  • the outputs d of the flip-flops 15 and 16 are connected to the inputs b and a of an OR gate 20, to the inputs a of two NAND gates 21 and 22, as well as to the control inputs of two analog switches 23 and 24.
  • the output of gate 21 is connected to the gate of a P-MOS transistor of power 25 and to the input a of an AND gate 26, the output of which is connected to the gate of an N-MOS transistor. of power 27.
  • the output of gate 22 is connected to the gate of a P-MOS transistor of power 28 and to the input a of an AND gate 29 the output of which is connected to the gate of a transistor N - Power MOS 30.
  • the sources of the P-type transistors 25 and 28 are connected to the positive pole of the electrical supply source and the sources of the N-type transistors 27 and 30 to the negative pole of this source.
  • the drains of transistors 27 and 25 are connected to terminal a of the motor coil 31, and the drains of transistors 28 and 30 to terminal b of this coil.
  • These power transistors 25, 27, 28 and 30 form switching means making it possible either to connect the coil to the terminals of the electrical supply source, or to short-circuit this coil.
  • the flip-flop 15 delivers a control pulse
  • the outputs of the gates 21 and 26 change to "0".
  • the transistor 27 is cut off and the transistor 25 becomes conductive, connecting the terminal a of the coil 31 to the positive pole of the power source.
  • the current flows in the meaning a - b.
  • the switch 23 When a pulse arrives at the output of the flip-flop 15, the switch 23 becomes conductive, so that a resistor R1 and the gate of an N-MOS transistor 32 are connected in parallel with the power transistor 30.
  • the entry D (e) of the flip-flop of type D, 12 passes to "1", and this one delivers on its exit Q (d) very fine negative pulses of duration 2 ⁇ s at the frequency of 32 kHz which are transmitted by the gate 29 on the gate of the transistor 30, which periodically blocks this transistor, for very short moments. Since the current in the coil 31 can no longer flow in this transistor 30, it then passes entirely through the resistor R1, causing an increase in the voltage on the gate of the N-MOS transistor 32.
  • the output of amplifier 34 is connected to input D (a) of a type D flip-flop, 35, whose clock input (b) is connected to the output Q (d) flip-flop 12 delivering negative test pulses.
  • the flip-flop 35 records the state of its input D and thus stores the state at the output of the amplifier 34, depending on the level of current in the coil.
  • the power supply to the coil is interrupted and short circuit restored to its terminals each time the discriminator delivers a signal corresponding to the condition that the current in the coil is greater than the fixed value, which produces a state "0" on the output c of the flip-flop 35. Conversely each time the output of the discriminator remains at "0", which corresponds to the condition that the current in the coil is less than the fixed value, the output c of the flip-flop 35 comes to "1" and the power supply of the driving coil 31 by the transistor 25 is restored, the transistor 27 being cut off.
  • the voltage Ub across the coil is given by where L is the self-induction of the coil 31.
  • the voltage Ub is equal to the supply voltage V:
  • the voltage Ub is equal to 0:
  • FIG. 5 shows a comparison between the form of current Ic delivered by the power supply in the case (5a) where the coil is supplied with constant voltage and in the case (5b) where the coil is supplied with constant current by the device according to the invention. in constant current by the device according to the invention.
  • the current decreases when the induced voltage increases and vice versa.
  • the current at the end of the control pulse tends to its maximum value.
  • FIG. 6 represents by way of example the block diagram of a circuit for analyzing the sequence of logic states delivered by the control circuit of FIG. 4, a circuit making it possible to determine the ratios Ui / V and U R / V.
  • This circuit is connected to the control circuit of FIG. 4 by the points P1 (test pulses), P2 (test), P3 (motor control pulses) and P4 (end of motor control pulses).
  • the point P2 which corresponds to the output of the level discriminator and to the input D (a) of the flip-flop 35, is connected to the input D (a) of a transfer register 40 of 16 stages, at the clock input of a type D flip-flop, 41, and at inputs a of an EXCLUSIVE gate 42 and a NOR gate 43.
  • the point P1 which delivers fine pulses of 2 ⁇ s of duration at 32 kHz on the clock input b of the flip-flop 35 is connected to the clock input b of the register 40 and to the clock inputs a of two type D flip-flops, 44 and 45 .
  • the point P3 which corresponds to the output of door 20 on which positive pulses appear for each motor control pulse, pulses delivered either by the flip-flop 15 or by the flip-flop 16, is connected to the input d 'an inverter 46 whose output is connected to the reset inputs c of register 40, b of the type D flip-flop, 41 and to another type D flip-flop, 47.
  • the register 40 and the flip- Flops 41 and 47 are therefore only operational for the duration (max. 16 ms) of the motor control pulses since they are kept at "0" between these pulses.
  • This sequence of states is transmitted with a delay period on the door Q of the second stage of register 40 with two periods of delay on the output Q from the third floor, etc. and with 15 periods of delay on the exit Q (e) of the 16th stage of register 40.
  • This register 40 thus permanently stores the last 16 periods of the sequence of logic states, ie a duration of 0.5 ms.
  • the start of this first group begins as soon as the current in the coil reaches the setpoint Io, ie as soon as the test input (P2) changes to "1" and the output Q from the first stage of the register to "0".
  • the end of this first group of 16 periods corresponds to the moment when this state "0" on the output Q of the first stage arrives at the last stage of the register, that is to say when the exit Q 15 (e) of register 40 in turn goes to "0" for the first time, the output Q15 (d) passing, to "1".
  • the output Q (e) of the flip-flop 47 is at "0".
  • the output of gate 43, ie input b of flip-flop 44 comes to "1” each time input P2 comes to “0".
  • the "test pulses” on P1 simultaneously attack the clock inputs of flip-flop 44 and register 40, so that the output Q (c) of flip-flop 44 changes to "1” each time the first stage of register 40 registers a state "1" on its output Q .
  • the output c of the flip-flop 44 returns to "0” as soon as the resistor 48 has charged the capacitor 49 and actuated the reset.
  • This output c of the flip-flop 44 therefore delivers a pulse to the clock input (a) of a counter 50, for each state "1" of the sequence of logic states delivered by the control circuit of FIG. 4.
  • the reset input R (b) of the counter 50 is connected to the output Q (e) of flip-flop 41 which goes to "0" at the start of the first group representative of 16 periods, so that the counter 50 is kept at 0 until the start of this first group.
  • the flip-flop 47 changes to "1", which blocks at "0” the input D (b) of the flip-flop 44 which therefore ceases to deliver pulses on its exit.
  • the counter 50 starting from 0, counts and stores the number of states "1" which are in the first group representative of 16 periods. Its state, represented by the binary combination present on its outputs Q0 (c), Q1 (d), Q2 (e) and Q3 (f), is equal to the ratio U R / V.
  • the output Q 15 (d) of the register 40 is connected to the input b of an EXCLUSIVE gate 42 whose output is connected to the input D (b) of the flip-flop 45 connected as a monostable, its output Q (c) being connected to its reset input (d) by a resistor 51, also connected to a capacitor 52, the second terminal of which is connected to ground.
  • the input D of the flip-flop 45 is at "1" each time the input P2 and the output Q 15 of the register are in different states, that is to say each time the number of states " 1 "in register 40 should change.
  • the flip-flop 45 goes to "1" at the next test pulse on P1 and delivers a pulse to the clock input a of a reversible counter 53.
  • This counter 53 therefore receives a pulse each once the number of states "1" contained in register 40 is increased or decreased by one.
  • the counting direction of the counter 53 is determined by the state of the input U / D of the counting direction (b) which is connected to the output Q 15 (d) of the register 40.
  • the counter 53 is incremented by one unit when this Q 15 output is at "1", that is to say when the number of states "1" in the register increases by one unit, and conversely it is decremented by one unit when the Q 15 output from the register 40 is at "0", that is to say when the number of states "1” in the register decreases by one.
  • these are the states of the outputs Q stages of register 40 which are taken into account to form the sequence of logical states representing the ratio (U R + Ui) / V. Indeed, it is necessary, at the start of the motor control pulse, to have only states "1" in the register, which is obtained by actuating the reset and taking into account the exits Q .
  • the input D (b) of the flip-flop 45 is at "0" and therefore it cannot deliver a clock pulse to the counter 53.
  • the reset input c of this counter 53 is connected to the output Q (d) of flip-flop 47 which changes to "0" at the end of the first group representative of 16 periods, ie when U R / V has been stored in counter 50.
  • the counter 53 therefore starts from 0 at the end of this first group of 16 periods and its state, represented by the binary combination present on its outputs Q0, Q1, Q2 and Q3 (d, e, f, g), is equal to the ratio Ui / V.
  • the circuit of FIG. 7 comprises a logic comparator 60 which receives on its inputs A the output signals 1 kHz, 2 kHz, 4 kHz and 8 kHz from the divider 11 of FIG. 4 and on its inputs B the output signals Q0, Q1, Q2 and Q3 of the counter 53 in FIG. 6, outputs on which the digital signal represents the value of the Ui / V ratio.
  • Signal A consists of a sequence of 16 logic states, 0000 to 1111, of 4 bits each, with a period of 1 ms imposed by the signal of 1 kHz.
  • Signal B which is proportional to the induced voltage Ui in the driving coil during a step, that is to say during a control pulse (max. Duration 16 ms), can be considered as constant for the duration of the 1 ms period of signal A.
  • comparator 60 delivers pulses of 8 kHz each millisecond at its output, and this as long as the binary value of signal B exceeds the binary value of signal A. In other words, the number of 8 kHz pulses delivered each millisecond at its output by comparator 60 is equal to Ui / V.
  • the output of comparator 60 is connected to the input a of an AND gate 61, the input b of which is connected to the 16 kHz output of the divider 11 in FIG. 4.
  • the gate 61 therefore lets each millisecond pass through its output a number of periods of the 16 kHz signal equal to the value of Ui.
  • This output is connected to the clock input a of a programmable divider 62, the reset input b of which is connected to point P5 (reset) in FIG. 6, so that this divider 62 does not work. only during the duration (max. 16 ms) of the motor control pulses.
  • the programming inputs of the divider 62 are connected to the doors Q0, Q1, Q2 and Q3 of the counter 50 of FIG. 6, representing the value of U R / V, so that the division rate of the divider 62 is equal to the ratio U R / V.
  • Ui / V number of signals delivered at the output of gate 61 each millisecond.
  • U R / V division rate of divisor 62.
  • the output of the divider 62 is connected to the clock input a of a counter 63, the reset input b of which is connected to point P5 in FIG. 6.
  • This counter 63 starts from 0 at the start of the motor control pulse and its content, represented by the states of its outputs Q0 to Q3 is representative of the integral ⁇ Ui.dt, value proportional to the energy received and delivered by the motor.
  • the content of the counter 63 can itself be compared, using a comparator 64, to a set value.
  • the outputs of the counter 63 are connected to the inputs B of a comparator 64 whose inputs A receive the set value.
  • the output B> A of comparator 64 can then be used for example to interrupt the motor control pulse.
  • control circuits cannot be dissociated from the control circuit.
  • the control circuits of FIG. 4 and the control circuits of FIGS. 6 and 7 would be incorporated into the integrated circuit of the watch, which is why these control circuits must be relatively simple and inexpensive.
  • FIG. 8 is shown a second embodiment of a device using a pick-up coil to detect the signals emitted by the driving coil and to reconstruct using these the sequence of logic states produced by the circuit. . This makes it possible, for example, to check an already fitted watch and the motor terminals of which are inaccessible.
  • FIG. 8 is shown the coil 70 of the motor and the sensing coil 71 of the device.
  • the driving coil 70 transmitting coil
  • the all-or-nothing signals with very steep sides of the sequence of logic states to be reconstructed. These steep sides can be detected by deriving the signal picked up by the coil 71, by means of a capacitor 72 connected to the input of an inverting amplifier 73, and of a resistor 74 connected between the capacitor 72 and the output of amplifier 73.
  • this amplifier At the output of this amplifier appear positive or negative pulses.
  • the polarity of these pulses depends on the direction of the current in the drive coil and the position of the pickup coil relative to the motor coil. It is therefore not possible to certify that a positive pulse corresponds to the establishment of the current in the coil and vice versa.
  • the positive pulses at the output of amplifier 73 are amplified by an NPN transistor 75, the base of which is connected to the output of amplifier 73 by a capacitor 76 and to ground by a resistor 77.
  • the collector of the transistor 75 is connected to the positive pole of the power supply by a resistor 78 and to the input of an inverter 79.
  • transistor 75 becomes conductive and produces a negative pulse on its collector at the input of inverter 79.
  • the output of inverter 79 delivers a positive pulse at input a of an OR gate 80, of which the output also delivers a positive pulse.
  • the negative pulses at the output of the amplifier 73 are amplified by a transistor 81 of PNP type, the base of which is connected to the output of the amplifier 73 by a capacitor 82 and to the positive pole of the power supply by a resistor 83
  • the collector of transistor 81 is connected to ground (negative pole of the power supply) by a resistor 84 and to input b of the OR gate 80.
  • the transistor 81 becomes conductive and produces a positive pulse on its collector, the output of the gate 80 also delivering a positive pulse.
  • This circuit allows in a way to "rectify" the pulses delivered by the amplifier 73, the output of the gate 80 delivering a positive pulse for each pulse at the output of the amplifier 73, whatever its polarity.
  • These pulses make it possible to synchronize an internal generator comprising in this example a high frequency generator (4 MHz) 85 and a divider 86 delivering inter alia a signal of 32768 kHz which is synchronized with the internal generator of the watch by the fact that the output of door 80 is simply connected to the reset input of this divider 86.
  • the output of door 80 is also connected to the clock input a of a D-type flip-flop, 87, operating in binary divider by 2, its output Q being connected to its input D (c).
  • FIG. 9 A last interesting aspect of the device according to the invention is described in FIG. 9. It relates to the possibility of programming at will the reference current Io fixing the tripping level of the discriminator of the current level in the driving coil. This can be done simply by replacing the resistor R1 in FIG. 4 with a programmable current source, such as that which is represented in FIG. 9.
  • This device comprises a circuit delivering a reference current formed by transistors of the P-MOS 90 and 91 type.
  • the source of the P-MOS transistor 90 is connected to the positive pole of the power supply, its drain is connected to ground by a resistor. of great value 92 and at the gate of the P-MOS type transistor, 91; its gate is connected to the positive pole of the power supply by a resistor R2 and to the source of transistor 91.
  • the drain of transistor 91 is connected to the gate and to the drain of an N-MOS, To type transistor, the source is connected to ground.
  • the P-type transistors 90 and 91 form a regulator maintaining the voltage across the resistor R2 equal to the threshold voltage V T of the transistor 90.
  • the transistor T1 delivers a current I R , the transistor T2 a current 2 I R , and the transistors T4 and T8 of the respective currents 4 I R and 8 I R.
  • the drain of transistor T1 is connected to the source of an N-MOS type transistor 96 whose gate is connected to the output Q0 (a) of a reversible counter 97.
  • the drain of the N-MOS type transistor T2 is connected to the source of the N-MOS type transistor 95 whose gate is connected to the output Q1 (b) of the counter 97.
  • the drain of the N-MOS type transistor, T4 is connected to the source of a transistor of the N-MOS 94 type, the gate of which is connected to the output Q2 (c) of the counter 97 and the drain of the N-MOS type transistor, T8, is connected to the source of an N-MOS type transistor 93 of which the grid is connected to the output Q3 (d) of the counter 97.
  • the drains of the type transistors N-MOS 93 to 96 are connected together at the common point P6. These transistors 93, 94, 95 and 96 act as switches, allowing the currents delivered respectively by the transistors T8, T4, T2 and T1 to pass, when their gate is at "1".
  • the circuit of FIG. 9 is therefore indeed a programmable current source. By replacing the resistor R1 in FIG. 4 with this current source, it is therefore possible to program the current level in the drive coil as desired. It is obvious that the grids of the transistors 93, 94, 95, 96 could also be connected to the outputs of any type of memory (ROM, RAM, REPROM, etc.).
  • the reversible counter 97 has been used to show that the programming of the current Io can be used in a complementary servo system making it possible to dose exactly the number of ampere-turns necessary for the motor rotor to to take his step in a determined time.
  • the clock input e of the counter 97 is connected to the output of an inverting amplifier 98, the input of which receives the motor control pulses on P3 in FIG. 4, the U / D input for controlling the counting direction (f) of the counter 97 receiving a signal of 64 Hz from the divider 11 of FIG. 4.
  • the system includes the circuit of FIG. 6, making it possible to interrupt the motor control pulse when the step is taken. The duration of this control pulse is therefore variable and it represents the time necessary for the rotor to perform its pitch.
  • the command pulse has a duration of 6 ms.
  • the 64 Hz signal on the U / D input changes to "1" after 8 ms, the counter 97 changes at the end of the motor control pulse on its clock input, that is to say when the U / D input is still at "0".
  • the counter then counts a step, its content decreasing by one, as well as the current Io.
  • the U / D input is always at "0" and the counter counts down a new step so that the current Io decreases by one more.
  • the rotor On the next command pulse, the rotor will therefore take even longer to take its step, 8.5 ms for example.
  • the U / D input has changed to "1".
  • the counter therefore advances by 1 step and the current increases by one unit, so that the duration of the next step will be shortened, the number of ampere-turns and consequently the cut of the motor being increased. It is therefore an automatic stabilization of the duration of the control pulse, and consequently of the rotor passage time, around 8 ms, and this also in the event of variations in the load torque of the motor. .

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  • General Physics & Mathematics (AREA)
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Claims (16)

  1. Steueranordnung für einen Schrittmotor, der eine Spule (31) mit zwei Anschlußklemmen und einen Läufer besitzt, der bei Stromdurchfluß durch die Spule (31) eine Drehbewegung ausführt, wobei diese Steuervorrichtung Mittel (15, 16) zum Erzeugen von Motorsteuerimpulsen in Beantwortung von Zeitbasissignalen sowie Schaltmittel (25, 27, 28, 30) enthält, die zum Verbinden einer ersten Anschlußklemme (a oder b) der Spule (31) mit einem ersten Pol einer Gleichspannungsquelle und der zweiten Anschlußklemme (b oder a) der Spule mit dem zweiten Pol der Gleichspannungsquelle oder umgekehrt auf die Steuerimpulse ansprechen, dadurch gekennzeichnet, daß die Anordnung Mittel (R1, 12, 23, 34, 35) zum periodischen Vergleichen des Stroms durch die Spule für die Dauer jedes Steuerimpulses mit einem konstanten Bezugswert, Mittel (34) zum Liefern eines Steuersignals, wenn der Strom durch die Spule den konstanten Bezugswert überschreitet, und Mittel (35, 21, 22, 26, 29) enthält, die auf das Steuersignal zum Steuern der Schalttmittel (25, 27, 28, 30) ansprechen, um die Verbindung der Spule (31) mit dem ersten Pol der Gleichspannungsquelle zu unterbrechen und dabei die zwei Anschlußklemmen mit dem zweiten Pol der Gleichspannungsquelle zu verbinden.
  2. Anordnung nach Anspruch 1, dadurch gekennzeichnet, daß sie außerdem Analysemittel (40-54) enthält zum vom Steuersignal Ableiten des Digital-Analysesignals als Darstellung der in der Spule (31) unter dem Einfluß der Bewegung des Läufers induzierten Spannung.
  3. Anordnung nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß das Steuersignal aus einer Folge erster und zweiter logischer Zustände besteht, wobei die ersten logischen Zustände dem entaktivierten Spulenzustand bei Verbindung der zwei Anschlußklemmen mit dem zweiten Pol der Gleichspannungsquelle und die zweiten logischen Zustände dem aktivierten Spulenzustand entsprechen, während die Analysemittel (40-54) zum Ableiten des Analysesignals von der (den) Anzahl(en) erster logischer Zustände ausgelegt sind, die in einem oder mehreren Abschnitten der Folge aufeinanderfolgender logischer Zustände vorhanden ist (sind).
  4. Anordnung nach Anspruch 3, dadurch gekennzeichnet, daß die Analysemittel derart ausgelegt sind, daß das Analysesignal den Wert (n+/n - no +/no) darstellt, worin n+/n die Anzahl erster logischer Zustände geteilt durch n aufeinanderfolgende logische Zustände der Reihe ist und no +/no die Anzahl erster logischer Zustände no + getielt durch no aufeinanderfolgende logische Zustände in einem Zeitintervall sind, wobei für die Dauer des Steuerimpulses oder nach dem Erreichen des Bezugswerts die durch die Läuferbewegung induzierte Spannung im wesentlichen gleich Null ist.
  5. Anordnung nach Anspruch 4, dadurch gekennzeichnet, daß das Zeitintervall sich am Anfang der Dauer des Steuerimpulses befindet.
  6. Anordnung nach Anspruch 4, dadurch gekennzeichnet, daß die Analysemittel (40-54) das Steuersignal empfangen und Speichermittel (40) aufweisen zum Speichern der logischen Zustände einer bestimmten Periodenanzahl des Steuersignals in Beantwortung der Zeitbasissignale, weiterhin erste Zählmittel (50) zum Zählen der Anzahl logischer Zustände in Beantwortung der Zeitbasissignale, wobei diese Anzahl dem entaktivierten Zustand der Spule bei Verbindung ihrer beiden Anschlußklemmen mit dem zweiten Pol der Gleichspannungsquelle in einer ersten Gruppe gespeicherter logischer Zustände entspricht, wobei die ersten Zählmittel (50) an ihren Ausgängen ein Digitalsignal zur Darstellung des Verhältnisses zwischen der Spannung infolge des Widerstandswerts der Spule (31) und der Speisespannung liefern, und zweite Zählmittel (53) aufweisen zum Zählen der zahlenmässigen Schwankungen in den logischen Zuständen entsprechend dem entaktivierten Zustand der Spule bei Verbindung ihrer beiden Anschlussklemmen mit dem zweiten Pol der Gleichspannungsquelle, und diese logischen Zustände im Speichermittel (40) enthalten sind, in Beantwortung der Zeitbasissignale enthält, und wobei diese zweiten Zählmittel (53) an ihren Ausgängen ein Digitalsignal liefern, das das Verhältnis zwischen der in der Spule (31) durch die Läuferbewegung induzierten Spannung und der Speisespannung darstellt.
  7. Anordnung nach Anspruch 6, dadurch gekennzeichnet, daß die ersten Speichermittel (40) ein Übertragunsregister enthalten.
  8. Anordnung nach Anspruch 6, dadurch gekennzeichnet, daß die zweiten Zählmittel (53) einen Vorwärts-Rückwärts-Zähler enthalten.
  9. Anordnung nach Anspruch 6, dadurch gekennzeichnet, daß sie ausserdem Mittel aufweist, die mit den zweiten Zählmitteln (53) zum Ausgeben eines Impulsendesignals verbunden sind, wobei das Verhältnis zwischen der induzierten Spannung und der Speisespannung einen bestimmten Wert hat, und Mittel zum Unterbrechen des Steuerimpulses in Beantwortung des Impulsendesignals enthält.
  10. Anordnung nach Anspruch 6, dadurch gekennzeichnet, daß sie ausserdem Mittel (60-64) aufweist zum Bestimmen der in einem Schritt vom Motor verbrauchten Energie.
  11. Anordnung nach Anspruch 10, dadurch gekennzeichnet, daß die Mittel (60-64) zum Bestimmen der in einem Schritt vom Motor verbrauchten Energie erste Vergleichsmittel (60) aufweisen zum Vergleichen des Verhältnisses zwischen der induzierten Spannung und der Speisespannung mit einem periodischen Digitalsignal, das aus einer logischen Verknüpfung wenigstens eines Teils der Zeitbasissignale gebildet wird, wobei die ersten Vergleichsmittel (60) ein Ausgangssignal liefern, wobei der Wert des periodischen Digitalsignals kleiner ist als der Wert dieses Verhältnisses, weiterhin Frequenzteilungsmittel (62), deren Teilungsverhältnis durch das Verhältnis zwischen der vom Spulenwiderstand bewirkten Spannung und der Speisespannung programmierbar ist, wobei die Frequenzteilungsmittel (62) in Beantwortung des Zeitsignals eine Anzahl von Signalen als Darstellung der vom Motor verbrauchten Energie liefern, und dritte Zählmittel (63) enthalten, die die Signale der Frequenzteilungsmittel (62) empfangen und an ihren Ausgängen ein Digitalsignal zur Darstellung der vom Motor bei jedem Steuerimpuls verbrauchten Energie liefern.
  12. Anordnung nach Anspruch 11, dadurch gekennzeichnet, daß sie ausserdem zweite Vergleichsmittel (64) aufweist zum Vergleichen des Digitalsignals zur Darstellung der verbrauchten Energie mit einem Sollwert, wobei die zweiten Vergleichsmittel (64) ein Impulsendesignal liefern, während der Wert des Signals zur Darstellung der verbrauchten Energie höher ist als der Sollwert, wobei das Impulsendesignal sich eignet zur Steuerung der Dauer der Steuerimpulse in Abhängigkeit vom Sollwert.
  13. Anordnung nach Anspruch 1, dadurch gekennzeichnet, daß sie Mittel (90-98, R2, T0, T1, T2, T4, T8) zum Programmieren der Bezugsgrösse enthält.
  14. Anordnung nach Anspruch 13, dadurch gekennzeichnet, daß die Mittel (90-98, R2, T0, T1, T2, T4, T8) zum Programmieren des Bezugswerts eine Bezugsspannungsquelle (90, 91, 92, R2, T0) enthalten, die eine Transistorgruppe (T1, T2, T4, T8) steuert, wobei diese Transistoren derart bemessen sind, dass sie entsprechend einer geometrischen Progression variierende Ströme liefern, wobei jeder der Transistoren (T1, T2, T4, T8) mit einem Schalttransistor (93, 94, 95, 96) mit einem Steuereingang und einem Ausgang in Reihe geschaltet ist, wobei die Ausgänge der Schalttransistoren (93, 94, 95, 96) mit einer gemeinsamen Klemme verbunden sind und die Steuereingänge dieser Schalttransisstoren mit einem der Ausgänge von Speichermitteln (97) verbunden sind, die an diesen Ausgängen ein Digitalsignal liefern, das den leitenden Zustand oder den gesperrten Zustand der Schalttransistoren (93, 94, 95, 96) derart bestimmt, dass die Summe der Ströme der Transistoren der Gruppe an der gemeinsamen Klemme für das Digitalsignal repräsentativ ist und daher durch dieses Digitalsignal programmiert ist, wobei die genannte Summe der Ströme an der gemeinsamen Klemme der Bezugswert ist.
  15. Anordnung nach Anspruch 14, dadurch gekennzeichnet, daß die Speichermittel (97) aus einem Vorwärts-Rückwärts-Zähler bestehen, der einen Takteingang aufweist, dem die Motorsteuerimpulse zugeführt werden, deren Dauer in Abhängigkeit von der Motorbelastung schwanken kann, sowie einen Zählrichtungssteuereingang aufweist, der ein Zeitbasissignal empfängt, das eine Periode in bezug auf die erforderliche Zeit für den Läufer zum Durchführen eines Schritts besitzt, wobei das Ausgangssignal des Vorwärts-Rückwärts-Zählers und daher der Wert des Bezugsstroms an der gemeinsamen Klemme abhängig sind von der relativen Dauer der Motorsteuerimpulse und von der Periode des Zeitbasissignals, wobei die Dauer des Steuerimpulses auf diese Weise in Abhängigkeit vom Wert der Periode des Zeitbasissignals und vom minimalen Energieverbruach gesteuert wird, sogar bei Schwankungen in der Belastung.
  16. Anordnung nach Anspruch 2, dadurch gekennzeichnet, daß ausserdem Mittel (70-89) vorgesehen sind, die mit den Analysemitteln zum Ausgeben eines Impulsendesignals gekoppelt sind, wenn die induzierte Spannung einen bestimmten Wert hat, und Mittel zum Unterbrechen der Speisung des Motors in Beantwortung des Impulsendesignals vorgesehen sind.
EP82810023A 1981-02-04 1982-01-21 Steuervorrichtung für einen Schrittmotor Expired - Lifetime EP0057663B1 (de)

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CH72581A CH647383GA3 (de) 1981-02-04 1981-02-04
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EP0057663A3 EP0057663A3 (en) 1982-08-18
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EP (1) EP0057663B1 (de)
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DE3280331D1 (de) 1991-06-13
EP0057663A2 (de) 1982-08-11
JPH0611197B2 (ja) 1994-02-09
EP0057663A3 (en) 1982-08-18
US4439717A (en) 1984-03-27
CH647383GA3 (de) 1985-01-31
JPS57148592A (en) 1982-09-13

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