EP0053487A1 - Appareil de test pour mesure de la temporisation des signaux - Google Patents

Appareil de test pour mesure de la temporisation des signaux Download PDF

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Publication number
EP0053487A1
EP0053487A1 EP19810305596 EP81305596A EP0053487A1 EP 0053487 A1 EP0053487 A1 EP 0053487A1 EP 19810305596 EP19810305596 EP 19810305596 EP 81305596 A EP81305596 A EP 81305596A EP 0053487 A1 EP0053487 A1 EP 0053487A1
Authority
EP
European Patent Office
Prior art keywords
flip
signals
flop
transistors
test apparatus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP19810305596
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German (de)
English (en)
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EP0053487B1 (fr
Inventor
Bruce C. Keene
Raymond E. Nielsen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Italia SpA
Honeywell Information Systems Inc
Honeywell Bull Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US06/211,162 external-priority patent/US4370574A/en
Priority claimed from US06/210,950 external-priority patent/US4370573A/en
Application filed by Honeywell Information Systems Italia SpA, Honeywell Information Systems Inc, Honeywell Bull Inc filed Critical Honeywell Information Systems Italia SpA
Publication of EP0053487A1 publication Critical patent/EP0053487A1/fr
Application granted granted Critical
Publication of EP0053487B1 publication Critical patent/EP0053487B1/fr
Expired legal-status Critical Current

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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means

Definitions

  • the present invention relates to test apparatus for measuring the time difference between two signals, paticu- larly signals which are cycled repeatedly.
  • Such apparatus is frequently required in the development and monitoring of digital electronic circuitry.
  • the primary need is often merely to determine which of two signals is the first to undergo a transition, but it is often desirable also to be able to measure the time interval between the two signals.
  • a clock oscillator and counter can be used, with gating circuitry which opens a gate to allow clock pulses into the counter when the first signal changes and closes the gate to freeze the count in the counter when the. second signal changes.
  • Another known technique is to use an oscilloscope, either a single trace oscilloscope with the trace triggered by one signal and showing the other, or a dual trace oscilloscope.
  • the known techniques generally involve a substantial amount of complex and expensive equipment. Also, when the time intervals to be measured are very small, in the sub- nanosecond range, some of the known techniques fail because they cannot cope with such speeds.
  • the object of the present invention is to provide test apparatus for measuring the time difference between two signals which is both simple and fast.
  • the present invention provides test apparatus for determining the time interval betwwen two signals, characterized by a pair of probes for picking up the two signals, circuitry for adjusting the polarities of levels of the signals, a pair of cross-coupled transistors, forming a simple flip-flop, input circuitry to the flip-flop to apply the signals to the flip-flop so as to cause the flip-flop to change from an initial abnormal state with both transistors in the same state to a normal state with the two transistors. in opposite states, detection circuitry fed from the two transistors to determine the difference between their outputs, and display means fed by the detection circuitry.
  • FIG. 1 shows the main units of the test apparatus.
  • Two probes 16 and 18 are attached to the two points at which the two signals, whose timings are to be compared, appear.
  • Two switches 20 and 21 select the probe outputs either direct or via level changing circuits 10 and 13, which are TTL to CML level shifters.
  • the switches 20 and 21 feed respective CML buffers 11 and 14, from which either the positive (direct) or negative (inverted, complemented) outputs can be selected by two more switches 22 and 23.
  • the two switches 22 and 23 feed a CML flip-flop circuit 12, which is the key to the signal comparison process.
  • This circuit 12 feeds a detection circuit 24, which in turn feeds a display unit 15 which displays an indication of the timing difference between the two signals.
  • a bias oscillator 20 which produces a sine wave output of frequency low compared to that of the signals being compared, is coupled to one input to the flip-flop 12.
  • a power supply 25 provides power for the remainder of the circuitry. In some circumstances, the circuitry can obtain its power supplies from the computer being tested instead of having its own independent power supply 25.
  • FIG. 2 shows the CML flip-flop 12 in detail. This comprises two transistors Q2 and Q3, cross-coupled and connected in series with two resistors R1 and R2 respectively as shown, to form a bistable circuit, together with two * input transistors Q1 and Q2 connected across Q2 and Q3 as shown.
  • This circuit is a very simple and primitive form of flip-flop, without any of the elaboration of input circuitry and clocking which is normally included in flip-flops as understood nowadays.
  • logical 1 is high, logical 0 is low.
  • the "normal” or quiescent state of the inputs to the flip-flop is both 0 (low). This means that Q1 and Q4 are both turned off.
  • the flip-flop can be in either of its two "normal” states: either Q2 on and Q3 off, or Q2 off and Q3 on.
  • a "normal” change of flip-flop state is accomplished by one or other, but not both, of the inputs going momentarily to 1. Say the input to Q1 goes briefly to 1. This turns on Q1, forcing the collector of Q1 and hence the base of Q3 low, and hence turning off Q3 and forcing the base of Q2 high, so turning on Q2. This forces the flip-flop to one of its two normal states, and it remains in that state when the input to Q1 goes back to 0.
  • signals Qlb and Q4b are the input signals applied to the bases of Q1 and Q4, and signals Q2c and Q3c are the signals appearing at the collectors of Q2 and Q3.
  • the input signals are both initially at 1; the full line graphs show what happens when the input to Q1 is the first to fall to 0, and the broken line graphs show what happens when the input to Q4 is the first to drop to 0.
  • the two inputs to the flip-flop are the two signals picked off by the probes 16 and 18. It is assumed that these two signals are both initially at 1, and it is required to determine which is the first to drop to 0. (If either or both is changing from 0 to 1, the CML buffers 11 and 14 can be used to invert them appropriately.) At time t0, when both have dropped to 0, the state of flip-flop 12 is dependent on which of the two signals was the first to change.
  • the detection circuit 24 is fed by the collectors of both transistors Q2 and Q3 of flip-flop 12 as shown, and forms the difference between the two voltages. This difference has a polarity dependent on the state of the flip-flop when the flip-flop is in either normal state, as indicated in Figure 3. Hence a positive voltage from circuit 24 indicates that the signal on probe 16 was the first to change, a negative voltage, that the signal on probe 18 was the first to change.
  • the display device 15 indicates the sign of this voltage.
  • the system under test will be cycling, and the signals picked up by the probes will return to 1 at some time after t0, probably (but not necessarily) in the same sequence that they went to 0.
  • the flip-flop 12 will then be forced back to the abnormal state, and will return to the normal state as soon as one or other of its input signal goes back to 0.
  • the output from the detection circuit 24 will probably be a pulse signal of one or other polarity.
  • This bias oscillator 20 provides a sinusoidal bias signal whose frequency is low compared to the cycle frequency of the system under test. This bias signal enables the time interval between the changes of the two signals being picked up by probes 16 and 18 to be measured, instead of merely the sign of this time interval being determined, as has been described so far.
  • a slow sine wave bias is used, as already stated.
  • the effect of this is shown in Figure 5.
  • the two signals V1 and V2 are shown cycling repeatedly.
  • the slow sine wave Vb carries the signal V1 up and down with respect to the critical voltage, so the instant at which the voltage ' V1 + Vb crosses the critical voltage will move relative to the instant at which the signal V2 crosses Vc.
  • the output Q2c - Q3c of the flip-flop 12 will consist of a series of positive pulses, as the flip-flop is repeatedly set to the same state on each signal cycle.
  • the flip-flop will be set to the other state, and its output will therefore be a series of pulses of the opposite polarity, until the bias voltage Vb drops back to the level where the change-over occurred.
  • the detection circuit 24 will therefore be fed with a signal somewhat as shown in Figure 5. It is evident that by smoothing this signal, a steady voltage can be obtained having a magnitude and polarity which indicate the magnitude and sign of the timing difference between the two signals V1 and V2.
  • the length of the output pulse from the flip-flop 12 is the time during which either of the two input signals is at 0. Hence as the relative timing of the two input signals is changed by the bias signal, so the length of the output pulses from the flip-flop 12 will change, increasing somewhat as the timings of the two signals move apart.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)
EP19810305596 1980-11-28 1981-11-26 Appareil de test pour mesure de la temporisation des signaux Expired EP0053487B1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US210950 1980-11-28
US06/211,162 US4370574A (en) 1980-11-28 1980-11-28 Detector for time difference between transitions in two wave forms
US06/210,950 US4370573A (en) 1980-11-28 1980-11-28 Wave form transition sequence detector
US211162 1980-11-28

Publications (2)

Publication Number Publication Date
EP0053487A1 true EP0053487A1 (fr) 1982-06-09
EP0053487B1 EP0053487B1 (fr) 1987-12-23

Family

ID=26905675

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19810305596 Expired EP0053487B1 (fr) 1980-11-28 1981-11-26 Appareil de test pour mesure de la temporisation des signaux

Country Status (4)

Country Link
EP (1) EP0053487B1 (fr)
AU (1) AU549448B2 (fr)
DE (1) DE3176582D1 (fr)
YU (1) YU279681A (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI381142B (zh) * 2006-02-08 2013-01-01 Sms Siemag Ag 用於加熱及／或熱平衡鋼或合金鋼之連續鑄造產物之輥道爐及其於熱條帶精軋機上游之設置
CN112947024A (zh) * 2019-12-10 2021-06-11 斯沃奇集团研究和开发有限公司 具有控制部件的表

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115047743B (zh) * 2022-08-16 2022-11-01 中国船舶重工集团公司第七0七研究所 一种基于反馈的用时端高精度时延补偿方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2962609A (en) * 1954-12-27 1960-11-29 Cons Electrodynamics Corp Pulse generator
US3509381A (en) * 1967-01-11 1970-04-28 Honeywell Inc Multivibrator circuit including output buffer means and logic means
US3534271A (en) * 1967-07-25 1970-10-13 Ryan Aeronautical Co Circuit for measuring the time differential between two pulses
GB1242855A (en) * 1967-11-01 1971-08-18 Joseph Kirkley Hourie Bi-stable trigger circuit
US3641443A (en) * 1969-12-11 1972-02-08 Westinghouse Electric Corp Frequency compensated pulse time discriminator

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2962609A (en) * 1954-12-27 1960-11-29 Cons Electrodynamics Corp Pulse generator
US3509381A (en) * 1967-01-11 1970-04-28 Honeywell Inc Multivibrator circuit including output buffer means and logic means
US3534271A (en) * 1967-07-25 1970-10-13 Ryan Aeronautical Co Circuit for measuring the time differential between two pulses
GB1242855A (en) * 1967-11-01 1971-08-18 Joseph Kirkley Hourie Bi-stable trigger circuit
US3641443A (en) * 1969-12-11 1972-02-08 Westinghouse Electric Corp Frequency compensated pulse time discriminator

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Instruments and Experimental Techniques, No. 1, January/February 1970, Plenum Publishing Corp. New York (US) S.S. KUZNETSKII et al.: "Phase-Metering Attachment for a Digital Frequency Meter" pages 156-159 * figures 1,3 * *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI381142B (zh) * 2006-02-08 2013-01-01 Sms Siemag Ag 用於加熱及／或熱平衡鋼或合金鋼之連續鑄造產物之輥道爐及其於熱條帶精軋機上游之設置
CN112947024A (zh) * 2019-12-10 2021-06-11 斯沃奇集团研究和开发有限公司 具有控制部件的表
CN112947024B (zh) * 2019-12-10 2022-04-12 斯沃奇集团研究和开发有限公司 具有控制部件的表
US11537082B2 (en) 2019-12-10 2022-12-27 The Swatch Group Research And Development Ltd Watch provided with a control member

Also Published As

Publication number Publication date
YU279681A (en) 1983-10-31
EP0053487B1 (fr) 1987-12-23
AU7690681A (en) 1982-06-03
AU549448B2 (en) 1986-01-30
DE3176582D1 (en) 1988-02-04

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