EP0032895A1 - Appareil d'essai pour systemes a base de microprocesseurs - Google Patents

Appareil d'essai pour systemes a base de microprocesseurs

Info

Publication number
EP0032895A1
EP0032895A1 EP79901509A EP79901509A EP0032895A1 EP 0032895 A1 EP0032895 A1 EP 0032895A1 EP 79901509 A EP79901509 A EP 79901509A EP 79901509 A EP79901509 A EP 79901509A EP 0032895 A1 EP0032895 A1 EP 0032895A1
Authority
EP
European Patent Office
Prior art keywords
bus
failure
signals
coupled
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP79901509A
Other languages
German (de)
English (en)
Other versions
EP0032895A4 (fr
Inventor
Edward Sneed Donn (Deceased)
Michael David Lippman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fluke Corp
Original Assignee
John Fluke Manufacturing Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by John Fluke Manufacturing Co Inc filed Critical John Fluke Manufacturing Co Inc
Publication of EP0032895A1 publication Critical patent/EP0032895A1/fr
Publication of EP0032895A4 publication Critical patent/EP0032895A4/fr
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G06F11/277—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault-free response

Definitions

  • ATE automatic testing equipment
  • a microprocessor-based board it is meant a general-purpose central processing unit (CPU) or a special purpose microprocessor-based process controller, or the like, which is assembled in a self-contained package such as one or several circuit boards and is characterized by input and output terminals, (board edge inputs and outputs), at least one microprocessor unit (MP ⁇ ), a bi-directional data and control bus coupled with the MPU, and at least some programmed logic functions (in either hardware or software form) , and which is capable of performing complex system functions and executing instructions according to "intelligent", i.e., programmed, decision criteria.
  • the invention is related to a technique for automatic operational (real-time) testing of a microprocessor-based board or system.
  • a difficulty in attempting to upgrade conventional ATE is the lack of facilities to automatical and sequentially search out and identify sources of error and locations of faults within a bus-connected operating system.
  • a second difficulty, which inhibits the diagnosi of faults, is the relatively limited access given the ATE the internal operation of the system.
  • the MPU-based boar or system with its minimum component count and minimum number control and data lines represents a tremendously advanced system design. But, when such a system works improperly, i.e., requires debugging, the complexity of t debugging problem can defy diagnosis by previously known trouble-shooting techniques. There is thus a need for improved techniques and devices for automatically testing microcomputer-based boards and systems.
  • Logic testers for some simple microprocessor-ba systems are also known. Fluke Trendar of Mountain View, California, manufactures a line of microprocessor board testers utilizing nodal signature diagnostic and real-tim comparative diagnostic techniques for testing of random logic boards, LSI-type boards and microprocessor-based boards.
  • One such representative system is the Model 3040A. Testers and techniques have also been developed capable of testing complex and irregular LSI devices in real time.
  • a representative system is offered by Megatest Corporation of Sunnyvale, California.
  • the level of complexity of a programmed microprocessor-based board exceeds the current capability of these or other ATE to thoroughly analyze and detect faults. For example, known spatial algorithms are incapable of locating faults which create errors propagated through a programmed bus-connected system. Therefore, with the increased availability and importance of microprocessor-based boards, there is an increased need for ATE capable of quickly and thoroughly diagnosing faults in complex programmed systems.
  • an automatic test apparatus is coupled to a bi-directional internal data, address and control bus of a programmed microprocessor-based system and tests the performance of a system in real time by direct comparison with a known good system (reference system) .
  • Signal responses on the bi-directional bus in the reference system are compared in real time to the unknown system, (system under test or test system), in order to sense failures.
  • Failures are isolated by monitoring the digital signals on the bi-directional bus, and, according to a sequential algorithm, stopping the test at the first occurrence of a failure, identifying the status of the bus at the occurrence of the failure, and directing a search for the source of the failure.
  • the technique is known as a "stop on first fail" algorithm.
  • the "stop on first fail” algorithm prevents a failure from propagating through a system which would otherwise make it impossible to locate the source of the fault.
  • the bi-directional bus is coupled to the microprocessor unit and acts as a sequentially time-shared "spinal cord" among subsystems communicating with the microprocessor unit.
  • the bus represents a tigh software/hardware feedback loop. According to the invention, therefore, the feedback loop is broken and th failure is traced by identifying the functional status o the bus and indicating the location of the failure throu automatic reference to the microprocessor memory map.
  • the principal object of this invention is to provide a means for automatically diagnosing faults of a programmed microprocessor-based board or system. This i accomplished by providing means for accessing and techni for monitoring the bi-directional data and control bus coupled to the MP ⁇ on the microprocessor-based board to locate operational failures..
  • a further object of the invention is to operat two microprocessor-based boards in parallel real time fo test purposes, one of which is a system under test (test system or SUT) . This is accomplished by stimulating bot the reference system (REF) and the SUT by peripherals (i and output devices) common to both systems or by a commo stimulus generator. In addition, means are provided for synchronously clocking the operation of both the REF and SUT.
  • REF reference system
  • peripherals i and output devices
  • a further object of the invention is to provide diagnostic algorithm for locating faults.
  • the algorithm operative to simultaneously stop the operation of the REF and the SUT at the first occurrence of non-coincident signals on the MP ⁇ bus.
  • the algorithm employs direct information, data information, and status information derived from the monitoring of all input and output terminals of the MPU and the memory map of- the SUT to loc and display the source of the failure.
  • a display may indicate which channel is the source of the error.
  • the t "channel" refers to that device corresponding to a particular memory address. A channel is identified from information obtained at the first failure and through the memory map.
  • a still further object important to the operation of the invention is to provide an ability in the tester itself to utilize key information fed to the MPU, and particularly to identify the status and operational mode of the bi-directional bus.
  • FIG. 1 is a block diagram of a tester according to the invention illustrating the testing equipment.
  • FIGs. 2A and 2B are together a detailed block diagram of the tester of Fig. 1.
  • Fig. 2C illustrates the manner in which Figs. 2A and 2B relate.
  • Figs. 2A, 2B and 2C are referred to collectively as Fig. 2.
  • Fig. 3 is a flow chart illustrating the sequential diagnostic algorithm according to the invention.
  • Fig. 4 is a circuit diagram according to the sequential diagnostic algorithm.
  • Fig. 5 is a circuit diagram of a preferred embodiment of the primary data collection functions according to the invention.
  • FIG. 1 illustrates a test system environment embodying the invention.
  • the environment includes a testing apparatus 10, a programmed computer system to be tested, "SUT” or “test system” 12, a system for comparison with the test system, "REF” or “reference system” 14, and operational peripheral devices 16 coupled through digital logic to the test system 12 and the reference system logic.
  • the peripheral devices 16 operate to stimulate both the test system 12 and the reference system 14 in synchronism.
  • the peripheral devices 16 may be input/output equipment actually used in an operational system, such as displays, keyboards, printers and sensors, or there may provided a stimulus generator which is operative to simu actual input/output signals.
  • Each system 12, 1 self-contained on a circuit board 15.
  • Each system 12, 1 comprises a digital central processing unit (CPU) 18, me 20, an input/output subsystem 22, interface logic 24 and directional (or three-state) data and control bus 26.
  • a clock 28 or clock input 30 is associated with each CPU 1
  • the memory 20 comprises a storage medium for digitized data and for an ordered set of operational instructions (a program) for the CPU 18.
  • the program may permanently resident in memory 20, for example, in the f of a read only memory, or it may be temporarily resident in a random access memory having read and write capabilities.
  • the CPU 18 compr a microprocessing unit which is generally provided in a single unit package (chip) with multiple terminals 30.
  • typical microprocessing unit chip has forty terminals. terminals 30 are coupled to the bi-directional bus 26.
  • the bus 26 is the main control and data information conduit of the programmed systems 12, 14, an is adapted to transmit information rapidly in both directions and in time-multiplexed format between subsys coupled thereto.
  • the programmed systems 12, 14 communicate with external environment through a further terminal set at t edge of the circuit board, often called a board edge connector 32.
  • the edge connector 32 couples with the sy interface logic 24, which in turn couples with the input/output system 22, which in turn communicates with bus 26.
  • the testing apparatus 10 i in order to diagno faults in the test system 12, the testing apparatus 10 i
  • a test bus probe 34 via a test bus cable assembly 36
  • a reference bus probe 38 via a reference bus cable assembly 40
  • the coupling is made in such a manner that comparison between simultaneous signals on the respective buses 26 can be made to detect non-coincidences ("failures") and to automatically trace them to their sources based on the information supplied by the bus 26.
  • a manual test probe 42 and a manual reference probe 44 may be provided for manually tracing faults not associated with the bus 26.
  • the test system 12 includes a clock (MPU clock) 28 which is coupled to the test system CPU 18 in a CPU socket 19 and to the reference system 14.
  • the MPU clock 28 is operative to synchronize the reference system 14 with the test system 12 to assure precisely synchronous operation.
  • the multiple terminal probes 34, 38 are typically a forty-pin connector (corresponding to the number of CPU 18 terminals).
  • the probes 34, 38 are generally attached directly to the test unit CPU 18 and reference unit CPU 18 in CPU socket 19.
  • a cable assembly 48 interconnects the testing apparatus 10 and the test environment.
  • the cable assembly 40 includes the forty-line bus cables 36, 40 adapted to convey all signal information coupled to the CPU 18, which in turn are coupled respectively to a test cable buffer circuit 50 and a reference cable buffer circuit 52.
  • the respective cable buffer circuits 50, 52 are operative to buffer the inputs and outputs of the CPU 18 for driving the diagnostic circuitry of the testing apparatus 10.
  • the buffer 50 is adapted to include logic circuitry 54 for testing for internal shorts on the test system bus 26.
  • Th shorts test logic circuitry 54 may specifically include a shorts test register (not shown), which is a thr state register. The shorts test register is responsive to shorts test data via a shorts test data line 58 and to a shorts test clock 56.
  • the shorts test sequence is undertaken as follow
  • the tester 10 is preprogrammed with an indication of which CPU terminals 30 (Fig. 1) are permanently stuck in high or low states so that those terminals are ignored.
  • the CPU 1 is removed from its socket 19 in the test system 12 for th duration of the shorts test.
  • the multiple terminal probe is then connected to the test system CPU socket 19 to forc all possible lines of bus 26 to float.
  • the shorts test register is cleared to zero.
  • all lines o bus 26 are tested one at a time for any which are stuck in high state.
  • Thereafter a single high bit is clocked throu the shorts test register one place at a time for each of t bus lines to change each of the bus lines high one at a time.
  • Each of the other bus lines is also tested to determine if any of the other bus lines has also changed state. In this manner each of the bus lines is checked to determine whether it is stuck high, stuck low or stuck together with another bus line.
  • a central controller 60 control switches or buttons 62, a display device 64 (such a cathode ray tube (CRT) or the like), cycle or personalit logic 66, test and reference buffers 68 and 70, and variou special purpose comparator and latch subsystems 72, 74, 76 and 78.
  • a display device 64 such as a cathode ray tube (CRT) or the like
  • CRT cathode ray tube
  • personalit logic 66 test and reference buffers 68 and 70
  • variou special purpose comparator and latch subsystems 72, 74, 76 and 78 variou special purpose comparator and latch subsystems 72, 74, 76 and 78.
  • the information on the bus 26 at one instant may be output from the CPU 18 to a particular memory 20 or I/O subsystems 22.
  • the- bus contained information may be input data to the CPU 18.
  • the CPU 18 may use the bus 26 to identify to other subsystems state information on its current operation or state. Address as well as data information may be time-multiplexed onto the common bus 26.
  • the bus may also exhibit an "off" state (characterized by a high impedance) during which time signals on the bus 26 have no significance.
  • the testing apparatus 10 must be capable of responding to or decoding the significance of each signal or state occurring on the bus 26.
  • the personality logic 66 is tailor designed to the characteristics of the type of CPU 18 employed in the test system 12.
  • the personality logic is operative to generate specialized strobe signals (via strobe lines 71, 73, 75, 77 and 79) and status signals (via CPU status bus line 110) for correct operation of the testing apparatus 10 with the particular CPU 18.
  • the personality logic 66 is combined with test buffer 68 to direct the timing and the routing of microprocessor signals to the comparator inputs.
  • the strobe signals are for time-demultiplexing the sequential bus line signals which enables the central controller 60 to sort out the information flowing on the bi ⁇ directional bus 26, and eventually to separate failure sources.
  • a data strobe carried via line 75 is derived by the personality logic 66 to identify those instants at which the bus 26 contains valid data.
  • a status strobe, carried by lines 71, 77, is similarly derived for identifying the particular process cycle in progress. The status strobe further defines the type of information transfer taking place on the bus 26.
  • An address strobe, carried via line 73, identifies when a valid address is being presented on the bus 26.
  • Further strobes as for example a control strobe carried via line 79, are employed to sample the states of the various control signals to an from the CPU 18, and also to time demultiplex shared address/data terminal input and output terminals of the C 18.
  • the personality logic 66 and buffers 68 and 70 may include storage registers (not shown) for temporarily storing digital information which can then be transmitted parallel with subsequent information through an enhanced line output bus of the buffers 68 and 70.
  • the buffers 68 and 70 are provided with forty input lines whereas a forty-eight line output is provided.
  • the first comparator and latch subsystem her the address comparator/latch 72, is coupled to receive parallel address signals from both the reference system buffer 70 and the test system buffer 68.
  • the second comparator and latch subsystem herein the data comparator/latch 74 is coupled to receive data informatio from the reference system buffer 70 and test system buffe 68.
  • the third comparator and latch subsystem herein the control/miscellaneous comparator/latch 76, is coupled to receive control signals and other miscellaneous signals f the reference system buffer 70 and test system buffer 68.
  • the fourth comparator subsystem herein the pro comparator 78, is an optional comparator coupled directly the manual probes 42 and 44.
  • the comparator/latches 72, and 76 are adapted to compare reference system bus signal and test system bus signals in parallel operational relation.
  • Each of the comparator/latches 72, 74, 76 provides four output types, namely a "Fail Indication” 80 82 and 84, a state description ("State”) 86, 88 and 90, a stuck register description ("Stuck”) 92, 94, 96 and a failure description ("Failures”) 97, 98 and 100.
  • the central controller 60 provides a reset mechanism via a reset signal line 46.
  • a Fail Indication signal 80, 82, 84 is generated whenever a comparator detects non-coincidence between outputs of the reference buffer 70 and the test buffer 68.
  • the particular Fail Indication signal identifies the type of failure, namely address, data or control.
  • the controller 60 immediately removes enable signals via signal line 102 from the comparators 72, 74, 76, 78 and the personality logic 66. This freezes the state of the latches in the comparator/latch subsystems 72, 74, 76 prior to the occurrence of the next timing strobe and thereby captures the State, Stuck and Failures description in the current location.
  • the State buses 86, 88 and 90 are merged into a single State bus 104, the Stuck buses 92, 94 and 96 are merged into a single Stuck bus 106 and the Failures buses 97, 98 and 100 are merged into a single Failures bus
  • the Failures bus 108 identifies the address of the non- compare signals.
  • the Stuck bus 106 identifies the signals which have never experienced logic state transitions.
  • the State bus 104 identifies the address and status of the system program at failure.
  • the removal of the enable signal via signal line 102 to the personality logic 66 also causes a latch (not shown) in the personality logic 66 to provide a CPU status signal to the controller 60.
  • the system information provided by the comparator/latches 72, 74 and 76 and the CPU status information disclose to the central controller 60 the identity and the location of faults within the test system 12.
  • a sequential diagnostic algorithm shown in Fig. 3 is the technique employed by the central controller 60 to analyze the information and to present the analysis in useful form to a display/output device 112.
  • the separate Fail Indication signals via signal lines 80, 82 and 84 serve as flags permitting the controller 60 to separate address, data and control failures according to the sequential diagnostic algorithm of Fig. 3.
  • the controller 60 checks CPU status (signal line 110). If the CPU 18 is operating in a direct memory access (DMA) cycle (step 200) the controller 60 immediatel identifies and signals a Bus Device Failure (step 202), causing display of current address, data and status information. This information will indicate failure at a specific bus-connected subsystem. Using this information, the user with the help of a program memory map of the test system 10 locates the defective bus-coupled subsystem.
  • DMA direct memory access
  • Th memory map may be automatically referenced by the controll 60 through a separate algorithm that compares the address, data and status information with the parameters of a memor map description. A description of an automatic memory map search is given hereafter. If the failure is not located a bus-coupled subsystem, then the bus-coupled subsystem propagating the failure is used as a starting point to locate the failure through a conventional spatial diagnost algorithm using the manual probes 42, 44. if a failure does not occur on a DMA cycle, the controller 60 then checks for address failure (step 204), that is, non-coincidence between the address information o the test system 12 and the reference system 14 indicated b signal line 80. A positive address failure indication points to a failure in the CPU 18 (step 206) thereupon the controller 60 causes display of "CPU FAIL" or the like, or the cycle count at fail (operational termination) .
  • step 204 the controller 60 checks for a control signal failure (step 208) as indicated by signal line 84. If a control signal failure is positively indicated, the controller 60 checks the CPU status line 110 to determine if the conditi occurred during control input (step 210), thereby indicati input control signal failure. A positive indication point to a bus-coupled subsystem failure (step 202) locatable wi the help of the program memory map previously described. negative indication points to a CPU failure (step 206).
  • step 208 the controller 60 checks for data failure (step 212) as indicated by signal line 82 (Fig. 2). If data failure has occurred, the controller 60 checks CPU status through line 110 to determine if the condition occurred during a write cycle (step 214). A positive indication points to CPU failure (step 206). A negative indication points to a bus-coupled subsystem failure (step 202).
  • a controller 60 embodying the sequential diagnostic algorithm comprises a means for indicating the nature of the non-coincidence between the reference system 14 and the test system 12 and a means for designating the bus-coupled subsystem originating the non- coincidence.
  • a test apparatus 10 incorporating the sequential diagnostic algorithm greatly facilitates the isolation of programmed microprocessor-based board/system faults.
  • FIG. 3 may be embodied as either a hard-wired circuit of digital logic gates or in software form.
  • D is TRUE if the system is on a read cycle at failure
  • E is TRUE if there is an input control signal at failure
  • Figure 4 represents a schematic diagram of a circuit according to Equations 1 and 2.
  • the test system memory map may be embodied manually by reference to printed documentation or automatically through an auxiliary memory map input device 63 (Fig. 2) coupled to the central controller 60.
  • the identification of a faulty bus-connected subsystem may the become the starting point of a technique or algorithm for automatically guiding the user to the faulty device or nod (terminal).
  • One such guide probe algorithm is the AutotrackTM algorithm embodied in the Model 3040A Logic
  • the implementation of the search for the program or data location of failure comprises first specifying the program address or address range of each of the bus-couple subsystems. Thereafter, utilizing the tester-generated address at failure, sequentially searching the address entries in the memory map until a matching address or cor ⁇ related address range is found. Then comparing the data b bits for which failure occurred against known information about which data bus bits are associated with that particular entry in the address map. This last step is necessary because each data bus bit may designate a different subsystem coupled to the data bus.
  • the tester has isolated the bus- coupled subsystem causing the error.
  • the organization of the data base, in this case a memory map, stored in the logic search apparatus determines the search implementation.
  • One example of one possible organization for search implementation is given in the Table below. In the Table, the first three columns are in hexadecimal (base 16) notation and the last column is in character notation such as ASCII code.
  • Column 3 is a data bit mask for identifying data bus bit position of a device coupled to the data portion of bus 26 (Fig. 1). The example is shown for a 16-bit address and 8-bit data bus configuration.
  • Entries 2 through 9 exemplify the 1024 x 1 bit RAM chips of the above example. Entry 1 is for a 2048 x 8 Read Only Memory (ROM) chip.
  • auxiliary functions include a mode selector 250, and address/mask circuit 252 and a cycle counter 254.
  • the comparator/latch subsystems 72, 74; 76 comprise a comparator section, a failure indication section and a three-state latch section.
  • the comparator section comprises forty EXCLUSIVE OR gates 260 (with inverted outputs) connected in parallel to the reference system buffer 70 and the test system buffer 68 (Fig. 2).
  • the three-state latch section includes a first array 270 of ten four-input D-type registers, such as type 8551 (manufactured by National Semiconductor Corporation of Santa Clara, California), a second array 272 of ten four- input D-type registers, also type 8551, and a third array 274 of ten four-bit latches or quad latches such as type 8544 also manufactured by National Semiconductor Corp.
  • the inputs of the first array 270 are derived from the outputs of gates 260.
  • the first array 270 is operative to store failing pin information, if any, and to make that information available to the controller 60.
  • the inputs of the second array 272 are derived from the output test buffer 68.
  • the second array is operative to store all binary state information and to make it available to the controller 60.
  • the third array 274 derives input from an array of forty dual input EXCLUSIVE OR gates 276 whose inputs consist of the state information from test system buffer 68 and from forty parallel delay circuits 278 (D-type flip-flops).
  • the third array is thus operative to store the compared current and previous state information to determine if there has been activity on each information line indicating stuck pins and to make the information available to the controller 60.
  • the failure indication section comprises the outputs of gates 260 coupled in groups of five to eight input NAND gates 262, each of which is coupled to a faul latch 264.
  • the eight fault latches 264 comprise D-type flops.
  • the inverted outputs " Q are coupled to one nine-i NAND gate 266.
  • a non-coincidence at any of the comparators 260 is propagated to the fault latches 26 which signals a Failure Indication at the output of gate 266, to the mode selector 250.
  • the Failure Indication disables the cycle counters and freezes all latches.
  • test modes of operation of the test apparatus 10 may include “st on-count”, “stop-on-Nth-fault” , “stop-on-probe” and “sto external-signal” .
  • the mode selector 2 monitors the COUNT signal line from cycle counter 254.
  • the cycle counter 254 registers a predetermined count, wh has been entered by the operator via keyboard control switches 62 (Fig. 2), the mode selector 250, through the signal line, it causes all registers and latches 270, 272 274 to be loaded with the current test information.
  • the "stop-on-probe" mode is normally employed after a bus failure has been identified in order to isola a non-bus-coupled failed subsystem.
  • the manual probes 42 44 (Fig. 1) are coupled to comparator 78 (Fig. 1) whose output as PROBE (Fig. 5) is provided to at least one of t
  • NAND gates 266 (Fig. 5) and to the mode selector 250.
  • Th manual probes 42, 44 are employed according to convention spatial diagnostic techniques to isolate the subsystem or device generating bad (non-coincident) outputs from good
  • the test apparatus 10 is operative to stop and latch data on an external signal. It is used when the test apparatus 10 i interfaced with other testers, as well as for diagnostic testing of the test apparatus 10 itself.
  • the "stop-on-Nth-failure" mode enables the operator to terminate system operation on a sensed non- coincidence other than the first sensed non-coincidence. This feature is particularly useful in testing circuitry or components which cannot be initialized such as a memory refresh controller having an internal counter (such as Intel 3222 of the Intel Corporation, Santa Clara, California) or an analog-to-digital (A/D) converter.
  • Uninitializable circuits may cause meaningless non-coincidences to be detected as failures, such as non-coincidences resulting from start-up.
  • this test mode may provide useful information by indicating how a real error would propagate through a system if the test system is allowed to continue operating after a failure occurs.
  • a counter clock selector 255 is provided at the input of the cycle counter 254.
  • the cycle counter 254 in operation is preloaded with N, the number of failures to be ignored.
  • the counter clock selector 255 monitors the FAIL signal output of NAND gate 266 to cause the cycle counter 254 to be clocked once each failure. Consequently the mode selector 250 inhibits the transition of the ENA signal in response to the FAIL signal until the COUNT signal line from the cycle counter 254 indicates that the predetermined number of failures has been counted.
  • One further feature of the invention is a masking function provided by the address/mask circuit 252.
  • the address/mask circuit 252 provides two types of masks, a hard ⁇ wired mask (EXT MASK) and a software-derived mask (ADDRESS).
  • the masking function is particularly useful when the test system 12 cannot be immediately initialized.
  • the hard-wired mask (EXT MASK) couples to the reset input of the fault latch 264.
  • the software-derived mask (ADDRESS) is initially loaded into an array of J-type flip-flops on the master reset (MR) signal and then is coupled to the fault latch
  • EXT MASK is operative to mask failures when TRUE.
  • ADDRESS mask is intended to mask all failures until a specified address occurs.
  • the inventive test apparatus provides access to the principal bi-directional .bus of a programmed microprocessor-based system, which considerab simplifies system diagnosis as compared with prior art e connected testers.
  • the invention is optimized for sequential bus-coupled operating systems such as program systems, as contrasted to random logic systems.
  • the invention provides controlled synchronous multiple clocking functions, which simplify diagnosis of programmed systems. Moreover, the invention allows for system diagnosis through program location and subsystem status analysis. Address, data and status, information i segregated, and a memory map is used to trace errors. . The invention provides a display of the channe fault rather than the failed pin. Inherent in the inven is the capability of deciphering the information on a ti multiplexed bi-directional bus.
  • a further feature is the capability of automatically testing for shorts on the bi-directional bu Without this feature, the "stop-on-first-fail" algorithm be defeated.
  • the sequential diagnostic algorithm herein disclosed may also be adapted to be embodied in any testi machine which is capable of sequentially monitoring all machine cycles and of stopping on the first failure of signal coincidence with a reference.
  • the algorithm may be implemented with a logic state analysis- type tester, a truth-table-type tester, or comparison-typ tester.
  • the algorithm cannot be implemented on signature-type testers since such testers cannot recogniz the first sequential failure.

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Abstract

Un appareil d'essai automatique (10) couple a un bus de commande et de donnee internes bidirectionnelles (26) d'un systeme a base de microprocesseurs programme (14) controle le rendement du systeme (14) en temp s reel. Des reponses de signaux du bus (26) dans un bon systeme connu (12) sont comparees en temps reel aux reponses de signaux sur le bus (26) du systeme non connu a l'essai (14) de maniere a identifier les defaillances. Les defaillances sont isolees par un algorithme sequentiel qui arrete le fonctionnement au moment designe ou se produit une defaillance, generalement la premiere defaillance, puis il etablit quel est le sous-systeme ou composant defectueux du systeme a l'essai (14), envoyant le signal d'erreur indiquee au bus bidirectionnel (26).
EP19790901509 1979-07-27 1981-02-24 Appareil d'essai pour systemes a base de microprocesseurs. Withdrawn EP0032895A4 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1979/000550 WO1981000475A1 (fr) 1979-07-27 1979-07-27 Appareil d'essai pour systemes a base microprocesseurs

Publications (2)

Publication Number Publication Date
EP0032895A1 true EP0032895A1 (fr) 1981-08-05
EP0032895A4 EP0032895A4 (fr) 1982-03-22

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EP19790901509 Withdrawn EP0032895A4 (fr) 1979-07-27 1981-02-24 Appareil d'essai pour systemes a base de microprocesseurs.

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EP (1) EP0032895A4 (fr)
JP (1) JPS56500945A (fr)
BR (1) BR7909027A (fr)
WO (1) WO1981000475A1 (fr)

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EP0032895A4 (fr) 1982-03-22
BR7909027A (pt) 1981-05-26
JPS56500945A (fr) 1981-07-09
WO1981000475A1 (fr) 1981-02-19

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