Classifications

• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
  • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
  • H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
  • H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
• • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
  • F28—HEAT EXCHANGE IN GENERAL
  • F28F—DETAILS OF HEAT-EXCHANGE AND HEAT-TRANSFER APPARATUS, OF GENERAL APPLICATION
  • F28F9/00—Casings; Header boxes; Auxiliary supports for elements; Auxiliary members within casings
  • F28F9/02—Header boxes; End plates
  • F28F9/04—Arrangements for sealing elements into header boxes or end plates
  • F28F9/06—Arrangements for sealing elements into header boxes or end plates by dismountable joints
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
  • H02P3/00—Arrangements for stopping or slowing electric motors, generators, or dynamo-electric converters
  • H02P3/06—Arrangements for stopping or slowing electric motors, generators, or dynamo-electric converters for stopping or slowing an individual dynamo-electric motor or dynamo-electric converter
  • H02P3/08—Arrangements for stopping or slowing electric motors, generators, or dynamo-electric converters for stopping or slowing an individual dynamo-electric motor or dynamo-electric converter for stopping or slowing a dc motor
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
  • H02P7/00—Arrangements for regulating or controlling the speed or torque of electric DC motors
  • H02P7/06—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current
  • H02P7/18—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power
  • H02P7/24—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices
  • H02P7/28—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices using semiconductor devices
  • H02P7/281—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices using semiconductor devices the DC motor being operated in four quadrants
  • H02P7/2815—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices using semiconductor devices the DC motor being operated in four quadrants whereby the speed is regulated by measuring the motor speed and comparing it with a given physical value
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
  • Y02T10/00—Road transport of goods or passengers
  • Y02T10/60—Other road transportation technologies with climate change mitigation effect
  • Y02T10/72—Electric energy management in electromobility

Definitions

• This invention relates to a control system for a direct current motor having a separately excited field, and more particularly to a motor as used in a batterypowered vehicle such as a lift truck.
• Various systems are in use for the control of direction and speed of motor-driven vehicles.
• such vehicles are provided with two operator controls, a direction selector member and a speed control.
• the direction selector functions to cause the field to be connected for flow of field current therethrough in the appropriate direction to cause the motor to rotate in the forward or reverse direction selected by the operator.
• the speed control typically a depressible foot pedal, is used to control the amount of power supplied to the motor from the battery.
• SCR silicon controlled rectifier
• the usual method of controlling the speed of the motor is to set and maintain the level of armature current through the main SCR in accordance with the position of the speed control.
• the more the pedal is depressed the greater the ratio of on-time to off-time of the main SCR, the greater the average armature current and the higher the speed of the motor.
• Such control has a disadvantage in that the vehicle speed is dependent upon the position of the speed control and on the load on the motor. With a particular level of armature current being maintained, the vehicle speed will be significantly lower if the vehicle is heavily laden and/or is going uphill than it will be if the vehicle is carrying no load and/or is going downhill. As a consequence, if the operator wishes to maintain a substantially constant speed, it is necessary for him to keep depressing or releasing the foot pedal as the load on the vehicle changes.
• the controls in use generally employ analog systems to control motor operation in accordance with changes in the primary and feedback information utilized in the control. That is, voltage signals are developed which have a magnitude dependent on the level of the condition being monitored. The system will then produce the end result desired in accordance with the magnitude of the voltage level of the various signals that are used.
• Analog systems however, have disadvantages in that frequent adjustment of circuit values is necessary to maintain voltage levels at proper values. Nonlinearity of response is often a problem, as well as undesirable circuit interaction. Also, it is difficult at times to design and maintain reliable analog circuits which compare two continually changing conditions and determine the magnitude of difference therebetween.
• the present control systems also function to control the armature current by the SCR chopper circuit throughout most of the speed range of the motor.
• bypass mode operation has the attendant disadvantage in that the operator has no further control of the motor until such time as he causes the system to go out of bypass mode by releasing the foot pedal.
• Present control systems also provide for dynamic braking, wherein the motor is driven as a generator by the momentum of the vehicle, the generated current being used to develop braking torque.
• the system is put into a dynamic braking mode by disconnecting the field and reconnecting it for flow of current therethrough in the opposite direction.
• Heavy duty and relatively expensive contactors are required to handle the large field currents present when the field connection is reversed.
• Contactor burn-out, from the arc created as the contactors open, is a common problem. Oftentimes the arc will weld the contactors together.
• the motor When in dynamic braking at high speeds the motor will develop a counter emf greater than that of the battery. It is desirable to use the generated current at such time to recharge the battery so that the efficiency of the system is increased.
• problems do exist in the design of a reliable and efficient circuit which will connect the motor to the battery for regenerative charging of the battery and which will disconnect the motor from the battery when sufficient counter emf for charging is not present and then connect the motor
• the degree of acceleration of the motor as it comes up to speed is a function of the armature power current from the battery. The higher the current, the greater the acceleration.
• the degree of deceleration is a function of the level of armature brake current generated by the motor. The higher the current, the greater the deceleration. It is often desirable to provide different current limits for power mode and braking mode so that the maximum acceleration can be established independently of the maximum deceleration. Likewise it is desirable to provide different current limits during regenerative and resistive braking so that the braking torque in the two modes may be equalized.
• the SCR chopper circuits include pulse transformers in series with the main SCR and armature, such pulse transformers being used to charge the commutating capacitor as load current flows therethrough.
• the main SCR is in conduction the voltage drop across such pulse transformers thus limits the amount of power that can be applied to the motor from the battery.
• no load current-carrying component is in series with the load and the main SCR so that maximum power of the battery can be applied to the load.
• the present SCR chopper circuits typically operate to control the ratio of on-time to off-time of the main SCR by frequency modulation or by pulse width modulation.
• the SCR is repeatedly gated into conduction at a desired and variable rate, with the SCR being cornmutated at a fixed length of time after it has been gated on.
• the ratio of on-time to off-time will increase as the frequency of application of gate pulses is increased and vice versa.
• the gate pulses are applied to the main SCR at a fixed rate, and the length of time until commutation occurs is varied.
• misfire detection circuits use a timer which is turned on each time the main SCR is gated on. When the timer times out, the conduction state of the main SCR is examined. If it is still in conduction, the main power circuit is interrupted. in systems wherein the main SCR is on for variable lengths of time each time it is gated on the present misfire detection circuits have a significant disadvantage.
• the time period of the timer must be longer than the longest time that the main SCR is normally on. Otherwise, if the timer timed out while the main SCR is properly on, the system would be shut down.
• the current level is high, i.e., with long lengths of normal conduction of the main SCR, a misfire is detected very shortly after it occurs.
• the degree of difference in current level if there is a misfire is not too great.
• the system is operating at low current levels, i.e., with short periods of on-time of the main SCR, and the SCR misfires, the current level will increase greatly before the timer times out and corrective action is taken. Accordingly there is a need for a misfire circuit which will detect a misfire as soon as it occurs, regardless of how long the SCR may have been on prior to its failure to commutate.
• the present invention is directed to solving one or more of the problems and/or fulfilling one or more of the needs referred to above.
• the control system of the present invention is basically a speed control system wherein the speed demanded by the operator (as by way of a conventional foot pedal) and the actual speed of the motor are continuously compared, and the level and direction of armature current and the level of field current are controlled to bring the actual speed to the demanded speed and maintain it thereat.
• the control system thus enables the operator to demand a desired speed and have the motor operate at that speed independently of the load on the motor.
• the demanded and actual speeds are compared to see whether the armature is to be connected to the battery for power mode operation, i.e., power current flows from the battery to the armature, or for braking mode operation, i.e., brake current flows through the armature in the reverse direction to cause a deceleration of the motor. If the demanded speed is a predetermined degree less than the actual speed (regardless of what the actual speed is) the armature is connected for braking mode operation. Otherwise, the armature is connected for power mode operation.
• power mode operation i.e., power current flows from the battery to the armature
• braking mode operation i.e., brake current flows through the armature in the reverse direction to cause a deceleration of the motor.
• the armature current is primarily controlled as a function of the magnitude of the demanded speed when the speed of the motor is below a predetermined base speed, the latter being substantially below top speed of the motor.
• a predetermined base speed the latter being substantially below top speed of the motor.
• the ratio of on-time to off-time of the main SCR connecting the armature and battery is increased and vice versa.
• the main SCR conducts continuously.
• the field current is primarily controlled as an inverse function of the demanded and actual speeds throughout the entire speed range of the motor.
• the present control system determines how much greater. If the demanded speed is sufficiently greater than the actual speed, acceleration signals are generated and used to boost the armature current and weaken the field so that the motor will be rapidly brought up to speed. As the actual speed increases, the boosting effect reduces,
• the present control also provides for separate and non-interacting control over the rate of acceleration and peak acceleration, the rate of acceleration being controlled by the rate at which armature current can increase in response to a demand for acceleration, and the maximum, or peak, acceleration being controlled by setting the maximum allowable power current limit.
• the present control further provides for limiting the speed of the motor to a predetermined top speed less than that which the operator can otherwise demand.
• the top speed limit circuits do not come into operation until the actual speed of the motor has reached such limit, and thus do not affect control of the motor or the degree of acceleration when the motor speed is below such limit. As a consequence, the operator can obtain a maximum rate of acceleration by demanding a speed greater than the top speed limit.
• the top speed limit circuits operate to take control of the motor and to maintain the speed thereof at such limit until such time as the operator demands a slower speed.
• the present control also provides for reducing the maximum allowable power current limit as an inverse function of the actual and demanded speeds so that less power current can flow through the armature at higher speeds, thereby reducing sparking at the armature brushes.
• the power connection of the armature to the battery is interrupted and the armature is connected for reverse flow of brake current therethrough, such current being generated as the motor is driven as a generator. If the motor speed is high enough, the armature is connected to the battery and the regenerative brake current is used to charge the battery. If the motor speed is not high enough to charge the battery, the armature is shorted for resistive braking.
• the field is controlled by monitoring the level of armature brake current and by regulating the field current so that the brake current is maintained at a maximum allowable brake current limit level.
• a higher brake current limit level is provided during resistive braking than in regenerative braking to equalize the braking torque.
• the present control system determines how much lower, and uses such determination in controlling the degree of deceleration. In more particular, the lower the demanded speed is, relative to the actual speed, the greater will be the allowable brake current. As the actual speed reduces towards the demanded speed, the allowable brake current is reduced so that the system will come smoothly out of deceleration.
• a further aspect of the invention is that a "dead band" is set, relative to the particular speed demanded by tht operator, wherein the actual speed of the motor is allowed to vary in accordance with the load on the motor. If the load increases somewhat the motor is allowed to slow enough to provide the necessary torque. Conversely, if the load increases somewhat, the speed is allowed to increase. However, if the load increases sufficiently so that the actual speed would fall below the lower limit of the dead-band range, an acceleration signal will be generated to cause the speed to increase and return the speed to within the range. Conversely, if the motor should speed up, because of a lower load thereon, to a point where it goes beyond the other end of the range, the system will go into a braking mode and return the speed to the range set by the foot pedal.
• a yet further point of the invention is that the field current is maintained at a constant level when the actual speed is within the dead-band range so that the system will not be uncomfortably sensitive.
• a still further aspect of the invention is the manner in which "plugging" is carried out, plugging being an operation wherein the motor is rotating in one direction, e.g., forward, with the field being connected to the battery for flow of current through the field in the direction to cause forward rotation of the motor, and the operator shifts to reverse.
• such shift puts the system into a braking mode, as if the operator had commanded a slower forward speed.
• the speed and field current are monitored as the motor is braked towards a stop. When, and only after, the speed and field current have reduced to predetermined minimum values, the field is disconnected and reconnected for reverse power operation.
• condition signals are generated for each of these variables, the codnition signals having a frequency which varies in accordance with the magnitude of the condition.
• the frequencies of the condition signals are then compared with each other or with fixed frequency reference signals, with digital control signals, i.e., high or low, being generated to indicate whether one compared signal is higher or lower than the other.
• the digital control signals are then used in logic circuits to produce digital command signals to cause the armature and field currents to produce the desired ⁇ esults.
• Another aspect of the invention is the manner in which the demanded and actual speeds are compared.
• the demanded and actual speeds are continuously compared to determine whether the actual speed should be increased (demanded speed is greater than actual speed) or decreased (demanded speed is lessthan actual speed). Moreover, the magnitude of difference must be determined to see how fast the motor should accelerate or decelerate to a demanded speed.
• such comparison is made by counting the number of cycles of the demandedspeed frequency signal per cycle of the actual speed frequency signal. Regardless of what the actual speed is, the digital count obtained will be the same if the demanded and actual speeds are equal. If the demanded speed is increased relative to the actual speed (or if the actual speed decreases relative to the demanded speed) the count will go up from that obtained when the speeds are equal. The greater the differences between demanded and actual speeds, the higher the count. Predetermined high count numbers are used to control the degree of acceleration. Conversely if the demanded speed is decreased relative to the actual speed (or if the actual speed increases relative to the demandedspeed) the count will go down from that obtained when the speeds are equal. Again, the greater such difference, the lower the count.
• the field current is controlled as an inverse function of the demanded and actual speeds, i.e., as an inverse function of the products of these two speeds.
• control is achieved by counting the number of cycles of a signal having a frequency proportional to the actual speed per cycle of a signal having a frequency inversely proportional to the demanded speed. If the demanded speed goes up and the actual speed remains unchanged, the count will increase. If the demanded speed is the same and the actual speed increases, the count will increase. If both demanded and actual speeds are increased, the count will increase as a result of both speed increases.
• the digital count is inverted and used to control the field so that the field current decreases as the count increases, and vice versa.
• an armature current signal is generated having a predetermined frequency when no current flows through the armature.
• the frequency of the armature current signal increases from the predetermined zero-current frequency, and increases proportionally to the magnitude of the power current.
• current flow is in the opposite direction, e.g., brake current
• the frequency of the armature current is decreased from the zero-current frequency, again with the degree of decrease of frequency being proportional to the magnitude of brake current.
• non-interacting current limit references may be set.
• a power current limit reference signal may be provided having a frequency above the zero-current frequency of the armature current signal while a brake current limit reference is provided having a frequency below the zero-current frequency.
• the frequency of the armature current signal is then compared to both current limit reference signals. If the frequency of the armature control signal is above the high frequency power current limit reference signal an excessive power current signal will be generated.
• the present invention also provides an improved SCR chopper circuit for control of armature current wherein the main SCR and load, e.g., the armature, are connected directly across the battery so that no other load components, such as a pulse transformer, are required to handle load currents , thus maximizing power transfer from the battery to the load.
• An inductor in parallel with the load charges a commutating capacitor to about twice battery voltage, thereby minimizing the size of capacitor and inductors needed.
• the commutating capacitor discharges in parallel with the main SCR so that full advantage of the charge on the capacitor is had during commutation.
• the SCR system also provides separate SCR's for connection of the armature to the battery for regenerative braking or for shorting of the armature for resistive braking.
• the SCR system further utilizes a single capacitor for commutating the main SCR or the resistive braking SCR, depending on which one is in conduction.
• Another aspect of the invention is the use of a monostable multivibrator in the pulsing circuit for the main SCR in the armature circuit, such multivibrator producing a single pulse in response to each trigger pulse applied thereto.
• the beginning of each monostable is used to gate on the main SCR and the end of each pulse is used to initiate commutation of the main SCR.
• Such use of a monostable multivibrator results in a very flexible control since the rate of pulsing can be varied by varying the rate at which trigger pulses are applied and the duration of the monostable pulses can be varied as desired.
• the pulse rate and pulse width can be independently varied.
• the monostable multivibrator also enables retrigger operation so that a continuous pulse is produced.
• Another advantage of the present invention is the manner in which a "misfire", i.e., a failure of a main SCR to commutate, is detected so that the system may be shut down.
• the conduction state of the SCR is looked at during the time interval beginning at a predetermined time after commutation is initiated (i.e., beginning when the SCR should be commutated) and ending prior to the time that the SCR would normally be gated back on. If the SCR is conducting during this time interval, a signal is generated to indicate a misfire.
• the misfire detection circuit operates independently of the length of time that the SCR is supposed to be on since the beginning of the time interval for inspection is dependent upon the time that commutation is initiated.
• a similar misfire circuit is provided for the main SCR for the field, but with a delay so that the conduction state of the SCR is not looked at until the second time interval following a misfire. Such delay provides a second chance for the SCR to commutate. If it still fails to do so, a misfire signal will be generated.
• FIG. 1 is a block diagram of the various components of the motor control system of the present invention showing the flow of control signals between the components;
• FIG. 2 is a schematic diagram of the power portion of the motor control of FIG. 1;
• FIG. 3 is a schematic diagram of the operator demand and armature and field current sensor amplifiers portion of the motor control of FIG. 1;
• FIGS. 4, 5 and 6 are schematic diagrams of the reference signal and comparator circuits portion of the motor control
• FIGS. 7, 8 and 9 are schematic diagrams of the control logic portion of the motor control
• FIG. 10 is a schematic diagram of the armature pulsing circuits of the motor control
• FIG. 11 is a schematic diagram of the field pulsing circuits of the motor control
• FIG. 12 is a schematic diagram of the gate pulse amplifiers portion of the motor control
• FIG. 13 is a graph illustrating the relationship of the direction and magnitude of armature current flow to the armature current voltage signal V IA ;
• FIG. 14 is a graph illustrating the relationship of the armature current frequency signal F IA to the armature current voltage signal V IA and to the armature current monitor signals;
• FIG. 15 is a graph illustrating the relationship of the fixed speed signals relative to actual motor speed
• FIG. 16 is a graph illustrating the relationship of the field current and the field current frequency signal F IA to the field current monitor signals;
• FIG. 17 is a chart illustrating the time relation of the signals involved in the detection of a misfire of the main armature SCR;
• FIG. 18 is a schematic diagram of a modification of the field pulsing circuits of the motor control.
• FIG. 1 shows the overall system for a silicon-controlled rectifier (SCR) control for a direct current motor having an armature 20 and a separately excited field 21 powered from a direct current source such as battery 22.
• SCR silicon-controlled rectifier
• the illustrated control has particular suitability in the drive system of a vehicle such as a lift truck (not shown).
• the control is provided with three operatoractuated devices: a main power switch 23, a control lever 24 for commanding a forward or reverse direction, and an accelerator pedal 25.
• FIG. 2 illustrates the power portion of the control of FIG. 1.
• Closure of main switch 23 will develop a supply of regulated voltages V S1 , V S2 and V S3 across zener diodes 27, 28 and 29, respectively.
• regulated voltages may be 20, 13.6 and 6.8 volts, respectively.
• Supply voltage V S1 is applied to the first transistor 30 of the four-stage transistor amplifier 31, transistors 32, 33 and 34 being powered from battery 22 through circuit breaker contact 35 and circuit breaker trip coil 36. Circuit breaker contacts 35 and 37 are manually closable and will remain closed unless trip coil 36 is driven by amplifier 31. If the voltage V S1 is not present (such as when the main switch 23 is opened) or if a V CBT signal is applied to transistor 30, trip coil 36 will be energized and contacts 35 and 37 will be opened to remove voltage from the amplifier 31 and the armature and field circuits of the motor.
• the field 21 of the motor is powered as follows. Assuming that the motor is to be driven in a forward direction, a forward signal FWD is received at the bottom center of FIG.
• FIG. 8 (a number in a circle adjacent a control signal on the drawings indicates the particular figure of the drawings whereinthe signal is generated or to which the signal is sent), is amplified by amplifier 38 and drives coil 39 of the forward relay to close the forward relay contacts 40 and 41 and thus connect one terminal of the field winding to ground and the other terminal to the cathode of the main field SCR, SCR MF , (The connection of the field winding terminals would be reversed if a reverse signal REV had been applied through amplifier 42 to the coil 43 of the reverse relay and reverse relay contacts 44 and 45 had been closed).
• Microswitches 46 and 47 are mechanically actuated to closed position upon closure of the forward or reverse contacts, respectively, and when closed will provide voltage signals DR F or DR R , to confirm that the forward or reverse contacts, respectively, have in fact closed. As indicated on the drawings, these signals are sent to the control logic of FIGS, 7 and 9,
• a subsequent gating on of the commutating SCR, SCR CF will then result in connecting the commutating capacitor C CF in parallel with SCR MF , back-biasing SCR MF and turning it off.
• C CF will charge through SCR CF so that its right plate will be positive with respect to its left plate. After charging, the current flow through C CF and SCR CF will cease and SCR CF will turn off.
• Regating of SCR MF and SCR LF will restart the sequence.
• the power to the field is controlled by varying the ratio of the on-time to the off-time of SCR MF .
• a current shunt 49 in the field circuit monitors the current flowing through the field and produces voltage signal +V F and -V F having a potential difference therebetween proportional to the amount of field current.
• a free-wheeling diode D FWF is connected across the field winding to allow current to flow during the periods when SCR MF is not conducting.
• a zener diode 50 and resistor 51 are also connected across the field, and a control signal V FM is obtained from the junction of zener 50 and resistor 51.
• Signal V FM will be high or low, respectively, depending on whether SCR MF is conducting or not, thereby providing a signal as to the state of conduction of SCR MF , which signal is used in the subsequently described misfire circuit illustrated on FIG. 7.
• the armature 20 of the motor is powered as follows. With circuit breaker contact 35 closed, battery voltage will be applied through fuse 55 to the anode of the main SCR for the armature, SCR MA . When this SCR is gated on, current will flow therethrough and through armature 20, inductance L FA and back to the battery. Inductance L FA is used to provide more inductance in the armature circuit for smoother operation. Charging SCR, SCR LA , is gated on to conduct before SCR MA is gated on, so that current will flow through commutating capacitor C CA and choke L CA to charge the capacitor to approximately twice battery voltage with its left plate negative with respect to its right plate. When such charging current ceases, SCR LA will turn itself off.
• SCR MA will continue to conduct, and power current from the battery will flow through the armature until such time as the commutating SCR, SCR CA , is gated on. When this occurs, capacitor C CA will be connected in parallel to SCR MA to back-bias and turn SCR MA off.
• the power supplied from the battery to the armature will be a function of the on-time to off-time of SCR MA .
• a free-wheeling diode D FWA is connected across the armature,
• a current shunt 56 is connected in the armature circuit to monitor armature current and produce voltage signals +V A and -V A at the shunt terminals. The voltage difference between these terminals is proportional to the level of armature current. A given level of armature power current will produce the same voltage difference between the shunt terminals as will the same level of armature brake current.
• a misfire signal (indicative of a failure of the main SCR MA to commutate) is obtained from junction 57 of SCR CA , SCR LA and C CA .
• SCR CA is gated on capacitor C CA will cause SCR MA to be turned off and C CA will charge through SCR CA so that the charge thereacross will be about twice the battery voltage, with its left plate positive with respect to its right.
• the potential at junction 57 will be either about twice battery voltage above ground (if free-wheeling current is flowing through the armature and diode D FWA ) or about three times battery voltage above ground (if no free- wheeling current is flowing).
• SCR MA is not successfully commutated and it continues to conduct, then the capacitor C CA cannot charge so that its left plate is positive with respect to its right and junction 57 will be at approximately battery voltage above ground.
• Zener diode 58, diode 59 and resistor 60 are connected in series from junction 57 to ground, zener diode 58 being used to drop battery voltage thereacross.
• the potential at junction 61 between diode 59 and resistor 60 will be approximately at ground if SCR MA has not commutated, or will be one or two times battery voltage if it has.
• Zener diode 62 and resistor 63 are connected from junction 61 to ground, with voltage signal V AM being taken across zener 62. Signal V AM accordingly will be high (zener 62 potential) if it has been commutated, and low if it has not.
• the momentum of the vehicle will cause the armature to be driven so that the motor acts as a generator. If the motor speed and field strength are sufficiently high, the emf developed across the armature will be greater than that of the battery. In such event, the regenerative braking SCR, SCR RB , connected across and oppositely poled to the main SCR MA is gated on to allow braking current to flow back and charge the battery. The SCR RB will commutate itself as the armature slows arid the emf across the armature becomes insufficient to continue charging the battery. After SC RRB is commutated, the resistive braking SCR, SCR B , is gated on to effectively short-circuit the armature for resistive braking of the motor.
• SCR CA is first gated on to allow C CA to charge with its left plate positive relative to its right. Then, SCR LA is gated on connect C CA across SCR B , back-biasing and commutating it. After such commutation, SCR MA is gated on to resume power operation of the motor.
• the particular disclosed arrangement of SCR MA , SCR LA , SCR CA , C CA , L CA and the armature 20 has several significant advantages.
• the armature and SCR MA are connected directly across the battery so that no other components, such as a pulse transformer are required to handle load current. As a consequence, power transfer from the battery to the armature is maximized.
• the inductor L CA is used to charge C CA to about twice battery voltage which minimizes the size of the capacitor, and no load current flows through the inductor, which minimizes its size.
• the commutating capacitor C CA discharges in parallel with SCR MA , enabling full advantage to be had of the charge thereacross during commutation.
• the field arrangement is the same, and has the same advantages.
• the disclosed arrangement of SCR B is also advantageous in that it permits the single commutating capacitor C CA to be used for commutation of either SCR MA or SCR B .
• C CA is first charged in one direction through SCR LA and is then connected across SCR MA by use of SCR CA .
• C CA is charged in the opposite direction through SCR CA , SCR LA then being used to connect the charged capacitor across SCR B .
• the actual speed of the motor is monitored by a speed pickup 65.
• a toothed gear 66 is driven by the armature, with its teeth rotating past a magnetic Hall effect sensing device 67, so that a low voltage (approximately 1 volt) ripple signal N MP is produced which rides on approximately a 5-volt d.c. signal.
• N MP low voltage ripple signal
• the operator-actuated direction-selection lever 24 is mechanically linked to switches 70 and 71.
• switch 70 will close and produce a forward-operator-demand signal F OD equal to supply voltage V S2 .
• F OD forward-operator-demand signal
• This signal passes through filter 72 to produce a high B signal and an inverted low signal for use in the various control and logic circuits indicated.
• movement of the direction-control lever to reverse position will generate a high A signal and a low signal, Switches 70 and 71 are mechanically interlocked to prevent simultaneous closure.
• Accelerator pedal 25 is mechanically linked to switch 73 and to the adjustment member 74 of potentiometer 75. Switch 73 will close in response to initial depression of the pedal 25 and will remain closed until the pedal is fully released.
• the accelerator-switch signal A S is filtered and appears as signal F.
• the degree of movement of adjustment member 74 will depend on the amount that the accelerator pedal is depressed, and the operator-demand signal V OD will vary from 0 to V S2 volts in accordance with the degree of such depression.
• the V OD signal is also applied to the base of transistor 76 to vary the conductance thereof and produce a positive voltage signal that varies inversely with V OD .
• the V OD signal is applied to voltage-controlled oscillator (VCO) 77 to produce a frequency signal F DM whose frequency is directly proportional to the voltage input thereto, i.e., to the degree of pedal depression and thus to the speed demanded by the operator.
• VCO voltage-controlled oscillator
• F DM frequency signal
• An RCA CD4046 may be used for this VCO as well as for the VCO's in the circuits described hereinbelow.
• the inverse signal is applied to VCO 78 to produce a frequency signal T 2 whose frequency is proportional to the magnitude of signal and thus inversely proportional to the operator demand.
• Signal T 2 is applied to and down-counted by counter 79 to produce a frequency signal T 1 whose frequency is also inversely proportional to the operator-demanded speed.
• the T 1 signal is used in FIG. 11 to control the field current.
• FIG. 3 also includes a pair of operational amplifiers 80 and 81, and associated conventional circuitry to amplify the millivolt signals produced by the field and armature shunts 49 and 56 (FIG . 2) .
• the amplifiers have gains of about 100 to amplify the input current signals to more workable voltage levels .
• a zero millivolt s ignal from shunt 56 (corresponding to ze ⁇ o current flow in the armature) will result in an output V IA from amplifier 81 equal to V S 3 (nominally 6.8 volts) .
• a +50 millivolt signal from shunt 56 resulting from power flow through the armature causes the output of amplifier 81 to be V S 3 plus 5.0 volts.
• the level of the signal V IA above the zero current reference level of V S3 is proportional to the magnitude of the power current flowing through the armature. If in a braking or plugging mode the direction of current flow through the armature will be reversed and the polarity of the signals applied to amplifier 81 will be reversed, A -50 millivolt signal from shunt 56, during braking or plugging mode, will decrease the level of signal V IA from V S3 by 5.0 volts.
• the degree by which the level of signal V IA is decreased from the 6.8-volt zero-reference level is proportional to the magnitude of brake current through the armature.
• the output signal V IA is always positive, however, whether power, brake or no current is flowing through the armature.
• Operational amplifier 80 will also have a V S3 (6.8 volts) output (signal V IF ) if the field current is zero. Since current can only flow in one direction through the field shunt 49, the signal V IF will only vary upwardly from the 6.8-volt zero-reference level and in an amount therefrom proportional to the magnitude of the field current.
• V S3 (6.8 volts) output
• FIG. 4 illustrates a portion of the reference signal generators and comparator circuits of the motor control, and more particularly the portion which compares the actual speed of the motor and the speed demanded by the operator by actuation of the accelerator pedal.
• the Nwp signal generated by the speed pickup 65 (FIG. 2) is passed through an a.c. amplifier 82 to remove the d.c. bias level and to amplify the ripple pulses.
• the signal is then passed through a Schmitt trigger 83, a logic inverter 84 and a delay/filter circuit 85 to produce square wave pulses N M1 which have a frequency proportional to the actual motor speed.
• Transmission gate 86 controlled by NAND gate 87, is used to affect the time delay of delay/filter circuit 85.
• the square wave pulses Nw. are fed into a phase locked loop consisting of phase/frequency comparator ( ⁇ C) 89, a low pass filter 90, VCO 91, and two counters 92 and 93,
• the external capacitor and resistors of VCO 91 are chosen so that the frequency of actual motor speed signal, F AM , generated by VCO 91, is 64 times that of the N M1 signal for all motor speeds above 45 rpm.
• Resistor 94 sets a minimum frequency of F AM corresponding to an actual motor speed of 45 rpm even though the actual speed is below 45 rpm.
• the F AM signal from VCO 91 is down-counted by counters 92 and 93 to produce signals F AM2 and F AM1 , signal F AM2 having a frequency 1/32 that of F AM , or twice the frequency of signal N M1 for any actual motor speed above 45 rpm.
• the frequency of signal F AM1 is 1/64 that of F AM and thus is equal to the frequency of the N M1 signal for actual motor speeds above 45 rpm.
• the F AM1 signal is fed back to comparator 89 to lock the frequencies of the F AM , F AM2 and F AM1 signals relative to the frequency of the N M1 signal for all actual motor speeds above 45 rpm.
• An inverter oscillator 95 (used for speed governing) produces a constant frequency reference signal F TSM proportional to the desired top speed limit of the motor.
• the control may be customized for a particular vehicle to limit the top speed thereof by changing the value of resistor 96.
• the F TSM and F AM signals are fed to a phase/frequency comparator 97 whose output will pulse high, and thereby (through filter arrangement 98) produce a high signal G when the actual motor speed signal F AM is greater than the top speed reference signal
• Fmgw. Logic inverter 99 will produce an inverted G signal.
• the speed demanded by the operator (by the accelerator pedal) and the actual speed of the motor are continuously monitored and compared in order to determine whether the motor should accelerate or decelerate. Regardless of what the demanded and actual speeds might be at any given time, if the demanded speed is greater than the actual speed, then the motor should accelerate so that its speed will increase to the speed which the operator wishes. conversely, if the demanded speed is less than the actual speed, then the motor should decelerate.
• the F DM signal has a frequency proportional to the demanded speed and the F AM signal (and the derivative F AM1 and F AM2 signals) has a frequency proportional to the actual speed of the motor.
• the actual and demanded speeds are equal -- regardless of the speed -- the frequency of the F AM and F DM signals are equal.
• the F AM and F DM signals are compared to generate a deceleration signal as follows.
• the F DM signal from FIG. 3 is passed through transmission gate 100 (which is closed for transmission therethrough as long as the actual motor speed is below the top speed reference and signal G is high) and is fed to the phase/frequency comparator 102 together with the F AM signal.
• the output of comparator 102 is low. If the frequency of the demanded speed signal is less than that of the actual motor speed, the output of comparator
• the 102 will pulse high, generating signal U which signifies that deceleration is desired.
• U which signifies that deceleration is desired.
• the absence of the U signal indicates that the actual and demanded speeds are equal or that acceleration is desired.
• the demanded and actual speed signals are also compared to determine the magnitude of difference therebetween so that the rate of acceleration or deceleration may be controlled.
• the higher the demanded speed is relative to the actual speed the greater the acceleration rate should be so that the motor may be quickly brought up to the demanded speed.
• the lower the demanded speed is relative to the actual speed the greater the deceleration rate should be to reduce the motor speed to that which is desired.
• the magnitude of the difference between the demanded and actual speeds is obtained by counting the number of cycles of the demanded speed signal F DM per cycle of the actual motor speed signal F AM2 (derived from the F AM signal and thus proportional to the actual motor speed).
• the F DM signal which passes through gate 100 is also passed through transmission gates 103 and 104 and buffer 104a to the clock input of counter 105.
• Gate 104 is closed by a high F AM2 signal and will remain closed until the F AM2 signal goes low. Thus, gate 104 will be closed during the time that thirty-two F AM pulses are generated. The gate will then open after the thirty-second F AM pulse and reclose after thirtytwo more F AM pulses have been generated. The length of time that gate 104 will remain closed, each time it closes, is thus inversely proportional to the actual speed of the motor. If the actual and demanded speeds are the same, then the F DM and F AM frequencies will be equal and thirty-two F DM pulses will pass through gate 104 each time it is closed and will be counted by counter 105. This will be true, regardless of what the actual speed may be at the time.
• Counter 105 is reset by the F AM1DD signal which is double-delayed by delay circuits 106 and 107 so that counter 105 is reset during the time that gate 104 is open.
• the count in counter 105 will be greater than thirty-two. As is apparent, the higher the demanded speed is relative to the actual speed, the higher the count in counter
• the count in counter 105 will increase or decrease as the demanded speed signal F DM increases or decreases. If the frequency of the demanded speed signal remains constant, the count in counter 105 will increase if the motor slows and will decrease as the motor speeds up.
• the third through seventh binary outputs of counter 105 are combined by NAND gates 108 and 109 and NOR gate 110 and applied to the D input of flip-flop 111 and clocked therethrough to the Q output by the delayed F AM1 signal, F AMID .
• the ACC OO deceleration signal at the Q output is low if the demanded speed per actual speed count is less than 24, and is high if the count is 24 or greater.
• the third, fourth and fifth binary outputs of counter 105 are combined by NAND gates 112 and 113 and NOR gate 114 (FIG. 4), and applied to the first and second inputs of shift register 115.
• the sixth and seventh outputs of counter 105 are applied directly to the third and fourth inputs of shift register 115.
• the inputs of shift register 115 are clocked through to the corresponding Q outputs by the F AMID pulse during the time that transmission gate 104 is open.
• Acceleration signals ACC 1 , ACC 2 , ACC 3 and ACC 4 and their inverses are obtained from the Q outputs of shift register 115, and the levels of these signals to the demanded/actual speed count in counter 105 is as follows:
• the sixth and seventh outputs of counter 105 are combined by logic gate 116 to maintain transmission gate 103 closed as long as the count of counter 105 does not exceed 192, thereby preventing overflow of the counter.
• the first through fourth outputs of counter 105 are also applied to the inputs of shift register 117.
• Flip-flop 116a, inverter 116b and NAND gate 116c enable the inputs of shift register 117 to be clocked to the outputs thereof by either a high fifth output of counter 105 or the F AMID signal.
• the latched output signals of register 117 are fed into an R/2R resistor network 118 for digital-to-analog conversion to establish the level of voltage signal V CLB which is used in FIG. 6 to establish a reference for current-limiting in the armature during braking. The lower the count in counter 105
• V CLB the level of voltage signal
• transmission gates 100 and 101 will open and close, respectively, to disconnect the F DM signal from counter 105 and instead apply the frequency signal F TSM thereto.
• FIG. 4 also includes a fixed frequency voltage controlled oscillator 119 which generates reference frequency F RC for creep speed. This reference frequency is compared with the operator-demand frequency F DM in comparator 120, and the output signal M will be high if the demanded speed is less than the established creep speed of the vehicle.
• the M signal is applied to shift register 115 to reset the register and thus inhibit the generation of the acceleration signals ACC 1 -ACC 4 when in the creep mode, i.e., when the signal M is high.
• the high M signal is also used in FIG. 10 to shorten the armature pulse width,
• FIG. 5 illustrates another portion of the reference signal generators and comparator circuits of the control system.
• a fixed-frequency voltagecontrolled oscillator 125 generates a reference frequency 2F B , which for the disclosed embodiment has a frequency equal to the frequency of the actual speed signal F AM1 when the actual motor speed is 1920 rpm.
• This reference frequency is applied to counter 126 and downcounted thereby, with the second through fourth binary outputs being applied to comparators 129, 128 and 127.
• the reference frequency 2F B is applied directly to comparator 130.
• the F AM1 signal having a frequency proportional to actual motor speed, is also applied to these comparators.
• the output signals from the comparators are as follows:
• FIG. 6 illustrates the remaining portion of the reference signal generators and comparator circuits of the control system, wherein the field and armature currents are compared to established references.
• variable voltage signal V IF which is proportional to the current in field 21 is applied to VCO
• a VCO 143 generates a fixed frequency signal F IFMAX whose frequency corresponds to a predetermined maximum allowable level of field current, this frequency signal being applied to comparator 141.
• Fixed frequency VCO 144 generates a frequency signal F IFMIN whose frequency corresponds to a predetermined minimum level of field current, this frequency signal being applied to comparator 142.
• the outputs of comparators 141 and 142 generate the following control signals (see also FIG. 16):
• the E signal is used in FIG. 6 in the generation of the "last-commanded-direction" signals C and which are used subsequently in FIG. 8 to control operation of the contacts 40, 41, 44 and 45 of the field relays, and prevent them from opening when more than minimum field current is passing therethrough.
• the E signal is combined with the motor speed signal (from FIG. 5) by logic gate 145 whose output, is low when field current is below minimum reference and the actual motor speed is below 120 rpm. (This signal is in verted to form signal V DE which is used in FIG. 10).
• the signal is applied to NOR gates 146 and 147. If the operator commands a forward direction, signal at the input of gate 146 will be low.
• Armature current signals are generated in FIG. 6 as follows.
• the variable voltage signal V IA from amplifier 81 of FIG. 3 is applied to VCO 150 to generate a frequency signal F IA proportional to the magnitude of signal V IA As will be noted from FIG.
• signal V IA With zero armature current, signal V IA will be 6.8 volts and VCO 150 will generate a frequency signal F IA of approximately 60 KHz, As the signal V IA increases in magnitude (from an increase in power current through the armature) the frequency of signal F IA will increase proportionally. If in a plug mode, an increase in plug current will reduce the level of the signal V IA from 6.8 volts and will cause the frequency of signal F IA to decrease proportionally. Thus, the frequency of signal F IA provides information as to the magnitude of armature current and whether such current is power current or brake current.
• the armature current frequency signal F IA is applied to phase/frequency comparators 151, 152 and 153, which provide signals that indicate where the armature current is, relative to predetermined minimum and maximum levels of power current, or relative to a maximum level of brake current. (See FIG. 14).
• a fixed frequency reference signal F IAO is generated by VCO 154, this signal having a frequency somewhat above 60 KHz and corresponding to a predeterr mined minimum amount of power current through the armature (e.g., approximately 80 amperes).
• Signal F IAO is applied to comparator 151 for comparison with signal F IA . If the two signals indicate that the magnitude of actual power current through the armature is less than this predetermined minimum, the output of comparator 151 will produce a high signal J. If brake current is flowing through the armature, the frequency of the F IA signal will always be less than the frequency of the signal F IAO and the signal J will be high, regardless of the amount of brake current. Inverted signal is also available.
• the maximum allowable level of armature power current is set by the F CLA signal generated by VCO 155 and applied to comparator 152, If the armature power current is belov/ the maximum allowable level, signal K will be high. If the power current exceeds such level, the signal K will go low. The inverse signal will be low or high, depending upon whether the armature power current is less or greater than the F CLA current limit level.
• variable voltage signal F CLA to the Input of VCO 155 so that the frequency of the F CLA signal will vary (between the minimum and maximum frequencies established by the external resistors and capacitor connected to the VCO) in accordance with the level of the Vp.. signal.
• the level of the V CLA signal will vary inversely as a function of the actual and demanded speeds. Accordingly, the greatest allowable armature current level will be set at low speeds of operation, with such current level limit being decreased when operating at high speeds.
• Transmission gate 156 is used to apply the fixed voltage at the junction of voltage-dividing resistors 156a and 156b to the input of VCO 155.
• Such fixed voltage is between the maximum and minimum limits of the V CLA voltage and thus serves to establish a minimum voltage level to the input of VCO 155 whenever the demanded acceleration is sufficient to generate the signal ACC 3 .
• the V CLA voltage signal will decrease and the current limit signal F CLA will decrease.
• the V CLA signal will be the same as that between the junction of resistors 156a and 156b. If only a relatively small degree of acceleration is demanded at such time, gate 156 will be open and the frequency of the F CLA signal will continue to drop as the level of V CLA drops.
• gate 156 will close, so that the frequency of the F CLA signal will stay the same even though the level of the V CLA signal drops. This enables the motor to continue in operation at a relatively high current limit level for high torque, as long as the demand for acceleration is high.
• gate 156 will open and VCO 155 will be controlled in response to the magnitude of the V CLA signal again.
• the frequency of operation of VCO 155. i.e., the frequency of signal F CLA
• the circuit operates as follows. Normally transmission gate 158 is open and external resistor 157 is in the circuit. If the load on the motor is such that the armature current increases above the current limit level, i.e., if the frequency of signal F IA is greater than the frequency of the current limit signal F CLA , the overcurrent signal K will go low.
• NOR gate 159 This signal is applied to NOR gate 159, and if the motor speed is below 120 rpm (so that D is low) NOR gate 159 will output a high to close transmission gate 160 so that F BM/4 pulses will be applied to counter 161.
• the overcurrent signals K and K will affect the operation of the armature and field pulsing circuits so that the armature current reduces, with normal operations being resumed when the armature current reduces below the current limit level (F CLA ).
• a continued load on the motor again causes the armature current to increase above the current limit level so that the K signal again goes low to allow more F BM/4 Pulses to go to counter 161.
• Transmission gate 158 opens and restores resistor 157 to the RC circuit of VCO 155 for normal operation.
• the maximum allowable armature current is set by the power current limit signal F CLA .
• the maximum allowable armature current when the motor is operating in a braking mode is set by the brake current limit signal F CLB which is generated by VCO 165.
• Comparator 153 continuously compares the armature current signal F IA and the brake current limit signal F CLB . As long as the armature brake current is less than the allowable current limit, the frequency of the signal F IA will be greater than that of the signal F CLB and the signal L will be high. If excessive brake current flows through the armature, F IA will be lower than F CLB and the signal L will go low.
• the frequency of operation of VCO 165 will vary in accordance with the magnitude of the V CLB signal applied to the input thereof and within the range set by the external capacitor and resistors of the VCO.
• the minimum frequency of operation of VCO 165 (with zero Vp.g input thereto) is set as a function of capacitor 166 and resistors 168a and 168b, while the maximum frequency of operation (with maximum V CLB input) is the minimum frequency plus a function of capacitor 166 and resistors 167a and 167b.
• the level of the V CLB signal will vary inversely with the degree of demanded deceleration. The greater the demanded deceleration, the lower the level of the V CLB signal, and vice versa. Since the frequency of the brake current limit signal F CLB varies directly with V CLB the frequency of the F CLB signal also varies inversely with the degree of demanded deceleration, so that as more deceleration is demanded, the amount of maximum allowable armature brake current will increase.
• braking will either be regenerative (with brake current flowing through SCR RB , to recharge the battery) of resistive (with the armature shorted by SCR B ) .
• resistive with the armature shorted by SCR B
• the present circuit operates to allow a higher armature brake current during resistive braking, as follows.
• the and signals from FIG. 10 and the signal from FIG. 5 are all applied to NAND gate 169 which logically combines them to produce a high output if the system is in a regenerative braking mode or a low output if in resistive braking.
• NAND gate 169 In order to keep the maximum frequency the same, the output of NAND gate 169 is inverted by inverter 169a and applied to transmission gate 167c to short out resistor 167b when in resistive braking. With a proper relation between the external resistors the maximum frequency of VCO 165 will remain substantially the same whether resistor 168b is shorted by transmission gate 168c or not.
• an indication of excessive armature power current (the K and it signals) is obtained when the F IA signal exceeds the predetermined maximum frequency set by F CLA while an indication of excessive armature brake current is obtained when the frequency of the F IA signal goes in the opposite direction from the zero-current reference frequency and goes below the predetermined minimum frequency set by F CLB
• the level of excessive power current can be set completely independently of the level of excessive brake current, and vice versa, and each level can be varied without affecting the other
• FIGS. 7-9 illustrate the control logic portion of the control system wherein various of the control signals generated in the system are combined to produce command signals.
• FIG. 7 will be discussed after the armature and field pulsing circuits have been described.
• FIG. 8 illustrates the logic portion wherein the forward and reverse signals FWD and REV are produced, these signals being used in FIG. 2 to energize one or the other of the coils 39 or 43 of the direction relays and close the contacts thereof to connect the motor field into the power circuit.
• Signals A, B, C, D, , E and E are logically combined by NAND gates 170, 171, 172, 173 and 174.
• the forward signal FWD at the output of gate 174 will be operatively high if one or more of the following conditions exist.
• the last commanded direction was forward (C) and a forward direction (B) is presently commanded.
• the A, B, D, , E and E signals are combined by NAND gates 175, 176, 177, 178 and 179 to produce the REV signal at the output of gate 179.
• the REV signal will be high if one or more of the following conditions exist: (1) The last commanded direction was reverse and the field current is above minimum
• the last commanded direction was reverse ( and reverse direction is presently commanded (A).
• the A, B, C, , DR F and DR R signals are combined by NAND gates 18 ⁇ , 181, 182, 183 and 184 to produce signal V FE which must be high in order for the field 21 and armature 20 to be energized.
• the signal V FE will be high if any one of the following conditions exist: (1) Reverse direction is being commanded (A), the last commanded direction was reverse , the reverse contacts 44 and 45 have closed and have actuated microswitch 47 to closed position (DR R ); or, (2) forward direction is being commanded
• V FE is combined with the L and H signals by NAND gate 185, whose output, V FO , will be low if V FE is high and the field current is below maximum reference (H) and if the armature brake current level is less than the allowable braking reference (L) .
• NOR gate 186 The DR F and DR R signals are combined by NOR gate 186, whose output will be low if either the DR F or DR R signal is present. If both the output of gate 186 and the V FO signal are low, the output of NOR gate 187 will be high. This output is combined with the Vwr signal from FIG. 10, and when both are high the output of NAND gate 188, V FI , will be low.
• V FI when low, is used in FIG. 11 to allow the main SCR for the field, SCR MF , to be turned on and off to supply power to the field. If the field inhibit signal V FI goes high, SCR MF will be inhibited from turning on.
• the deceleration signal ACC OO is combined with the signal by NAND gate 190 whose output is inverted by logic inverter 191 to produce a deceleration command signal V DEC , which signal will be high if the demanded/actual speed count from counter 105 (FIG. 4) is below 24 and the motor speed is above 120 rpm ( high). Otherwise, V DEC will be low.
• a plugging condition i.e., when the motor is being powered in one direction and the opposite direction is commanded by the operator by movement of lever 24, is indicated as follows.
• the B, C, A and signals are combined by NAND gates 192, 193 and 194. If a plugging situation does not exist, i.e., if the motor is operating in a forward direction (B) and the last commanded direction is forward (C), or if the motor is operating in a reverse direction (A) and the last commanded direction is reverse , the signal will be high. If the motor is being operated in one direction and the opposite direction is commanded, signal will go low.
• Logic inverter 195 thus causes signal V PG to be high when a plugging condition exists, this signal being used in FIG.
• the plugging and deceleration signals V PG and V DEC are also used in FIG. 9 to generate a high signal during either plugging or deceleration.
• the V DEC signal is applied to NOR gate 198, so that when the V DEC signal is high, the output of gate 198 will be low and be inverted to high by logic inverter 199. If either V DEC or V PG is high, the output of NOR gate 200 will go low and be inverted to a high signal by logic inverter 201.
• the high signal is used in FIG. 11 to boost the pulse frequency and pulse width of the oscillator for the main field SCR, SCR MF .
• a high signal is also produced by combining the K and T signals.
• both of these signals are low, i.e., when there is excessive armature power current at speeds below 1920 rpm, the output of NOR gate 202 will go high, causing the output of NOR gate 198 to go low. Again, such low signal will be inverted and applied to NOR gate 200 so that its output will go low to produce an inverted high signal.
• FIG. 9 also includes logic circuits for producing or inhibiting the production of a high V AO signal. This signal, when high, is used to turn on the pulse generator for the main armature SCR MA When the V AO signal is low, the pulse generator is inhibited from operating.
• Signals A and B are applied to NOR gate 203 whose output will be low if either a forward or reverse direction is being commanded by the operator.
• the output of gate 203 and the E signal are applied to NOR gate
• V CLC will be high if a direction is being commanded and if the field current is above minimum reference.
• the high V CLC signal is used in FIG. 6 to reset counter 161 and flip-flop 162 when the motor speed increases to more than 240 rpm and signal W goes low).
• V CLC The V CLC signal is inverted by logic inverter
• NAND gate 206 and combined with signal D (high when the motor speed is less than 120 rpm) by NAND gate 206.
• the output of gate 206 is combined with signal F (high when the accelerator switch 27 is closed), and by NAND gate 207, whose output is fed to NOR gate 208.
• the output of gate 198 is combined with the V FE signal by NAND gate 209 whose output is also fed to gate 208,
• the V CBT signal (used to open circuit breaker contacts 35 and 37) is also applied to gate 208.
• the output of gate 208 is signal V AO , which will permit operation of the main SCR for the armature, SCRw., when the V AO signal is high.
• the V A0 signal will be high if all of the following conditions exist:
• V CBT The circuit breaker trip signal
• V FE a high field enable signal
• V DEC is low
• FIG. 10 discloses the armature pulsing circuitry.
• the circuits of FIG. 10 are used to control the operation of the SCR's associated with the armature, both in power mode and in braking.
• the armature current is controlled by repeatedly turning the main armature SCR MA on and off to vary the average power current through the armature. If acceleration is not being demanded, the rate at which the SCR MA is turned on is dependent upon the degree of operatordemanded speed and the SCRw. will remain in conduction for a fixed length of time each time it is turned on.
• the rate at which the SCR MA is turned on will be boosted and the time of conduction will be lengthened, such boosting and lengthening being a function of the degree of demanded acceleration .
• the main SCR MA In the power mode and at motor speeds above 1920 rpm the main SCR MA will remain in continuous conduction and the speed of the motor will be controlled by varying the field current with the circuits of FIG. 11.
• the circuits of FIG. 10 function in the braking mode to inhibit the turning on of the main SCR MA and to turn on the regenerative braking SCR RB if the motor speed is above 1920 rpm or to turn on the resistive braking SCR B if the motor speed is below 1920 rpm.
• a one-second delay is provided before the resistive braking SCR B is turned on to ensure against both SCR RB and SCR B being in conduction at the same time.
• the circuits of FIG. 10 further function when the motor comes out of a braking mode and returns to a power mode to turn on the commutating SCR CA and commutate the resistive braking SCR B before the main SCR is turned back on.
• the basic operation of the power mode circuitry starts with the operator demand signal V OD from FIG. 3, the voltage of which is proportional to the setting of the accelerator-pedal-controlled variable resistor 75. This signal is passed through an RC filter (resistor
• Resistor 220 and capacitor 221 are used for jerk control to allow a gradual increase of the voltage applied to VCO 222 in the event the magnitude of signal V OD is suddenly increased by an abrupt depression of the accelerator pedal by the operator.
• the frequency signal F ADI is downcounted by counter 223 and NAND gate 224 to produce frequency signal F AD which is also proportional to the degree of the operator demand signal V OD .
• the F AD signal clocks flipflop 225 to generate trigger pulses being then applied to the trigger input of monostable multivibrator 226 (MONO 2).
• Monostable multivibrator 226 (as well as the other monostable multivibrators hereinafter identified) will produce a single pulse in response to each trigger pulse applied thereto, the length of the monostable pulse being dependent on the values of the external capacitor and resistors connected to terminals 1, 2 and 3 of the monostable, i.e., capacitor 227 and resistors 228-232.
• positive-edge triggering is accomplished by application of a leading-edge pulse to the "+T" input and a low level to the "-T" input.
• negative-edge triggering7 a trailing-edge pulse is applied to the "-T" input and a high level is applied to the "+T".
• Input trigger pulses may be of any duration relative to the output pulse.
• the monostable can be retriggered, on the leading edge only, by applying a common pulse to both the "+T" and "RT" inputs.
• the output pulse, at Q remains high as long as the period between the leading edge of consecutive trigger pulses is shorter than the pulse period of the monostable as determined by its RC components. In the period between monostable pulses, its Q and outputs will be low and high, respectively.
• Such monostable multivibrators as described and used herein are commercially available, as for example, the RCA series CD4047A COS/MOS Low-Power Monostable/Astable Multivibrator.
• Signal and delayed signal are obtained from the output of monostable 226, these signals being high in the period between the end of a pulse and the beginning of the next pulse of monostable 226.
• signal is obtained from the output of monostable 240, this signal being high in the interpulse period of monostable 240.
• Capacitor 242 and resistor 243 are connected between supply voltage V S2 and ground to produce a reset voltage signal R upon initial start-up, which signal is used to reset monostables 226 and 240 and the monostables in the field pulsing circuitry (FIG. 11).
• monostable 226 will pulse, and the main and charging SCR's for the armature will be gated on at a rate proportional to the degree of operator demand. As V OD increases, the pulse rate of monostable 226 will increase, and vice versa.
• the on-time of the main SCR MA will be substantially the same as the pulse duration of monostable 226 since the commutating SCR CA is not gated on by monostable 240 until the end of the pulse of monostable 226. Conduction of SCR MA is thus dependent upon the pulse frequency and. pulse length of monostable 226.
• the pulse frequency and pulse width of monostable 226 is affected by the acceleration signals produced in FIG. 4 in response to a difference between actual motor speed and demanded speed.
• the acceleration signals ACC 1 , ACC 2 , ACC 3 and ACC 4 are applied to transmission gates 245, 246, 247 and 248 to close these gates when the acceleration signals are high and thereby connect the supply voltage V S2 through one or more of the weighted network of resistors 249, 250 and 251 and thereby cause a boosting of the voltage input into VCO 222 so that the frequency F ADI is increased beyond that demanded by signal V OD .
• This increases the pulsing rate of monostable 226 during acceleration, with the pulse rate being increased proportionally to the degree of acceleration being demanded.
• the pulse length of monostable 226 is dependent upon the resistance values of resistors 228-232.
• signal When the motor speed is below 1920 rpm, signal will be high, and transmission gate 255 will be closed. If no acceleration is called for, the and signals will all be high, closing transmission gates 256, 257 and 258, thereby connecting resistors 230, 231 and 232 in parallel with resistor 228. If acceleration is called for, so that one or more of the , or signals goes low, its transmission gate will open, resulting in an increase in resistance between terminals 2 and 3 of monostable 226 and a longer pulse length of the monostable.
• the acceleration signals increase both the pulse frequency and pulse length of the monostable and thereby increase the amount of current flowing to the armature through SCR MA beyond that called for by the operator-demand signal.
• gate 255 opens, to increase the pulse length whether or not acceleration is demanded.
• Signals K, T and M are combined by NOR gates 260 and 261, the output of gate 261 being inverted by logic inverter 262 and applied to transmission gate
• Resistor 228 is sized so that when it alone is in the circuit, the pulse length of monostable 226 is sufficiently long relative to the frequency of the trigger pulse from flip-flop 225 at this speed that the monostable operates in its retTigger mode, i.e., the output remains high and the Q output remains low. In such mode, the commutating SCR CA does not fire and the main SCR MA remains on continuously so that full battery power is applied to the armature and no commutating power is lost. As may be seen from the foregoing, the single monostable 226 provides great flexibility in the control of armature current.
• the leading edge of the output pulse is used to gate the main SCR MA into conduction, while the trailing edge of the pulse is used (by monostable 240) to commutate the main SCR MA .
• the pulse rate and pulse width of the monostable are independently controllable so that the rate at which the main SCR MA is gated on is controlled by this monostable as well as the length of time that SCR MA remains in conduction each time it is gated on.
• the monostable can be put into retrigger operation for continuous current flow to the armature.
• the output of NOR gate 275 will go high to clock the voltage at the D input of flip-flop 276 through to its Q output, which will pulse high if the D input is high and thereby trigger monostable 277 (MONO 5).
• the speed signal D is applied to the D input of flip-flop 276 so that the flip-flop will only pulse high if the actual speed is greater than 120 rpm. This monostable produces a fixed-length pulse of approximately one second duration.
• the Q output which goes low for the one-second time, is applied to NAND gate 271 to provide a one-second delay between the time that the GA RB , signals cease and the GA B , signals start, to ensure against simultaneous conduction of SCR RB and SCR B .
• the Q output of monostable 277 is applied to the inhibit input of VCO 222 to inhibit operation and ground the output of VCO 222 during the one-second pulse of monostable 277.
• the G signal high when the actual motor speed is above top reference speed, is used at such time to reset counter 223 and maintain it reset so that no F AD pulses are produced and the monostable 226 is thereby inhibited from pulsing until the actual speed reduces to below the top reference speed.
• the Q output of flip-flop 281 is inverted by logic inverter 283 and applied to NOR gate 284, so that when the Q output of flip-flop 281 is low the output of gate 284 is low and flip-flop 225 is inhibited from operating.
• transmission gate 291 will open and monostable 226 will be taken out of retrigger mode operation.
• the E signal high during braking, is used to take monostable 226 out of retrigger mode to prevent a lockage condition, wherein the monostable 226 stayed on even though the input pulses thereto were resumed during braking. Disconnecting the retrigger input from the +T input at such time alleviates such lockup.
• the VDE signal when high, i.e., when the motor speed is less than 120 rpm and the field current is less than minimum reference, will close transmission gate 292 and allow jerk capacitor 221 to discharge through resistor 293 so thatjerk control is provided on the next acceleration.
• FIG. 11 discloses the field pulsing circuit.
• the field is controlled in power operation by varying the field excitation as an inverse function of the demanded and actual speeds, i.e.,
• the excitation of the field is varied by controlling the field current as an inverse function of the demanded and. actual speeds. Since the demanded speed signal T 1 from FIG. 3 is inversely proportional to the degree of the operatordemanded speed and since the actual speed signal F AMI from FIG. 4 is directly proportional to the actual speed of the motor, field excitation is controlled as follows:
• the frequency of the F AMI signal is substantially higher than the frequency of the T 1 signal and a count is repeatedly obtained which is proportional to the number" of cycles of the F AM1 signal occurring during each cycle of the T 1 signal.
• the field current is then regulated so that it varies inversely with the magnitude of such count.
• the field pulsing circuit provides automatic field weakening in the event acceleration is demanded and automatic field strengthening in case of excessive armature power current. In the braking mode, the field pulsing circuit functions to maintain the armature brake current at the maximum permissible brake current limits.
• the T 1 pulses from FIG. 3 pass through logic inverter 301 and delay circuits 302 and 303 to the reset input of binary counter 304, so that the counter is reset at a rate inversely proportional to the demanded speed.
• the T. pulses also act through NOR gate 305 to close transmission gate 306 so that the F AM1 pulses (proportional to actual motor speed) can pass therethrough to the counter.
• the count in counter 304 will be a function of the demanded speed and the actual motor speed. If the demanded speed increases while the actual motor speed remains the same, the T 1 frequency will decrease so that more F AM1 pulses are counted for each T 1 pulse.
• the shift register 310 when in the power mode, the shift register 310 will be continuously clocked as long as acceleration is demanded.
• clocking of shift register 310 will stop, and the outputs will remain latched at the last clocked state until such time as acceleration is again demanded and the shift register is newly clocked.
• the shift register 310 is also clocked once after return of the system to power mode from a braking mode. During braking, the demanded and actual speeds will have decreased so that the count in counter 304 will have increased. During such time the outputs of shift register 310 will not have changed, since no clock pulse has been applied thereto.
• the output of NOR gate 282 when the system returns to power mode from braking operation the output of NOR gate 282 will go high and then low after the first F AD pulse.
• the output of NOR gate 282 is inverted in FIG. 11 by logic inverter 310d and momentarily causes gate 310b to output a high to flip-flop 310c.
• the next T. pulse can then clock shift register 310 so that the increased count at the inputs thereof are clocked to the outputs.
• NOR gate 282 then goes high and shift register 310 will not then be clocked again until such time as acceleration is demanded.
• the binary count at the inputs will be inverted at the outputs.
• the latched and inverted count is applied to the R/2R resistor network 311 for digital-to-analog conversion.
• the output voltage of network 311 is applied to the voltage divider comprised of resistors 312, 313, 314 and 315, and then through a negative jerk filter comprised of resistor 316 and capacitor 317 to the input of voltage-controlled oscillator 318.
• VCO 318 thus oscillates and produces pulses F D1 at a frequency which varies inversely with the count in counter 304, i.e., inversely with the operator demanded speed and actual motor speed.
• the digital-to-analog conversion network 311 utilizes six inputs from register 310 and thus provides sixty-four discrete steps of conversion so that the incremental change of output voltage is relatively small, for smoother operation, as the count increases or decreases.
• the output of the digital-to-analog R/2R network 311 is also used as the source of the F CLA signal which is used in FIG. 6 to set the frequency of the armature power current limit signal F CLA as an inverse function of the count in counter 304.
• Resistors 312 through 315 are sized relative to those of the R/2R network 311 so as not to load the output of the R/2R network.
• the monostable 320 (MONO 1). As before, the monostable 320 will produce one pulse for each trigger pulse applied thereto, the length of the pulse being dependent upon the values of capacitor 321 and resistors 322 and 324-331 in the RC circuit of the monostable.
• the normally high output of monostable 320 is fed to monostable multivibrator 332 (MONO 4), having a fixed length pulse, so that the end of the pulse of monostable 320, monostable 332 will generate a pulse.
• the output of monostable 320 and the Q output of monostable 332 are combined by NOR gate 333 so that each time monostable 320 pulses a high signal GA MF/LF is produced at the output of gate 333, which passes to FIG. 12 for amplification and then to FIG. 2 to gate the commutating SCR, SCR CF , for the field.
• the operational states of monostables 320 and 332 are indicated by the and signals taken from the outputs, these signals being high during the interpulse periods of the monostables.
• the pulse frequency of monostable 320 is inversely proportional to the demanded and actual motor speeds, so that the main field SCR MF will pass less current and thereby provide field weakening at high speeds. Conversely, field strengthening is provided at low speeds.
• the pulse frequency of monostable 320 is also automatically increased if the armature power current is excessive or if the system is in a regenerative braking mode.
• the T, and signals are logically combined by NAND gate 336, inverter 337 and NOR gate 340, so that if there is excessive armature power current (K is high) or if the system is in regenerative braking (T, and are all high) the output of NOR gate
• transmission gate 342 closes transmission gate 342 to apply supply voltage V-2 to the junction of resistors 313, 314 and 316 and thereby boost the voltage applied to VCO 318, raise the frequency of the pulses to the main field SCR MF and cause the field to be strengthened.
• the highest output of shift register 310 is applied to transmission gate 343.
• resistor 313 When this gate is closed, resistor 313 will be shorted out so that the amount of the output from the R2R output applied to VCO 318 is boosted to cause field strengthening.
• the voltage divider network of resistors 312-315 is also affected by transmission gate 344 which will short out resistor 315 when the output of NOR gate 345 is high, i.e., when both of the signals and are low. If the motor speed is below 480 rpm (3 is high) or if in a plugging or decelerating mode (Vwp is high) , gate 344 will open, putting resistor 315 in series with resistor 316 to boost the voltage to VCO 318 and cause field-strengthening.
• gate 344 will close to short out resistor 315 and reduce the input to VCO 318 for field-weakening.
• the V M5 signal (high during the one-second pulse period of monostable 277) is used to close transmission gate 346 to allow the negative jerk capacitor 317 to discharge through resistor 347 during that period.
• the V FI signal from FIG. 9 is applied to VCO 318 and flip-flop 319 to allow operation thereof when the V FI signal is low and to inhibit operation when the V FI signal is high.
• V FI when the system is in a power mode, signal V FI will normally be continuously low so that the field will be continuously pulsed.
• the V FI signal When operating in a braking mode, the V FI signal will be low or high primarily in dependence upon whether the armature brake current is below or above the maximum allowable limit set by the F CLB signal, and the V FI signal will thus control the operation of the VCO 318, flip-flop 319 and monostable 320 to maintain the armature brake current at the F CLB level.
• monostable 320 has a plurality of resistors 322-331 in its external RC circuit, these resistors being provided to enable the pulse length of the monostable to be varied,
• the four highest outputs of counter 304 are logically combined by NOR gate 350, NAND gates 351 and 352 and logic inverters 353 and 354 and applied to the inputs of shift register 355,
• the latched outputs of shift register 310 are logically combined by NAND gate 356, inverter 357, and NOR gate 358 and applied to the input of shift register 355, the inputs to shift register 355 being latched in the Q outputs by the clock pulse from the output of flipflop 310C.
• the Q outputs of shift register 355, and the highest Q output of shift register 310 are applied to transmission gates 360, 361, 362 and 363.
• NOR gate 340 which (when inverted) is used to operate transmission gate 342 and thereby affect the pulse frequency, is also used to operate transmission gate 369 and thereby affect the pulse length. If the system is neither in a regenerative braking mode nor in an armature current limit condition, transmission gate 369 will be closed, shorting out resistor 324. If in a current limit condition, or if in a regenerative braking mode, transmission gate 369 will open, placing resistor 324 in the timing circuit. This will increase the resistance and provide a longer pulse duration so that the field current is increased.
• FIG. 12 illustrates the gate pulse amplifiers which isolate the control circuits from the power circuits and which develop the actual pulses used to gate the SCR's on.
• Gate pulse amplifier 380 utilizes three transistors 381, 382 and 383 all of which are off when the input signal GAw. from the armature monostable 226 (FIG. 10) is low, allowing capacitor 384 to charge to supply voltage V S1 through resistor 384a. When the signal GA MA goes high, all three transistors turn on, allowing capacitor 384 to discharge through the primary of pulse transformer 385 and transistor 383, causing the secondary to apply a pulse across the gate and cathode of the main armature SCR MA and gate it into conduction.
• Gate pulse amplifier 390 utilizes two transistors 391 and 392 which are turned on by a high GA LA signal to allow capacitor 393 to discharge through transistor 392 and the primary of pulse transformer
• this figure illustrates the portion of the control logic used to generate the circuit breaker trip signal V CBT .
• This signal when high, is used in FIG. 2 to cause trip coil 36 to open contacts 35 and 37 and remove power from the armature 20 and field 21. Also, as explained in connection with FIG. 9, when the V CBT signal is high, it will prevent the V AO signal from being high and will thereby inhibit the armature pulsing circuitry of FIG. 10,
• the output of NAND gate 405 will be low (for normal operation), providing all of the inputs thereto are high. If any input is low, a high V CBT signal will be generated, A transient suppression filter 406 is provided at the output of gate 405 to prevent spurious generation of a high V CBT signal.
• the first condition monitored by this circuit utilizes the DR F , DR R , F and J signals, these signals being logically combined by NOR gate 407, inverter 408 and NAND gate 409, It has been found from vehicle operation that electrical transients can cause the main SCR, SCR MA , for the armature to be turned on when the accelerator switch 73 is open and the field is not connected.
• the output of gate 407 will be high if the field is not connected (the microswitch signals DR F and DR R will be both low) while inverter 408 will output a high if the accelerator switch is open. If the main SCR MA does happen to be gated into conduction, as soon as the armature current increases beyond the minimum reference value (set in FIG. 6) , signal will go high causing gate 409 to output a low to gate 405. Gate 405 will then output a high V CBT signal which will cause the circuit breaker to trip and disconnect the armature from the battery.
• a second condition monitored by NAND gate 405 is the logical combination of the A and B signals applied to NAND gate 410. Under normal circumstances only one of these signals will be high. If a malfunction causes both to occur simultaneously, a high V CBT signal will be generated,
• a third condition resulting in the generation of a high V CBT signal is a "misfire" of the main armature SCR MA , i.e., a failure of this SCR to commutate.
• misfire is sensed by monitoring the conduction state of SCR MA and generating a V AM signal in response thereto.
• the V AM signal is low if the SCR MA is conducting and high if it is not.
• NAND gate 411 is used herein to see if the SCR MA is conducting at a time when it should be off. If so, the gate 411 will output a low, a situation which will occur if all of its inputs are simultaneously high.
• FIG. 17 illustrates the time sequence of the conditions which affect gate 411.
• Each time flipflop 225 (FIG. 10) delivers a trigger pulse to the armature monostable 226, the monostable will pulse for a length of time determined by capacitor 227 and its associated resistors. During this time its Q output goes low to produce a low signal. The signal is delayed to form a low signal. The beginning of the pulse is used to gate on the main SCR MA while the end of the pulse is used to trigger the commutating monostable 240. The high Q output of monostable 240 is used to gate on the commutating SCR CA , and the output goes low during the pulse period.
• the and signals are all applied (FIGS. 7 and 17) to NAND gate 411.
• one or more of these signals will be low during the time from the beginning of the pulse of the armature monostable 226 until the end of the pulse of the commutating monostable 240, and thus NAND gate 411 cannot have a low output during such time.
• all three of the and signals will be high. As a consequence a "window" in time is provided, for the period that all three signals are high, in which to see if the main armature SCR MA is in conduction or not.
• the V AM misfire signal is combined in FIGS.
• misfire circuit is not to produce a misfire signal if the armature power current is below minimum reference level. If the current is below such level, the signal J will be high and will inhibit NOR gate 412 from outputting a high. If the power current is above minimum, the output of NOR gate 412 will depend upon whether the V AM misfire signal is high or low. If the main armature SCR MA is conducting, gate 412 will output a high to NAND gate 411, and vice versa.
• the main armature SCR MA will be gated on shortly after the beginning of the monostable 226 pulse and will be commutated during the pulse time of monostable 240.
• SCR MA will be off during the entire time of the window provided by the and signals.
• NOP armature misfire signal
• gate 412 With SCR MA off and the armature misfire signal V AM high, NOP, gate 412 will have a low output to maintain NAND gate 411 with a high output.
• the armature misfire signal V AM When the motor is operating at speeds above 1920 rpm and the SCR MA is in continuous conduction, the armature misfire signal V AM will be continuously low and the output of NOR gate 412 will be continuously high. However, such continuous high from gate 412 will not cause a Vp BT signal to be generated because, with the armature monostable 226 operating in retrigger mode, its output (the and signals) will be contin uously low and no time window is provided.
• armature monostable 226 is taken out of retrigger operation, e.g., by a U signal if operating above 1920 rpm or by being braked to below 1920 rpm and returned to power mode operation, a time window will again be provided to see if SCR MA has failed to commutate.
• the present misfire circuit has a particular advantage in that the length of time from the occurrence of the misfire, a.e., the time that SCR MA should have been commutated but was not, until NAND gate 411 goes low is quite short and independent of the length of the pulse of monostable 226, Thus, no matter how short or how long the pulse of monostable 226 is, a misfire condition can exist only for the portion of the fixed pulse length of the commutating monostable 240 that occurs after misfire and up to the end of the monostable 240 pulse. As soon as that pulse ends, goes high and NAND gate 411 can go low to cause generation of the V CBT signal. As a consequence, a misfire can be detected just as quickly when the SCR MA is being operated by short pulses from monostable 226 as when it is being operated by long pulses.
• the V CBT signal is also generated in the event of a misfire of the main field SCR MF by the use of NAND gate 413.
• NAND gate 413 In case there is a misfire of the main armature SCR MA , as just described, it is desirable to generate the V CBT signal immediately and gate 412 will do so by looking at the armature misfire signal V AM through the first time window occurring after SCR MA fails to commutate.
• a misfire of the main field SCR MA is not as critical a malfunction and the present system will operate so that if, during a cycle of operation, SCR MF should fail to commutate, it is allowed to remain in conduction for a next cycle of operation. If SCR MF is successfully commutated in that cycle, the system will continue in operation. However, if SCR MF still fails to commutate, the circuit breaker trip signal V CBT will be generated.
• the and signal from the Q outputs of the field monostables 320 and 332 are applied to NAND gate 413 to provide a time window, during each cycle of operation, from the end of the commutating monostable 332 pulse until the beginning of the next pulse of monostable 320, signals and being both high during such time.
• the signal is also used, to inhibit generation of a V CBT signal if the field current is below minimum reference value, being low at such time.
• the field misfire signal V FM (high if SCR MF is conducting and low if SCR MF has been commutated) is applied to NAND gate 413 through delay circuit 414 comprised of resistor 415, capacitor 416 and buffer
• capacitor 416 will charge and discharge through resistor 415. If the V FM signal is high for a sufficiently long time, capacitor 416 can charge to a voltage sufficient to cause buffer 417 to output a high to NAND gate 413.
• the values of capacitor 416 and resistor 415 are chosen to provide a time delay between V FM going high and the output of buffer 417 going high so that if SCR MF should fail to commutate and V FM remains high; the buffer will not go high until after the commutating portion of the next cycle of operation.
• the system will function primarily in either a power mode or a braking mode.
• the power mode is the mode of operation wherein the armature is connected to the battery by SCR MA and is driven by the battery. Power mode operations during acceleration, at demanded speed and during deceleration, are separately discussed below.
• the system functions in a braking mode when the direction of the field current remains the same and the direction of armature current is reversed so that the counter emf of the motor provides a braking torque.
• the operator can choose to operate in either a "deceleration” or a "plugging" form of braking. Assume that the operator has commanded a forward dirction and the vehicle is operating in a power mode and travelling in that direction. If the operator desires "deceleration", he merely lets up on the accelerator pedal. Assuming a sufficient release of the accelerator pedal so that the system is taken out of the power mode, the system will go into a braking mode and the vehicle will be slowed down to the speed commanded by the new accelerator pedal position.
• the system will then return to power mode operation in the same direction at the lower speed. If instead the operator desires "plugging", he operates the direction control lever to command a reverse direction. (The position of the accelerator pedal may be left the same, increased or decreased).
• the system is immediately taken out of the power mode and put into the braking mode to brake the speed of the vehicle.
• the speed has decreased to a low value, the direction of field current is reversed, the system is put back into a power mode and the speed of the vehicle in the reverse direction is brought up to the speed demanded by the setting of the accelerator pedal.
• the system When operating in either deceleration or plugging, the system will operate in a regenerative braking mode or in a resistive braking mode, depending upon the speed of the mehicle.
• the armature is connected to the battery by the regenerative braking SCR, SCR RB . If the motor speed is insufficient to charge the battery, the armature is shorted out by the resistive braking SCR, SCR., A "coasting" mode of operation is also described below wherein the vehicle is neither operating in a power mode nor a braking mode.
• switch 70 With the direction control lever 24 moved to command a direction, e.g., a forward direction, switch 70 will close (FIG. 3) causing voltage F OD to generate the forward command signal B, This signal goes to FIG. 8, and through NAND gates 171 and 174 to generate the FWD signal. This latter signal goes to FIG. 2, is amplified and used to energize the forward coil 39 to close the forward contacts 40 and 41 and connect the field 21 to the power circuit. Microswitch 46 closes and sends signal DR F back to FIG.
• a direction e.g., a forward direction
• shift register 310 will not yet have been clocked and all of its outputs will be high.
• the input to VCO 318 will also be high so that monostables 320 and 332 will begin pulsing. Battery current is thus supplied through SCR MF and the forward contacts 40 and 41 (FIG, 2) to the field.
• the field current rises above the minimum reference (e.g., 3 amperes) and signal E goes low (FIG. 6).
• the field current can continue to rise, but if it goes to the maximum reference level (e.g., 55 amperes) signal H goes high, and, in FIG. 9, will act on gate 185 to cause the field inhibit signal V FI to go high and shut off the field pulsing circuit so that the field current will be held below the maximum reference level.
• the operator may now command fo ⁇ ward movement by depressing foot pedal 25. Assume the pedal is depressed halfway and held in such position.
• the position of the accelerator pedal 25 will determine the level of signal V OD (FIG. 3) that is applied (FIG. 10) to VCO 222 and will thus determine the pulse rate of monostable 226 which is used to gate on the main SCR MA for armature 20.
• V OD level of signal
• the operator demand voltage V OD is used in FIG. 3 to generate frequency signal F DM whose frequency is proportional to the degree of depression of the accelerator pedal.
• This frequency signal F DM is compared in FIG. 4 to the frequency of signal F AM which is proportional to the actual motor speed.
• the acceleration signals ACC 1 , ACC 2 , ACC 3 and ACC 4 will be produced.
• these acceleration signals will artificially boost the input voltage to VCO 222 to increase the pulse frequency of monostable 226.
• the now low inverted acceleration signals and will close transmission gates 256, 257 and 258 to increase the pulse width of monostable 226.
• the acceleration signals will cause the armature current to be appreciably greater than that demanded in FIG. 10 by the operator demand signal V OD alone.
• Jerk capacitor 221 and resistor 220 allow the voltage applied to the input of VCO 222 to rise gradually so that the motor will accelerate smoothly.
• F AM1 and T 1 will De low and high, respectively, and the counter 304 (FIG. 11) will have minimum count.
• the depression of the accelerator pedal will cause the frequency of the T 1 signal to decrease and the count in counter 304 to increase.
• the count is clocked through shift register 310 and inverted to decrease the pulse rate of VCO 318 and the field monostable 320. This will reduce the field current, thereby weakening the field and reducing the counter emf of the motor to enable its speed to increase.
• the acceleration signals ACC 1 - ACC 4 are used to shorten the pulse width of monostable and provide further field weakening during acceleration.
• the actual speed of the motor is continuously monitored by speed pickup 65 and, as the speed increases, the frequency of the actual motor speed signal F AM (FIG. 4) will increase proportionately.
• the derivative F AM1 pulses are continuously compared with the reference frequencies from fixed frequency oscillator 125 and counter 126 so that the relationship of the actual motor speed to the fixed reference speed points of 120, 240, 480 and 1920 rpm is known at all times.
• the ⁇ signal is used in FIG. 11 to open transmission gate 344 so that resistor 315 is in series with resistor 314, to provide a boosting of the input to VCO 318 and thus boost the field current.
• the actual motor speed increases to 480 rpm signal will go low, causing transmission gate 344 to close and remove the boosting effect on the field.
• VCO 155 (FIG. 6) will set a maximum power current limit level F CLA which will allow the power current to rise to about 450 amperes.
• transmission gate 158 will close, raising the frequency of the F CLA signal so that the armature can operate with a maximum limit of about 600 amperes (the top rating of the motor).
• the W signal will cause gate 158 to open and thus reduce the F CLA . signal to normal.
• gate 156 will open (FIG. 6) so that the armature power current limit signal F CLA is controlled by the decreasing
• the increasing motor speed and derivative actual motor speed signal F SM1 will cause the count in counter 304 (FIG. 11) to increase.
• the increasing count of counter 304 will be clocked through shift register 310.
• the frequency of the pulsing of the field monostable 320 and the field strength will progressively decrease.
• the progressive loss of the acceleration signals ACC 4 - ACC 1 will cause the transmission gates 365-368 to open and thus remove the artificial field weakening effect desired during acceleration.
• shift register 310 When all acceleration signals ACC 1 -ACC 2 4ave been lost, shift register 310 will no longer be clocked and the count of counter 304 which was present when the last acceleration signal was lost will be latched (in inverted form) at the outputs of the shift register.
• the field strength is now set by the latched count. With the field monostable pulsing field strength now set in response to the latched inverted count of counter 304 and the armature monostable pulsing set by the operator demand signal V OD , the speed of the motor will stabilize according to the torque demand on the motor.
• motor speed is controlled in response to the operator demand by setting the on-off ratio of conduction of the main armature
• the motor will accelerate in a manner as described above until the motor speed reaches 1920 rpm.
• the speed comparison signal T goes low and opens gate 255 (FIG. 10), increasing the pulse width of the armature monostable 226 so that it operates in the retrigger mode with its Q and outputs continuously high and low, respectively.
• the main armature SCR MA will now remain on continuously to supply full battery power to the armature.
• the operator may increase motor speed by a further depression of the accelerator pedal. With the frequency of the T 1 signal decreased, the count in counter 304 will increase. If the newly demanded speed is sufficiently high to generate an ACC 1 acceleration signal, the higher 304 count will be clocked through shift register 310 and will cause the field to be weakened. The speed of the motor will thus increase and eventually stabilize at a higher speed.
• the operator may also increase motor speed by further depressing the accelerator pedal. Such depression will raise the V OD signal and increase the armature current. If the newly demanded speed is insufficient to generate an ACC 1 signal, the field strength will remain the same and the speed will stabilize in accordance with the same field strength and the increased armature current. If an ACC 1 signal had been generated in response to the newly demanded speed, the increased count in counter 304 will be clocked through shift register 310 to weaken the field.
• the excessive armature power signal also acts, as last described, to boost field strength.
• the K and T signals are applied to gate 260 so that transmission gate 263 is closed. Gate 263 puts resistor 229 into the circuit and shortens the duration of the existing monostable pulse so that commutation of the main CR MA is hastened. Otherwise, SCR MA tvould continue to conduct for the full normal length of such pulse.
• the K and T signals are applied to gate 202, and will cause the V AO signal from gate 208 to go low so that the armature monostable 226 (FIG. 10) will not be retriggered by flip-flop 225. When the armature current reduces to below the current level limit, the V AO signal will be restored and normal operation of the armature and field monostables will resume.
• the circuits controlling the peak acceleration and the rate of acceleration are independent of each other, thereby enabling the system to be customized so that one can be varied without affecting the other.
• the degree of acceleration will depend upon the amount of armature current flow and peak acceleration is thus a function of the maximum allowable armatre power current during acceleration. Since the maximum allowable power current is set by the current limit signal F CLA , the frequency of such signal can be set to whatever is desired by appropriate selection of the values of the external resistors of VCO 155 (FIG. 6).
• the rate of acceleration is a function of the rate of change of the voltage applied to VCO 222 (FIG. 10), and this rate of change is dependent upon the value of positive jerk capacitor 221, jerk resistor
• the acceleration rate may be customized for a particular application by changing the value of the jerk resistor 220.
• Current-limiting operation, by the F CLA signal and resultant signals K and K, is independent of the rate of acceleration.
• Signal K will go low when there is excessive armature power current, regardless of how slowly or how quickly such current has reached and exceeded the F CLA limit.
• the acceleration-rate control at the input of VCO 222 is independent of the current limit signal K. For given values of capacitor 221 and resistor 220, the rate of change of the input voltage to VCO 222 will be the same, regardless of the frequency of the F CLA signal, or if the armature power current is excessive or not.
• the operation at motor speeds above 1920 rpm is as follows.
• a U signal will be generated when the newly demanded speed is less than the actual motor speed.
• the U signal will open transmission gate 291 and take the armature monostable out of retrigger operation.
• the U signal goes low, allowing the armature monostable to go back into retrigger operation and maintain SCR MA in continuous conduction. If the operator lets up on the accelerator pedal sufficiently so that the difference between the newly demanded speed and the actual speed is sufficient to generate the ACC 00 signal, the system will be taken out of power mode and put into a braking mode, as described hereinafter.
• the ACC 1 acceleration signal will be generated. When it is, it will cause the pulse width of the field monostable to decrease the field strength. If below 1920 rpm, the armature monostable pulse frequency is boosted to provide more armature current to provide the necessary torque to drive the vehicle up the slope at near demanded speed. If above 1920 rpm, the reduced field and decreased speed causes more armature current so that the torque demand is met. In either event, the speed will stabilize at about the speed relative to demanded wherein the ACC 1 signal is produced.
• the speed will again stabilize if delivered and demanded torques are the same.
• the motor speed will increase to a point wherein the difference between actual and demanded speeds is such as to cause the deceleration signal ACC 00 to be generated. This will cause the motor to be put into a braking mode, and the resultant dynamic braking will slow the vehicle. The speed will stabilize at approximately the speed wherein the ACC 00 signal is produced.
• the actual motor speed will be somewhere within the range wherein the speed is neither slow enough to produce an ACC 1 signal nor fast enough to produce an ACC 00 signal.
• the accelerator pedal is held at a fixed position, the actual motor speed will Nary in accordance with the torque demand. However, the actual speed will be held within a range relative to the demanded speed, the low speed of the range being that wherein an ACC 1 signal is generated and the high speed of the range being that wherein the ACC 00 signal is generated.
• the width of the range is a matter of choice.
• the actual motor speed signal F AM1 is varying with the speed and the count in counter 304 is likewise varying (since the operator demand signal T 1 is constant). If the actual speed goes down, the count in counter 304 goes down. If desired, the count in counter 304 could be clocked by each T 1 delayed pulse (instead of being inhibited from clocking if there is no acceleration signal) so that such decrease in motor speed will result in a strengthening of the field and thereby increase the delivered torque to meet the increase in demanded torque. Likewise, if the motor speed increase above demanded, the count in counter 304 will increase, and the field will be weakened to reduce the delivered torque. Thus, small variations between actual and demanded speeds would produce changes in the field strength which would cause the speed to stabilize near the demanded speed. By so doing the sensitivity of the system can be increased.
• the operator can control the rate of acceleration by use of the accelerator pedal.
• a gradual depression of the pedal to its fully depressed position as the motor speed increases will result in a slow rate of acceleration.
• An initial full depression of the pedal will result in a maximum rate of acceleration to the demanded speed.
• the top speed reference oscillator 95 (FIG. 4) is used to limit the top speed of the motor to a predetermined desired speed which is below the maximum speed demandable by full depression of the accelerator pedal, but without affecting the control by the operator of the rate of acceleration.
• the components of oscillator 95 are selected so that its frequency of oscillation, F TSM will he the same as the frequency of the actual speed signal F AM when the motor speed is at the desired top speed limit.
• the F TSM and F AM signals are continuously compared by comparator 97. As long as the actual speed of the motor is less than the top speed limit, transmission gate 100 will allow the operator demand signal F DM to go to comparator 102 and counter 105, and transmission gate 101 will block the F TSM output of oscillator 95 from having any effect on the system. As a consequence, as long as the actual speed is below the top speed limit, the operator has full control of the rate of acceleration.
• the armature monostable 226 (FIG. 10) will be controlled as a function of the V OD signal corresponding to full pedal depression up to the base speed of the motor, after which monostable 226 goes into retrigger operation with continuous armature current, Ther field monostable 320 (FIG.
• comparator 97 (FIG. 4) causes the G and G signals to go high and low respectively.
• Transmission gates 100 and 101 open and close, respectively, to substitute the lower frequency top speed limit signal F TSM for the F DM . demand signal. With the F TSM signal applied to comparator 102, and with the actual speed being greater than the top limit speed, comparator 102 will cause the U signal to go high.
• F TSM top speed limit signal
• the U signal will take the armature monostable 226 out of retrigger operation and the G signal will reset counter 223 and hold it reset so that the armature monostable will be inhibited from being triggered. Accordingly, armature current will be cut off.
• the effect on the field in response to the actual speed going above the top limit speed is as follows.
• the F TSM signal is now applied to counter 105 in place of the F DM signal.
• the counter 105 will then have a count indicating that the actual speed has gone above the top speed limit and the acceleration signal ACC 1 will go low (if it was still high).
• the field strength will remain essentially constant and at a strength determined by the actual speed signal corresponding to the top speed limit, while armature current is allowed or inhibited depending on whether the actual speed falls below or increases above the top speed limit.
• Such self-regulation will maintain the level of power to the motor to stabilize the actual speed at the top speed limit.
• the inhibition of armature current may not be sufficient to cause the vehicle to slow. If such is the case, the actual speed may continue to increase.
• the count in counter 105 (FIG. 4) is based on a comparison of the top speed limit signal F TSM and the actual speed signal F AM when the actual speed is above the top speed limit, when the actual speed increases enough relative to the top speed limit, the count in counter 105 will become low enough to cause the ACC 00 signal to be generated so that the system is put into a braking mode to cause an affirmative slowing of the vehicle back down to the top speed limit.
• the motor is operating at a demanded speed substantially above 1920 rpm and the operator lets up on the pedal to a position demanding a speed substantially below 1920 rpm.
• the U signal (FIG. 4) is generated. Also, since the newly demanded speed is substantially below actual speed, signal ACC 00 will go high. In FIG. 9, the ACC 0 0 signal cause the V DEC signal to go high, which, in turn, causes the V AO and signals to go low and the signal to go high. With the V AO signal now low, the armature monostable 226 is inhibited from operating and the main armature SCR MA is prevented from being further gated into conduction. With SCR MA now off to disconnect the armature from the battery the power current will drop. When the power current decays to below the minimum reference level, set by signal F IAO (FIG. 6) the signal will go low. In FIG.
• this signal is logically combined with the now low signal to generate a high brake enable signal and start the braking oscillator F BRK into operation. Since the motor speed is above 1920 rpm, the braking oscillator pulses will pass through gate 269 and the regenerative braking SCR RB will be gated on to connect the armature to the battery for flow of charging current to the battery.
• the brake enable signal and T signals are combined by NAND gate 336 and cause the transmission gates 342 and 369 to close and open respectively, to apply supply voltage V S2 to the input of VCO 318 so that it will operate at maximum frequency and to increase the external resistance of the field monostable 320, both of which will cause the field monostable to operate so that maximum field strength can be provided.
• the charging of the negative jerk capacitor 317 at the input of VCO 318 will control the rate at which the field strength is raised.
• the inertia of the vehicle will continue to drive the armature in the same direction, causing the motor to act as a generator. With the motor speed being above 1920 rpm base speed, the increasing field will cause the motor to develop sufficient voltage thereacross so that the generated current will flow back to the battery through SCR RB to recharge the battery as the motor decelerates.
• the generated voltage (and brake current produced thereby) is a function of armature speed and field strength.
• the armature brake current is continuously monitored and the field is controlled so that the brake current is held at a desired level.
• the armature brake current will rise as the field is built up, and the frequency of the armature current signal F IA will decrease.
• the frequency of the F IA signal will decrease below the frequency of the brake current limit signal F CLB (FIG. 6) and the excessive brake current signal L will go low.
• the low L signal will cause the field inhibit signalV FI to go high, so that, in FIG.
• the operation of the field monostable will be inhibited and current to the field will be shut off.
• the field will decay and reduce the generated brake current.
• the L signal will again go high, causing the field to be energized. This action repeats continuously so that the field monostable will operate to maintain the field at a level wherein the armature brake current is maintained at the F CLB level.
• the control of the field monostable in response to the L signal will automatically set the field strength at the proper level for any speed so that the generated brake current is held at the F CLB limit.
• the generation of braking current produces a braking torque so that the vehicle decelerates.
• a the speed reduces, the L signal will cause the field monostable to go into and out of operation at a progressively high level of field strength so that the armature brake current remains at the F CLB level.
• the motor will be slowed to a speed wherein excessive field current will be required to generate armature brake current at the F CLB level.
• the signal which is generated in FIG. 6 in response to the presence of excessive field current, is used in FIG. 9 to cause the field inhibit signal V FI to go low so that the field monostable operates to hold the field strength at the level produced by maximum allowable field current (approximately 55 amperes).
• the generated voltage will now decrease and will drop to a level wherein it is insufficient to overcome the battery voltage and supply current thereto.
• the maximum allowable field current will determine the lowest speed at which the motor can be operated to recharge the battery.
• the "base speed” referred to herein is substantially near this lowest recharging speed.
• the motor speed will decrease to the base speed of 1920 rpm and the actual speed signals T and will go low and high respectively.
• the now high T signal applied to gate 269, will inhibit further braking pulses F BRK from passing through gate 269 so that a gate pulse will not be applied to the regenerative braking SCR RB .
• the 1920 rpm speed is below that required to produce sufficient emf to charge the battery, the potential on the cathode of SCR RB will have become more positive than on the anode and SCR RB will have ceased to conduct.
• the T pulse and signals are used, on FIG. 10, to clock on flip-flop 276 and trigger on the one-second monostable 277.
• the Q output of this monostable is applied to gate 271 so that the F BRK brake pulses now passing through gate 270 (since T is now low) will be prevented from passing through gate 271 and being used to gate on SCR B .
• the V M5 signal from the Q output of the one-second monostable is used in FIG. 9 to cause the field inhibit signal V F1 to go high and shut off the field for the one-second duration of the pulse from monostable 277.
• V M5 signal from monostable 277 is also used, in FIG. 11, to cause a rapid discharge of the negative jerk capacitor 317 during the one-second monostable pulse period, so that the field will not be abruptly increased as deceleration continues.
• signal V,,-. goes high and allows F BRK signals to pass through gate 271 so that the resistive braking SCR B is turned on to effectively short circuit the armature for resistive braking.
• Trans ⁇ mission gate 342 opens, so that VCO 318 will pulse at a frequency determined by the output from the R/2R network 311, i.e., at the relatively low level existing when deceleration began. Transmission gate 369 closes to reduce the pulse width of the field monostable 320.
• the armature brake current is continuously monitored and compared to the
• the resultant excessive brake current signal L again affects the V FI signal to allow or inhibit the operation of the field monostable 320 and thereby maintain the armature brake current at the F CLB limit.
• the armature brake current should be greater during resistive braking.
• the brake current limit VCO 165 is controlled so that the current limit signal F CLB is lower than when in regenerative braking, to allow more brake current during resistive braking.
• the maximum allowable brake current may be held to about 150 amperes, with the maximum allowable brake current limit being about 400 amperes during resistive braking.
• the V AO and signals again go high and the signal goes low.
• the now high signal shuts off the brake oscillator which produces F BRK .
• the resistive braking SCR B will remain in conduction, however, until it is commutated.
• the resistive braking SCR B must be commutated before the main armature SCR MA is turned back on. The re-establishment of the V AO signal is used to accomplish this, in FIG. 10, as follows.
• the motor slows to'the demanded speed.
• the U signal will go low.
• the coincidence of the low U signal and the next low signal from monostable 240 will set flip-flop 281 with a high Q output.
• Gate 284 now allows the V AO signal to restore the armature monostable 226 into operation.
• the first pulse therefrom will gate SCR LA on to connect the commutating capacitor across SCR B to back-bias it and cause it to commutate.
• the delayed signal GAw. from the armature monostable will then gate the main armature SCR MA into conduction.
• the same deceleration sequence will occur if the original motor speed had been less than 1920 rpm except that the regenerative braking operation involting SCR RB will not occur.
• the one-second monostable 277 (FIG. 10) will be triggered on at the beginning of deceleration, in order that the V M5 output therefrom will discharge the negative jerk capacitor 317 for smooth deceleration. However, if the motor speed is less than 1920 rpm except that the regenerative braking operation involting SCR RB will not occur.
• the one-second monostable 277 (FIG. 10) will be triggered on at the beginning of deceleration, in order that the V M5 output therefrom will discharge the negative jerk capacitor 317 for smooth deceleration. However, if the motor speed is less than
• the signal will be low, so that the one-second monostable will not operate, thereby allowing the system to go into immediate braking.
• the deceleration signals ACC 00 and U will disappear, putting the system back into the power mode. If the newly demanded speed is sufficiently higher than the actual speed so that one or more of the acceleration signals ACC 1 -ACC 4 are generated, the system will go into the acceleration mode as soon as it returns to the power mode.
• the operator can command deceleration by simply letting up on the accelerator pedal.
• the operator can control the degree of deceleration by the amount that he releases the pedal. For any given actual speed, the more the pedal is released, the greater will be the degree of deceleration.
• the magnitude of the difference between these two signals is ascertained by counter 105 and is applied through shift register 117 to the digital-to-analog resistor network 118.
• the lower the demanded speed is, relative to the actual speed, the lower the count in counter 105 and the lower the voltage output of signal V CLB . Since this signal is inputted into VCO 165 (FIG. 6) the frequency of the brake current limit signal F CLB is a function of the count in counter 105.
• the operator if he wishes, can release the accelerator pedal all the waywhile moving in one direction. This produces a minimum F CLB signal and maximum braking. While decelerating, the operator can depress the pedal to a position still calling for a reduced speed. This will raise the frequency of the F CLB signal which will reduce the level of brake current and decrease the braking torque. As in the acceleration mode, the present system provides for independent control of the peak deceleration and the rate of deceleration.
• peak deceleration is a function of the brake current limit signal F CLB generated by VCO 165 (FIG. 6).
• the armature brake current is maintained at the F CLB limit generated by VCO 165 (FIG. 6).
• the degree of braking torque and deceleration will depend on the level of the F CLB signal.
• the rate of deceleration is a function of the rate of rise of the voltage applied to VCO 318 (FIG. 11) for the field monostable, i.e., the rate at which the field is built up to produce brake current and braking torque. This rate of change is dependent upon the values of the negative jerk capacitor 317 and the negative jerk resistor 316.
• the frequency of the F CLB signal is completely independent of the deceleration rate. Current-limiting will occur when the brake current reaches the F CLB , limit regardless of how quickly or how slowly the brake current rises to that limit. Contrarily, the rate of rise of the brake current is independent of the maximum allowable brake current.
• the degree of deceleration can be customized for a particular application by changing the values of the external resistors of VCO 165, Likewise, the rate of deceleration can be customized by changing the value of the negative jerk resistor 316.
• the peak acceleration and acceleration rate are independent of the peak deceleration and deceleration rate. Peak acceleration and peak deceleration are functions of maximum power and maximum plug currents through the armature.
• the current limit signals F CLA and F CLB come into effect at opposite ends of the F IA curve and thus there is no interaction between the F CLB and F CLB signals.
• the acceleration rate is a function of the rate of change of the input voltage to VCO 222 for the armature monostable
• the deceleration rate is a function of the rate of change of the input voltage to VCO 318 for the field monostable. Varying the rate of change of input to the VCO for the armature monostable will not affect the rate of change of the input to the VCO for the field monostable, and vice versa.
• gate 182 will output a low, so that gate 184 will continue to output a high field-enabling signal V FE to maintain the field pulsing circuitry of FIG. 11 in operation.
• gates 192 and 193 will both output a high to gate 194 so that the signal will go low.
• the plugging signal V PG goes high.
• the low signal is applied to gate 207, and, by gate 208 causes the V AO signal to go low and inhibit the armature pulsing circuitry of FIG. 10.
• the high V PG signal is applied to gates 197 and 200 so that signals and go low and high respectively.
• control signals V AO and are affected by the plugging signal V PG in the same way as they are by the deceleration signal V DEC .
• the now high V PG signal is used in FIG. 4 to close transmission gate 196 and ground the brake current limit signal V CLB .
• This in turn (FIG. 6) causes VCO 165 to operate at its lowest frequency.
• the brake current limit signal F CLB is not affected by accelerator pedal position as previously described but is instead set for maximum braking effect.
• the F CLB signal may permit up to 450 amperes during regenerative braking and up to the maximum Tating of the motor, e.g., 600 amperes, during resistive braking,
• the V PG signal is used, instead of the difference between actual and demanded s.peeds, to affect the brake current limit signal F CLB , the motor will be braked in the same manner as previously described.
• SCR RB will be gated on for regenerative braking, and the will boost the pulse frequency and pulse width of the field monostable as before.
• Field strength will be maintained, by the L and V FI signals, at a level to hold the brake current at the F CLB limit. The only difference is that deceleration will be greater since more brake current is allowed to flow through the armature.
• the motor will go out of regenerative braking in the same manner. Again as it does so, the boosting of the pulse frequency and pulse width of the field monostable 320 by the signal will terminate and the monostable will pulse at the lower frequency set by the output of the R/2R network 311.
• the L and V FI signals will allow or inhibit operation of the field monostable to maintain the armature brake current at the F CLB limit.
• the motor will decelerate so that its speed drops below the lowest speed reference, 120 rpm. At such time the D and motor signals will go high and low, respectively.
• each of gates 180-183 is now low (i.e., for gate 180, B for gate 181 and D for gates 182 and 183), causing each gate to output a high to gate 184 so that the field enable signal V FE goes low.
• the field inhibit signal V FI goes and stays high to inhibit operation of the field monostable 320 (FIG. 11). With the field cut off, the field current will begin to decay.
• the forward contacts 40 and 41 will remain closed, since signal C and are both high, and will, in FIG. 8, cause gate 170 to maintain the FWD signal.
• gates 192, 193 and 194 cause the plugging signal V PG and to revert to their non-plugging low and high states, respectively. Signals and also revert to their non-braking high and low states, respectively.
• the D RR signal together with the A and signals, will cause gate 180 to reinstitute the field enable signal V FE which causes the field pulsing circuitry to begin functioning again to rebuild the field.
• the low E signal will act on gat 204 and cause the armatureon signal V AO to be generated.
• flip-flop 281 will have been reset when the direction-control lever was shifted through neutral from forward to reverse.
• transmission gate 241 closes and the commutating monostable 240 is triggered by an V AD pulse so that SCR LA is gated on to charge the commutating capacitor C CA .
• Flip-flop 281 then sets so that the V AO signal will now enable the main armature monostable 226 to be triggered.
• the first pulse gates on SCR LA to connect the charged commutating capacitor across SCR B to commutate it and then gates on the main armature SCR MA .
• the system is now in the power mode and the motor speed is then brought, in the reverse direction, up to the speed demanded by the operator in the manner as previously described.
• Coasting Mode This mode is one in which the vehicle is moving and is neither in the power nor braking mode.
• the coasting mode will hot normally be used, but it is available to the operator in case he wishes it.
• gates 192 and 193 will both output a high so that gate 194 outputs a low.
• the plugging signal V PG will go high, braking signal goes low and signal goes high, as if a plugging mode were being commanded. However, very little braking will occur since the field has been cut off.
• the field current will decay. When it drops to the minimum reference level, signal will go low. In FIG, 8, this will result in a loss of the FWD signal, the forward relay contacts 40 and 41 will now open, to disconnect the field, and the motor will now coast with no power applied to either the field or the armature. Again, the contacts 40 and 41 will not open until the field current has dropped below the minimum reference level and arcing at the contacts is thus prevented.
• the last commanded direction signal C will remain high as long as the motor speed remains above 120 rpm.
• the primary control of the motor is achieved by using the Vo ⁇ . (and derivative signals) signal proportional to the demanded speed and the F AM signal (and derivative signals) proportional to the actual speed of the motor and using such signals so that the actual speed is brought to the demanded speed.
• the demanded speed signals are independent of the load on the vehicle. They are dependent only upon the degree of depression of the accelerator pedal. For a given pedal position, the V OD , F DM and T 1 signals will be set, regardless of whether the vehicle is loaded or empty or whether it is going up or downhill.
• the actual speed signals are independent of the load on the vehicle. For any given actual speed, the frequency of the F AM signal will be the same, whether the vehicle is loaded or not.
• the operator can control the speed of the motor, and of the vehicle propelled thereby, in a very positive manner. If he wishes to travel at a certain speed, he sets the accelerator pedal to demand that speed. The speed of the vehicle will then stabilize at or near that speed (within the dead-band range between ACC 00 and ACC 1 signals) whether the vehicle is loaded or empty or whether the vehicle goes up or down slopes. This is true whether the motor is accelerating or decelerating to the demanded speed.
• the armature current is also continually monitored. In the event of excessive armature current, either power or brake current, the system operates to regulate the operation of the field so that the excessive current is reduced to allowable limits. Such feedback of armature current information is not used, however, to control the speed of the motor -- it is used to keep armature current within allowable limits as the motor changes speed during acceleration or deceleration to reach a demanded speed.
• the present system also enables the operator to continue to control the speed of the motor after full power is applied to the armature. It is customary to regulate speed of a motor by using an SCR control to vary the amount of average power supplied to the armature from the battery. Full speed in such systems is obtained by bypassing the SCR control and connecting the motor directly across the battery. When this occurs the operator has no further control over the motor except to take it out of the bypass mode and return to SCR control.
• armature current can be increased by the main SCR MA up to a point (1920 rpm) wherein the SCR MA is in continuous conduction and the armature is essentially connected across the battery (save fo ⁇ the relatively small voltage drop through the conducting SCR).
• the operator still has direct control of the motor speed above that point by virtue of the field control obtained in response to further pedal depression.
• the present system also utilizes a digital, rather than analog, control.
• the signals are either generated directly as frequency signals or else the underlying variable voltage signal is converted to a corresponding frequency signal.
• the actual speed of the motor is indicated by the frequency signal
• F DM and T 1 The magnitude of armature and field current is indicated by the frequency signals F IA and F IF . These signals are compared in frequency with each other or with the frequency signals generated by the various oscillators in the control, such as the current reference signals F CLA , F IAO , F CLB , F IFMAX , and F IFMIN , or the speed reference signals from VCO 119 (FIG. 4), VCO 125 (FIG. 5) and oscillator 94 (FIG. 4).
• the current reference signals F CLA , F IAO , F CLB , F IFMAX , and F IFMIN or the speed reference signals from VCO 119 (FIG. 4), VCO 125 (FIG. 5) and oscillator 94 (FIG. 4).
• FIG. 18 discloses a modification of the field pulsing circuit.
• the end results of a system using the FIG. 18 circuit are essentially the same as if the previously described circuit of FIG. 11 is used. That is, during power operation, the excitation of the field, is controlled as an inverse function of the demanded and actual speeds so that the field current is high at low demanded and actual speeds and low at high demanded and actual speeds.
• the field is controlled by regulating the field current so that the armature brake current is held at the maximum allowable brake current limit set by the brake current limit signal
• both circuits function in the same manner during braking.
• the field monostable 320 is operated at a pulse rate and pulse width such that if the monostable was allowed to operate continuously the generated armature current would be excessive.
• the armature current signal F IA is continuously compared to the brake current limit signal F CLB , and tne resultant
• L signal is used to allow the field monostable to operate as long as the armature brake current is not excessive and to inhibit operation during such time as the armature brake current is excessive. By so doing, the field strength is regulated to maintain the armature brake current at the F CLB limit.
• FIGS. 11 and 18 differ primarily in the manner in which the field current is regulated during the power mode of operation.
• the field monostable operates continuously, with the field strength being regulated by varying the pulse frequency and pulse width as an inverse function of the count in counter 304.
• the field monostable 320 operates at a fixed pulse frequency and pulse width sufficient to produce maximum field strength if the monostable were to operate continuously.
• Field current is then regulated by allowing or inhibiting operation of the monostable so as to maintain the field current at a desired level, namely at a level which varies as an inverse function of the count in counter 304.
• the maximum allowable field current signal F I FMAX is varied as an inverse function of the count in counter 304.
• the actual field current is continuously monitored and the resultant actual field current signal F IF is continuously compared to the field current limit signal F IFMAX .
• the comparison signal H (high if the field current is less than the current limit and low if the field current exceeds the current limit) is then used to allow or inhibit operation of the field monostable and thereby maintain the field current at the
• operation of the field pulsing circuit of FIG. 18 is of the same character during braking and power modes of operation.
• the L signal is used to allow or inhibit operation of the field monostable to maintain armature brake current at the F CLB level.
• the II signal is used to allow or inhibit operation of the field monostable to maintain field current at the F IFMAX level.
• the field monostable 320 is triggered by the pulses from flip-flop 319 which is clocked by the output of
• VCO 318 In this case, the input of VCO 318 is connected by resistor 430 to the supply voltage V S2 so that VCO 318 oscillates at a fixed frequency.
• the pulse width of monostable 320 is normally a function of capacitor 321 and resistor 322, resistor 324 being shorted out by transmission gate 369 which is closed except when in a regenerative mode or if excessive armature power current is present.
• the pulse frequency and pulse width of the field monostable 320 are such that the field current will exceed the maximum allowable limit (e.g., about 55 amperes) if the monostable 320 were to operate continuously.
• the T. and F AM1 pulses are applied to counter 304 so that a count is continuously obtained of the number of cycles of actual speed signals F AM1 per cycle of the demanded speed signal T 1 .
• This count is applied to shift registers 310 and 355 and clocked therethrough by the Q output of flip-flop 310c in the same manner as previously described in connection with FIG. 11.
• the outputs of shift register 310 are applied to the R/2R digital-to-analog resistor network 311 to produce an output voltage which varies inversely with the count in counter 304. As before, this output is sent to FIG. 6 as the V CLA signal to set the frequency of the armature power current limit signal F CLA .
• the analog output of the R/2R network 311 is also applied to the voltage dividing network of series resistors 431, 432, 433, and 434, the latter being connected to ground.
• Transmission gates 436, 437 and 438 are connected across resistors 431, 432 and 433, respectively, to short out these resistors when the gates are closed.
• the values of the resistors in the voltage dividing network are chosen so that the V CLA utput of the R/2R network 311 is not unduly loaded as resistors 431, 432 and 433 are selectively shorted out.
• VCO 143 produces a frequency signal V I FMAX which varies in frequency according to the level of the V IFMAX signal, the F IFMAX signal and the actual field current signal F IF being applied to comparator 141. If the level of field current is below the F IFMAX limit set by VCO 143, the comparison signal H will be high. If the field current exceeds such limit the H signal will go low.
• the H signal is used in the logic circuit of FIG. 9 to cause the field inhibit signal V FI to go low if the field current is excessive and the H signal is low. Also, as before, when the field inhibit signal V FI goes low, the VCO 318 and flip-flop 319 are inhibited so that the field monostable 320 is not triggered. When the field current reduces below the maximum limit, the H and V FI signals go high, so that the field monostable can resume operation and pulse at its fixed frequency and pulse width. The H signal thus causes the field current to be maintained at whatever the F IFMAX level may be.
• the system operates in an acceleration mode as follows. Assume that the actual and demanded speeds are both quite low. The count in counter 304 will be low and the output of the R/2R network 311 will be high. Gates 436 and 437 will both be closed, shorting out resistors 431 and 432. V IFMAX will be a proportion (as determined by the values of resistors 433 and 434) of the R/2R output . If the accelerator pedal is depressed, the count in counter 304 will increase and the R/2R output will decrease so that the level of the V I FMAX signal applied to VCO 143 is decreased proportionally. The F IFMAX signal is accordingly decreased in frequency so that a lesser amount of field current can flow.
• the H signal regulates the operation of the field monostable 320 so that the field current is reduced and maintained at this new F IFMAX level. If the demanded acceleration is sufficiently high, the ACC 4 signal will close gate 438 so that the V IFMAX signal is taken directly from the output of the R/2R network 311. This will serve to allow more field current and more torque on initial acceleration. When the actual motor speed increases to a point where the
• the count in counter 304 will progressively increase and the R/2R output will progressively decrease so that the V IFMAX level will decrease and provide field weakening.
• the count in counter 304 will increase, as the motor speed increases, to a point wherein the count is sufficient to open transmission gate 437, With resistor 432 now in series with resistor 433, the level of signal V IFMAX will drop. A further increase in speed will cause gate 436 to open, putting resistor 431 in the circuit so that the proportion of the R/2R voltage appearing at VCO T43 is further reduced.
• Capacitor 443, connected between the input of VCO 143 and ground enables the voltage level of V IFMAX to change smoothly as resistors 431, 432 and 433 are shorted out or cut back into the circuit.
• the signal will go high to close transmission gate 444 and boost the level of the V IFMAX signal. This in turn raises the frequency of the V IFMAX signal to allow the field strength to build up and thereby reduce the armature current.
• the operation of the circuit of FIG. 18 in deceleration is as follows. Assume that the motor is operating above 1920 rpm and the operator releases the acceleration pedal to demand a speed substantially below 1920. As before the demanded deceleration will generate a signal, and the V AO signal will go low to shut off the armature monostable (FIG, 10). When the armature power current decays below minimum reference, the signal goes loxv and the brake enables signal goes high. The regenerative braking SCR, SCR RB , is gated on to connect the armature to the battery.
• the high and signals cause the output of NAND gate 447 to go low. This low causes gate 369 to open and put resistor 324 in series with resistor 322 to lengthen the pulses of field monostable 320.
• the low output of gate 447 is inverted by inverter 448 to close gate 451 and apply supply voltage V S2 to the input of VCO 143, to raise the field current limit signal F IFMAX to its maximum.
• the rate of deceleration may be customized for a particular application by changing tfie value of the negative jerk resistor 441.
• the armature With maximum field now allowed to be applied, the armature will generate braking current to recharge the battery. As before, the armature brake current is continuously monitored and the L signal is used to control the state of the field inhibit signal V F1 and thereby allow the field monostable 320 to pulse or to be inhibited from operating so that the armature brake current is maintained at its maximum allowable limit (set by the F CLB signal).
• Vwr signal will close gate 453 so that the negative jerk capacitor 443 may discharge through resistor 454 and ground the input of VCO 143,
• SCR B will be gated on to short across the armature for resistive braking.
• the field inhibit signal V FI goes high to allow the field monostable 320 to begin pulsing again.
• Gate 453 will open, allowing capacitor 443 to charge and raise the frequency of the F IFMAX signal, with the rate of rise being governed by the charge time of the negative jerk capacitor 443.
• the excessive armature brake current signal L is again used to control the field inhibit signal V FI to regulate the field strength at a level which maintains the armature brake current at the F CLB current limit.
• the field monostable 320 is triggered at a lower rate during such time to provide smoother operation. This is accomplished by combining the and signals by NAND gate 456. These signals will all be high when braking, when the speed decreases below 1920 rpm and after the one-second delay of monostable 277.
• the output of NAND gate 456 will go low, the output of inverter 457 will be high and close transmission gate 458 to connect resistor 459 and capacitor 460 in series with resistor 430.
• the voltage input to VCO 318 will rise from ground p potential, at a rate determined by the values of resistor 430 and capacitor 460, to a reduced level determined by the values of voltage dividing resistors 430 and 459.
• FIG. 18 field control circuit When the system is in a plugging form of braking, the FIG. 18 field control circuit will operate to regulate the armature brake current during regenerative and resistive braking in the same manner as just described.

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• Engineering & Computer Science (AREA)
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• Physics & Mathematics (AREA)
• Thermal Sciences (AREA)
• Mechanical Engineering (AREA)
• General Engineering & Computer Science (AREA)
• Control Of Direct Current Motors (AREA)
• Heat-Exchange Devices With Radiators And Conduit Assemblies (AREA)

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• 1979
  • 1979-01-15 DE DE792934898A patent/DE2934898A1/de active Granted
  • 1979-01-15 WO PCT/US1979/000017 patent/WO1980001526A1/en unknown
• 1980
  • 1980-01-14 IT IT19195/80A patent/IT1129676B/it active
  • 1980-07-29 EP EP79901037A patent/EP0022774A1/de not_active Withdrawn
• 1984
  • 1984-08-29 SG SG60184A patent/SG60184G/en unknown

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