EP0020980B1 - Dispositif d'affichage par segments - Google Patents

Dispositif d'affichage par segments Download PDF

Info

Publication number
EP0020980B1
EP0020980B1 EP80102574A EP80102574A EP0020980B1 EP 0020980 B1 EP0020980 B1 EP 0020980B1 EP 80102574 A EP80102574 A EP 80102574A EP 80102574 A EP80102574 A EP 80102574A EP 0020980 B1 EP0020980 B1 EP 0020980B1
Authority
EP
European Patent Office
Prior art keywords
stroke
segment
display system
segments
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP80102574A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP0020980A2 (fr
EP0020980A3 (en
Inventor
Robert Howard Lantz
Alfred Alexander Schwartz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP0020980A2 publication Critical patent/EP0020980A2/fr
Publication of EP0020980A3 publication Critical patent/EP0020980A3/fr
Application granted granted Critical
Publication of EP0020980B1 publication Critical patent/EP0020980B1/fr
Expired legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/06—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows
    • G09G1/08—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam directly tracing characters, the information to be displayed controlling the deflection and the intensity as a function of time in two spatial co-ordinates, e.g. according to a cartesian co-ordinate system
    • G09G1/10—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam directly tracing characters, the information to be displayed controlling the deflection and the intensity as a function of time in two spatial co-ordinates, e.g. according to a cartesian co-ordinate system the deflection signals being produced by essentially digital means, e.g. incrementally

Definitions

  • the present invention relates to circuits relating to display devices in which symbols or alpha-numerical configurations are defined by means of a series of segments. More particularly, the present invention essentially relates to a technique making it possible to reduce the size of the memory required to define groups of segments corresponding to the different elements that comprise any assortment of alpha-numeric characters.
  • a conventional display system which uses the use of segments is described in US Pat. No. 3,540,032.
  • a main deflection coil is used to direct the beam towards a point on the surface. of a cathode ray tube (CRT) where it is desired to form a character, point from which a character deflection coil is used to move the beam so as to trace successive segments, the video circuits being in turn turned on and off, appropriately, to obtain the desired character, symbol, number, etc.
  • CTR cathode ray tube
  • the data necessary for the generation of all the characters, numbers, etc. that the system is capable of displaying are stored in a register.
  • US-A-4,054,951 describes a technique applicable to long data sets which are repeated periodically.
  • the space available in memory is saved by omitting the integral repetitions of such sets in the data suite.
  • the sets thus omitted are inserted by means of devices capable of recognizing the presence of a particular flag among the data in memory.
  • the next element of information contained in the data series is then interpreted as constituting the address in memory of the start of a data set which must be inserted in this data series.
  • the next item of information is interpreted as representing the length of the data set to be inserted, and the next item of information indicates the number of insertions of this data set.
  • This technique therefore makes it possible to obtain the address of the data to be inserted, an address which must then be accessed from another part of the memory.
  • segment memory the bits defining the segments
  • this technique requires the allocation of a particular “flag” code, which, in the case of the segment display method described above, would require the allocation of one of only sixteen possible bit configurations. , assuming the use of four bits per segment.
  • the present invention as characterized in claims 1 and 6 therefore provides a technique for compressing the data relating to the segments with a view to their storage and for expanding this data for the purposes of their use by the display device, and which makes it possible to obtain a reduction in the dimensions of the segment memory.
  • This technique is based on the fact that when an elementary segment or increment is traced in one of, for example, eight possible directions, it is never necessary that the following segment has an opposite orientation and presents the same video state (applicable or deletion of the beam) than the segment which precedes it.
  • the segments are here the subject of a special transposition and coding so that, when the segment consecutive to that which is being traced has relative to the latter an opposite orientation and an identical video state, the display device is informed that it must automatically take certain predetermined measures instead of displaying said consecutive segment.
  • the preferred embodiment described below is a device in which the recognition of the fact that the segment consecutive to the current segment has a reverse orientation and the same video state, automatically causes the tracing of two additional segments identical to the segment current. There is therefore no need, when using the present technique, to provide a particular coded configuration intended to act as a flag and which cannot be used as a segment. It suffices that it is observed that a segment presents with respect to that immediately preceding it an opposite orientation and the same video state for the circuit to automatically supply a series of additional segments.
  • the circuit described below is intended to be used with a display device on cathode-ray tube by means of a directed beam, which device makes it possible to trace segments of characters or symbols, each segment being defined by four bits, to know three bits that specify its orientation and one bit that governs the application or removal of the beam.
  • the segments are stored at the rate of nine segments per word, so that each word can contain a maximum of thirty-six bits divided into groups of four.
  • the present invention takes advantage of the fact that it is never necessary for a given segment to be followed by another segment having the same video state and an orientation which differs by 180 ° with respect to that of the first segment. Since these reverse segments are unnecessary for the purpose of character representation, they are used in the present invention to indicate the presence of several segments having the same orientation as the first segment and preceding one or more reverse segments.
  • the reverse segments are not transmitted to the deflection device.
  • a reverse segment is equivalent to two additional segments of the same type as the segment immediately preceding the first reverse segment, but the number of additional segments could possibly differ from two and any other type of automatic operation could possibly be triggered as soon as the detection of a reverse segment having the same video state.
  • Figure 1 shows the logic elements of the preferred embodiment of the invention.
  • the first four bits of the word are transferred via a multiplexer 12 to a four-bit register 13, hereinafter called register A.
  • register A the register of the word
  • the remaining thirty-two bits are loaded into a shift register 10.
  • the register 10 and register A are both loaded, or their content is shifted, by means of a pulse designated SC which is generated by an inverted OR circuit 14. This loading or this shift is caused by negative transitions which occur in the SC pulse train. Normally, this pulse train is an inversion of the clock pulse train which is applied to circuit 14.
  • FIG. 2 shows that, at clock time 0, a series of segments represented by the characters M, N, P, Q, R, S and T are stored in the floors SR1 to SR8 of the shift register, as well as in registers A and B.
  • each of the segments M, N, P, etc. of Figure 2 represents a group of four bits of binary data .
  • Three of the four bits in each group represent one of the eight possible orientations of the beam, while the fourth bit represents the video state of the beam (the application or removal thereof).
  • register A contains a single segment represented by N in Figure 2. This same register does not contain the series of segments necessary to generate the character N.
  • comparison circuit A the comparison circuit 16 hereinafter called comparison circuit A, is connected so as to receive on one of its two inputs the four bits contained in the first stage of the shift register 10 and defining a segment, and on its other input the four bits contained in register A and defining another segment.
  • the comparison circuit A therefore acts as a forecasting device which makes it possible to detect the appearance of an inverse segment in the first stage of the shift register 10, that is to say a segment which has the same video state as that of the segment contained in register A and an opposite orientation. In this case, the comparison circuit A transmits on its output line 22 a high level signal.
  • a comparison circuit 17, hereinafter called comparison circuit B makes it possible to compare the content of register A with that of register B and transmits a high level signal on its output line 23 if it detects the presence in register A of a segment which is the reverse of that contained in register B.
  • the appearance of this signal on line 23 results in the obtaining of a low level signal at the output of an inverter 18, this latter signal having the effect of prohibiting the transfer by the AND gate 9 of the segment contained in register A to register B.
  • the registers A and B as well as the eight stages of the shift register 10 constitute a sequential routing circuit (or “pipeline”) of the data relating to the segments, which circuit is interposed between the memory of segments and the deflection device that comprises the cathode ray tube.
  • the segment stored in register B is available to the deflection device.
  • a segment M is in the register B, a segment N in the register A, a segment P in the stage SR1 of the deca register lage, and a segment P of opposite orientation in the stage SR2 of this register. Since neither of the comparison circuits generates a high level signal at the first clock instant, the content of each of the elements of the sequential routing circuit is shifted and transferred to the element following of this circuit.
  • a segment N is in the register B and is available to the deflection device.
  • the segment P is in the register A and the segment P reverses in the stage SR1 of the shift register.
  • This high level is applied via the OR gate 28 to the CLR (restore) and J inputs of the JK 21 flip-flop.
  • the positive transition from the clock pulse train toggles the flip-flop 21 and provides a level SRB signal on line 14 high.
  • the flip-flop 21 switches again for a short time interval, then is restored at the start of the fourth clock instant due to the fact that the signal present on the line 23 is at the high level and remains at this level until segment offset has ended.
  • this high level signal disappears, at the instant when the output signal of the comparison circuit B goes to the low level, the input CLR of the flip-flop 21 no longer receives a positive input and this flip-flop is restored .
  • the different codes contained in the stages of the shift register 10 and in the registers A and B are subject to a shift.
  • the flip-flop 21 remains restored and none of the comparison circuits A and B provides a high level output signal.
  • the comparison circuit A detects the presence in the first stage of the shift register 10 of a segment whose orientation is the opposite of that of the segment contained in the register A.
  • the codes are shifted in the register 10 and in the registers A and B.
  • the flip-flop 21 switches and provides a high level signal on line 24 so as to prevent any shift at the start of the eighth clock instant.
  • the comparison circuit B detects the presence in the register A of a segment whose orientation is the opposite of that of the segment contained in the register B and generates on line 23 a signal of high level which has the effect of restoring the flip-flop 21 at the start of the eighth instant of the clock.
  • the segment S is available to the deflection circuit, as well as during the eighth clock instant.
  • the segment S which is thus available during the eighth clock instant is the first of the two segments S which are automatically generated in response to the detection of the inverse segment S which immediately follows the segment S in the series of segments initially stored.
  • the flip-flop 21 Since the flip-flop 21 is now restored, at the beginning of the ninth clock instant the segments are shifted in register 10 and in register A. However, since the comparison circuit B has continued to generate a high level signal during eighth clock instant, the reverse segment S is not transferred by shift from register A to register B. During this ninth clock instant, the second of the two segments S automatically generated is available to the deflection circuit. However, comparison circuit B continues to generate a high level output during this time interval due to the fact that the second inverse segment has now been transferred by shift to register A. At the ninth clock instant, the flip-flop 21 is engaged due to the fact that the high level signal continues to be generated on line 23 by the comparison circuit B.
  • the codes are not subject to any shift in register 10 and in register A. Due to the presence on line 23 of the high level signal generated by the comparison circuit B, the inverse segment S is not transferred by shift from register A to register B.
  • the second of the two automatically generated segments S is made available to the deflection circuit due to the presence of the first inverse segment S immediately consecutive to the segment S in the series of segments initially stored.
  • the first of two segments S which are automatically generated again is made available to the deflection circuit. This second pair of segments S is automatically generated due to the second inverse segment S which was present in the series of segments which had been stored.
  • a segment S is made available to the deflection circuit.
  • the flip-flop 21 is again restored.
  • the content of the shift register 10 and that of the register A are shifted, so that the register A now contains a new segment.
  • the inverse segment S which was previously in the register A is not transferred to the register B because of the high level signal generated by the comparison circuit B which was present on the line 23 at the beginning of this clock instant.
  • the second segment of the second pair of automatically generated segments S is available to the deflection circuit.
  • the flip-flop 21 is activated for a short period of time and then restored in the same way as it had been at the beginning of the fourth clock instant.
  • the flip-flop 21 is activated for a short period of time and then restored in the same way as it had been at the beginning of the fourth clock instant.
  • another shift in the content of all the registers occurs and the last segment forming part of the stored sequence is available to the deflection circuit.
  • the comparison circuit A triggers an automatic operation in response to the detection of a series of reverse segments, while the comparison circuit B maintains this automatic operation.
  • This may result in a restriction in the preferred embodiment of the invention. Indeed, since the last segment of a word composed of nine segments is introduced into register B when loading a new word, it is not possible to detect the presence of reverse segments during the passage of one word to another, and the series of segments stored in the memory of segments for each character or symbol that one wishes to display must comply with this restriction. However, the latter can easily be avoided by using a third comparison circuit connected so as to be able to determine whether the first segment of the next word contained in the segment memory and which must be transferred to the decompression logic is an inverse segment of the segment. contained in register A.
  • FIG. 4 shows schematically the part of a typical device for displaying character segments with which the present invention can be advantageously used, said part relating to the deviation of the characters.
  • each of the codes representing the alpha-numeric symbols which it is desired to display is transferred from a regeneration memory to a consultation memory 30 by the through a line 29.
  • the memory 30 can be produced, for example, in the form of an unalterable memory comprising tables so as to be able to supply a starting address to the address counter 31 which addresses the memory of segments 32 so that it provides as many nine-segment words as necessary to draw a character or an alpha-numeric symbol corresponding to each of the codes accessed in the regeneration memory.
  • the nine-segment words from the segment memory 32 are applied to the decompression logic 33 which constitutes the essence of the present invention shown in Figures 1 to 3.
  • the output of the latter logic consists of a signal which is transmitted on line 25 and which controls the application or suppression of the video beam, and a three-bit signal which is transmitted on line 26 and which controls the orientation of a segment. These last two signals are applied to both the original decoder 34 and the segment decoder 40.
  • the decoder 34 decodes the first segment of each character or alpha-numeric symbol so as to control the accumulators x and y 41 and 43 in order to direct the beam towards the correct starting position for the tracing of the character or of the particular alpha-numeric symbol which it is about. All the following segments are applied to the decoder 40 in order to increment and decrement the accumulators 41 and 43 and according to the data relating to the segments, so that the beam moves correctly to form the character or the alpha-numeric symbol.
  • the signal transmitted on line 25 controls the application or suppression of the beam in an appropriate manner.
  • the increment or decrement values x and y of the accumulators 41 and 43 are respectively applied to the digital / analog converters 42 and 44, whose output signals respectively transmitted on lines 50 and 51 are applied to the deflection coils of so as to ensure correct and precise positioning of the cathode beam.
  • the invention therefore makes it possible to reduce the amount of memory required to specify groups of sequences of segments corresponding to any of the characters or symbols of a chosen alpha-numeric assortment.
  • the logic circuits make it possible to determine the presence of a segment whose video state (application or suppression of the beam) is the same as that of the segment which immediately precedes it and whose orientation is the reverse of that of the latter, so as to cause in such a case the generation of a predetermined number of additional segments identical to the previous segment, instead of using the reverse segment to return the beam to the position it occupied immediately before the tracing of the previous segment. Thanks to this technique, there is no need to assign a particular code acting as flag to cause this automatic operation, which flag could not also be used as a segment. It will also be noted that the use of two additional segments generated in response to the detection of a reverse segment constitutes only an example used for the purposes of the description of the present invention and does not constitute a limitation, said detection possibly being used to trigger any other type of automatic operation.

Landscapes

  • Engineering & Computer Science (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
EP80102574A 1979-06-25 1980-05-09 Dispositif d'affichage par segments Expired EP0020980B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/052,054 US4237458A (en) 1979-06-25 1979-06-25 Stroke expansion apparatus
US52054 1979-06-25

Publications (3)

Publication Number Publication Date
EP0020980A2 EP0020980A2 (fr) 1981-01-07
EP0020980A3 EP0020980A3 (en) 1982-03-17
EP0020980B1 true EP0020980B1 (fr) 1985-04-03

Family

ID=21975140

Family Applications (1)

Application Number Title Priority Date Filing Date
EP80102574A Expired EP0020980B1 (fr) 1979-06-25 1980-05-09 Dispositif d'affichage par segments

Country Status (5)

Country Link
US (1) US4237458A (enrdf_load_stackoverflow)
EP (1) EP0020980B1 (enrdf_load_stackoverflow)
JP (1) JPS5638092A (enrdf_load_stackoverflow)
CA (1) CA1135427A (enrdf_load_stackoverflow)
DE (1) DE3070411D1 (enrdf_load_stackoverflow)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4434420A (en) 1982-06-21 1984-02-28 Motorola, Inc. Interline spacing adjustment circuit in a scanning CRT visual display system
JPS6041193U (ja) * 1983-08-29 1985-03-23 鈴木　允 型押し装置
JPS60114155A (ja) * 1983-11-22 1985-06-20 Daikei:Kk 米飯加工食品の自動製造機における食材供給方法
US4724432A (en) * 1985-08-15 1988-02-09 Sperry Marine Inc. Generation of graphic symbols for cathode ray tube displays
JPS6471451A (en) * 1987-09-12 1989-03-16 Fuji Seiki Kk Apparatus for forming rice ball

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3402395A (en) * 1965-02-15 1968-09-17 Bunker Ramo Data compression and display system
US3459926A (en) * 1965-10-18 1969-08-05 Ibm Graphic vector generator
US3540032A (en) * 1968-01-12 1970-11-10 Ibm Display system using cathode ray tube deflection yoke non-linearity to obtain curved strokes
FR2044615A5 (enrdf_load_stackoverflow) * 1970-03-05 1971-02-19 Philips Ind Commerciale
US4054951A (en) * 1976-06-30 1977-10-18 International Business Machines Corporation Data expansion apparatus

Also Published As

Publication number Publication date
DE3070411D1 (en) 1985-05-09
EP0020980A2 (fr) 1981-01-07
JPS623955B2 (enrdf_load_stackoverflow) 1987-01-28
JPS5638092A (en) 1981-04-13
EP0020980A3 (en) 1982-03-17
CA1135427A (en) 1982-11-09
US4237458A (en) 1980-12-02

Similar Documents

Publication Publication Date Title
EP0825542B1 (fr) Méthode pour synchroniser la présentation de composantes statiques et dynamiques d'un document multimédia interactif
EP0142439B1 (fr) Procédé de compression d'une succession d'informations numériques, et dispositif mettant en oeuvre ce procédé
FR2554256A1 (fr) Appareil et procede de regeneration d'un tampon de trames fonctionnant a grande vitesse
FR2657741A1 (fr) Interface de restructuration de trames pour trains numeriques multiplexes par multiplexage temporel d'affluents numeriques a differents debits.
FR2465281A1 (fr) Dispositif de transmission numerique et d'affichage de graphismes et/ou de caracteres sur un ecran
FR2522490A1 (fr) Appareil pour diagnostic par ultrasons
EP0026699B1 (fr) Procédé et dispositif de codage de données binaires, dispositif de décodage des données codées et système de transmission comportant de tels dispositifs
EP0682828B1 (fr) Procede d'entrelacement et de desentrelacement en bloc et dispositif de mise en oeuvre
EP0416985A1 (fr) Procédé de multiplexage d'un signal sonore avec un signal vidéo analogique et système correspondant de distribution d'images fixes sonorisées
EP0020980B1 (fr) Dispositif d'affichage par segments
EP0466554B1 (fr) Procédé de traitement d'un signal vidéo
FR2646540A1 (fr) Dispositif perfectionne d'effacement rapide de l'afficheur de sortie d'un systeme informatique
EP0151077A2 (fr) Circuit d'adressage d'un imageur matriciel comportant des registres à décalage formés de mémoires statiques et procédé d'adressage avec un tel circuit
FR2491651A1 (fr) Ensemble a memoire pour le transfert de donnees vers un dispositif de visualisation a tube a rayon cathodique
EP0476592A2 (fr) Générateur d'adresses pour la mémoire de données d'un processeur
EP0083998B1 (fr) Générateur d'octets chiffrants ou déchiffrants
EP3423978B1 (fr) Procede de d'affichage d'une animation lors de la phase de demarrage d'un dispositif electronique et dispositif electronique associe
EP0054490A1 (fr) Procédé et dispositif pour permettre l'échange d'information entre des systèmes de traitement d'information à vitesses de traitement différentes
FR2619461A1 (fr) Procede et circuit de compression video pour affichage sous forme de carte de bits
EP0635786A1 (fr) Dispositif de stockage de données
EP0056207A1 (fr) Procédé et dispositif pour la visualisation de messages transmis par un signal du type télévision, sur un dispositif d'affichage à trame balayée tel qu'écran d'un tube à rayons cathodiques, ledit message comportant des éléments répétitifs
EP0145046A2 (fr) Procédé pour engendrer des objets dans une image vidéo
FR2626131A1 (fr) Procede et dispositif de permutation de lignes de television par bloc
EP0391784B1 (fr) Dispositif et procédé de génération de signaux de contrôle
EP0021942A1 (fr) Procédé et dispositif de remise en phase d'une horloge locale

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Designated state(s): DE FR GB

17P Request for examination filed

Effective date: 19810828

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Designated state(s): DE FR GB

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Designated state(s): DE FR GB

REF Corresponds to:

Ref document number: 3070411

Country of ref document: DE

Date of ref document: 19850509

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 19900404

Year of fee payment: 11

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 19900424

Year of fee payment: 11

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 19900529

Year of fee payment: 11

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Effective date: 19910509

GBPC Gb: european patent ceased through non-payment of renewal fee
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Effective date: 19920131

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Effective date: 19920303

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST