EP0020980B1 - Segmented-display device - Google Patents

Description

Technical area

The present invention relates to circuits relating to display devices in which symbols or alpha-numerical configurations are defined by means of a series of segments. More particularly, the present invention essentially relates to a technique making it possible to reduce the size of the memory required to define groups of segments corresponding to the different elements that comprise any assortment of alpha-numeric characters.

State of the prior art

A conventional display system which uses the use of segments is described in US Pat. No. 3,540,032. In this latter patent, a main deflection coil is used to direct the beam towards a point on the surface. of a cathode ray tube (CRT) where it is desired to form a character, point from which a character deflection coil is used to move the beam so as to trace successive segments, the video circuits being in turn turned on and off, appropriately, to obtain the desired character, symbol, number, etc. The data necessary for the generation of all the characters, numbers, etc. that the system is capable of displaying are stored in a register.

Before tracing each character on the screen, a starting position is defined, then a series of information is defined defining successive modifications of position, and each of these is accompanied by additional information relating to the application or to the suppression of the cathode beam. Reference may also be made to document US-A-3,459,926 which describes a generator of short elementary segments, of the same amplitude intended to allow the tracing of a long segment of variable amplitude. Although many variants are possible, it has been found that there is interest in defining each elementary segment by means of four bits, three of which make it possible to define one of eight directions separated from each other by 45 °, the fourth bit used to determine the application or the suppression of the cathode beam. It is obvious that if each elementary segment is short enough for a sufficiently detailed representation of characters such as e, a and s to be obtained, a large number of segments is essential to form characters such as L, E, and 'F. If the assortment of alpha-numeric characters is large, a large memory becomes necessary.

Since the capacity of a memory generally only increases in discrete increments, a relatively small decrease (expressed as a percentage) in the number of memory bits corresponding to all the segments which constitute the different elements of a given assortment of characters can allow a relatively significant saving (also expressed as a percentage) with regard to the dimensions of the memory since it is not necessary to increase its capacity by an increment in order to be able to store all the required bits for a selected assortment of alpha-numeric characters and symbols.

It is therefore obvious that it would be advantageous to use a data compression technique to minimize the dimensions of the memory required to store the segments constituting the alpha-numeric characters or the symbols which it is desired to display. Many documents deal with the problem of data compression in specific cases. An example is the article published in the IBM Technical Disclosure Bulletin Vol. 15 N ° 9 of February 1973, page 2966. To draw a continuous curve, it is proposed to group in pairs the eight types of segments defining the eight possible directions, which saves a few bits. But there is a more general problem related to the four-bit coding technique described above. If we study the sequences of segments constituting characters or symbols, we see that, in many cases, we use uninterrupted sequences of identical segments. If we use the coding technique described above, which calls for the use of four bits per segment, we see that a considerable number of bits are used without reason to define a series of identical segments.

US-A-4,054,951 describes a technique applicable to long data sets which are repeated periodically. In this technique, the space available in memory is saved by omitting the integral repetitions of such sets in the data suite. When data must be extracted from the memory, the sets thus omitted are inserted by means of devices capable of recognizing the presence of a particular flag among the data in memory. The next element of information contained in the data series is then interpreted as constituting the address in memory of the start of a data set which must be inserted in this data series. The next item of information is interpreted as representing the length of the data set to be inserted, and the next item of information indicates the number of insertions of this data set. This technique therefore makes it possible to obtain the address of the data to be inserted, an address which must then be accessed from another part of the memory. In the case of a high-speed display device, it would be extremely expensive, if not impossible, to manage the data relating to the segments in this way, it being understood that the detection of a flag would require access to another part of the memory containing the bits defining the segments (called segment memory) for the purpose of retrieving the information relating to these. Furthermore, this technique requires the allocation of a particular “flag” code, which, in the case of the segment display method described above, would require the allocation of one of only sixteen possible bit configurations. , assuming the use of four bits per segment. Finally, if we take into account the need to use a flag and three additional bytes of data (address, length and number of repetitions), it is obvious that this technique of the prior art would not necessarily result in a significant reduction in the number of bits corresponding to the segments which constitute a set of alpha-numeric characters to be displayed.

Data compression using the so-called stroke length coding technique can be used for this purpose. Document US-A-3,755,805 describes such a technique. In this case, a few bits (usually two) are added to each segment to indicate the number of segments that are to be drawn in the specified direction. Depending on the parameters of the system, it is thus possible to obtain a certain reduction in the dimensions of the segment memory. However, this type of coding can lead to data expansion when the races are not long enough and, if implemented, substantial penalties in the absence of consecutive identical segments.

It would therefore be advantageous to use a data compression and expansion technique which can be applied to elementary segments, which does not cause data expansion during the storage of the segments, and which makes it possible to obtain more greater compression than in the case of the stroke length coding technique.

Statement of the invention

The present invention as characterized in claims 1 and 6 therefore provides a technique for compressing the data relating to the segments with a view to their storage and for expanding this data for the purposes of their use by the display device, and which makes it possible to obtain a reduction in the dimensions of the segment memory. This technique is based on the fact that when an elementary segment or increment is traced in one of, for example, eight possible directions, it is never necessary that the following segment has an opposite orientation and presents the same video state (applicable or deletion of the beam) than the segment which precedes it. On the contrary, the segments are here the subject of a special transposition and coding so that, when the segment consecutive to that which is being traced has relative to the latter an opposite orientation and an identical video state, the display device is informed that it must automatically take certain predetermined measures instead of displaying said consecutive segment. By way of example, the preferred embodiment described below is a device in which the recognition of the fact that the segment consecutive to the current segment has a reverse orientation and the same video state, automatically causes the tracing of two additional segments identical to the segment current. There is therefore no need, when using the present technique, to provide a particular coded configuration intended to act as a flag and which cannot be used as a segment. It suffices that it is observed that a segment presents with respect to that immediately preceding it an opposite orientation and the same video state for the circuit to automatically supply a series of additional segments.

Other objects, characteristics and advantages of the present invention will emerge more clearly from the following description, made with reference to the drawings appended to this text, which represent a preferred embodiment thereof.

Brief description of the figures

• Figure 1 schematically shows the preferred embodiment of the segment decompression logic of the present invention.
• Figure 2 schematically shows the flow of data relating to the segments at different clock times.
• Figure 3 is a timing diagram showing the state of several logic devices in the circuit of Figure 1 during the flow of data used in the example in Figure 2.
• FIG. 4 schematically represents a part of a typical device for displaying characters constituted by segments with which the present invention can be advantageously used, said part of the device being devoted to the deviation of the characters.

Description of an embodiment of the invention

The circuit described below is intended to be used with a display device on cathode-ray tube by means of a directed beam, which device makes it possible to trace segments of characters or symbols, each segment being defined by four bits, to know three bits that specify its orientation and one bit that governs the application or removal of the beam. The segments are stored at the rate of nine segments per word, so that each word can contain a maximum of thirty-six bits divided into groups of four. These figures are given by way of example only and could possibly be modified, the present invention being able to be used in a wide range of devices.

In this example, you can use as many words as you need to form a character, but a character must necessarily start with a new word and a particular segment is used to indicate the end of the character. This last segment is essential, even if it requires the use of an additional word. The first four bits of a character are not interpreted as a segment, but contain initial positioning information.

The present invention takes advantage of the fact that it is never necessary for a given segment to be followed by another segment having the same video state and an orientation which differs by 180 ° with respect to that of the first segment. Since these reverse segments are unnecessary for the purpose of character representation, they are used in the present invention to indicate the presence of several segments having the same orientation as the first segment and preceding one or more reverse segments. The reverse segments are not transmitted to the deflection device. In the preferred embodiment, a reverse segment is equivalent to two additional segments of the same type as the segment immediately preceding the first reverse segment, but the number of additional segments could possibly differ from two and any other type of automatic operation could possibly be triggered as soon as the detection of a reverse segment having the same video state.

Figure 1 shows the logic elements of the preferred embodiment of the invention. In order to facilitate understanding of the operation of the circuit shown in Figure 1, reference will also be made to Figures 2 and 3. In Figure 1, during the transfer of each thirty-six bit word from the segment memory to the decompression circuit , the first four bits of the word are transferred via a multiplexer 12 to a four-bit register 13, hereinafter called register A. The remaining thirty-two bits are loaded into a shift register 10. The register 10 and register A are both loaded, or their content is shifted, by means of a pulse designated SC which is generated by an inverted OR circuit 14. This loading or this shift is caused by negative transitions which occur in the SC pulse train. Normally, this pulse train is an inversion of the clock pulse train which is applied to circuit 14. However, as will be seen in detail below, the presence of a high level SRB signal emanating from of a flip-flop 21 and which is applied to the circuit 14 via a line 24, has the effect of prohibiting any transition in the train of pulses SC, so that these pulses are maintained at a level low as long as the SRB signal is high.

We will now refer to Figure 2, which shows that, at clock time 0, a series of segments represented by the characters M, N, P, Q, R, S and T are stored in the floors SR1 to SR8 of the shift register, as well as in registers A and B. It is particularly important to note that each of the segments M, N, P, etc. of Figure 2 represents a group of four bits of binary data . Three of the four bits in each group represent one of the eight possible orientations of the beam, while the fourth bit represents the video state of the beam (the application or removal thereof). For example, register A contains a single segment represented by N in Figure 2. This same register does not contain the series of segments necessary to generate the character N. The arrow pointing to the left which is above some of the characters in Figure 2 which represent segments indicates that the segment in question is a reverse segment having the same video state as the segment which precedes it and which is not surmounted by an arrow. The orientation of the arrows in Figure 2 in no way corresponds to the direction in which the beam moves when tracing a segment.

Reference will again be made to FIG. 1, on which the comparison circuit 16, hereinafter called comparison circuit A, is connected so as to receive on one of its two inputs the four bits contained in the first stage of the shift register 10 and defining a segment, and on its other input the four bits contained in register A and defining another segment. The comparison circuit A therefore acts as a forecasting device which makes it possible to detect the appearance of an inverse segment in the first stage of the shift register 10, that is to say a segment which has the same video state as that of the segment contained in register A and an opposite orientation. In this case, the comparison circuit A transmits on its output line 22 a high level signal.

The codes stored in register A can be shifted and transferred to register B via the AND gate 9. A comparison circuit 17, hereinafter called comparison circuit B, makes it possible to compare the content of register A with that of register B and transmits a high level signal on its output line 23 if it detects the presence in register A of a segment which is the reverse of that contained in register B. The appearance of this signal on line 23 results in the obtaining of a low level signal at the output of an inverter 18, this latter signal having the effect of prohibiting the transfer by the AND gate 9 of the segment contained in register A to register B.

As can be seen by referring to FIGS. 1 and 2, the registers A and B as well as the eight stages of the shift register 10 constitute a sequential routing circuit (or “pipeline”) of the data relating to the segments, which circuit is interposed between the memory of segments and the deflection device that comprises the cathode ray tube. At each clock instant, the segment stored in register B is available to the deflection device. Thus, in Figure 2, at clock time 0, a segment M is in the register B, a segment N in the register A, a segment P in the stage SR1 of the deca register lage, and a segment P of opposite orientation in the stage SR2 of this register. Since neither of the comparison circuits generates a high level signal at the first clock instant, the content of each of the elements of the sequential routing circuit is shifted and transferred to the element following of this circuit.

Therefore, at the first clock instant, a segment N is in the register B and is available to the deflection device. The segment P is in the register A and the segment P reverses in the stage SR1 of the shift register. It will also be noted with reference to FIG. 3 that after the first clock instant the output of the comparison circuit A goes high on line 22. This high level is applied via the OR gate 28 to the CLR (restore) and J inputs of the JK 21 flip-flop. At the second clock instant, the positive transition from the clock pulse train toggles the flip-flop 21 and provides a level SRB signal on line 14 high.

At this second clock instant, the segments contained in the different stages of the sequential routing circuit are shifted again. The segment P is now available to the deflection device in register B and the reverse segment P is now in register A. The output of comparison circuit A goes low and that of comparison circuit B goes to high level on line 23 because the segment which is now in register A is the opposite than that in register B.

At the third clock instant, no code shift occurs since the signal SC is at the low level, the signal SRB applied via the line 24 to the input of the circuit 14 being at the high level. The flip-flop 21 is then restored due to the fact that there was on line 23, at the start of this third clock instant, a high level signal emanating from the comparison circuit B. During this same clock instant , another segment P is found in register B, available to the deflection circuit. This is the first of two segments that must be automatically generated due to the fact that the current P segment immediately precedes a reverse orientation segment with the same video state. As will be understood by those skilled in the art, any other type of automatic operation resulting from the detection of an inverse segment and having the same video state as the segment which precedes it could possibly be envisaged.

Since the output of the flip-flop 21 present on line 24 has been reduced to a low level at the beginning of the third clock instant, the codes are shifted in register 10 and in register A at the beginning of the fourth instant d clock, as shown in Figure 2. However, since the output of comparison circuit B was still at a high level at the beginning of this fourth clock instant, AND gate 9 did not transmit the content from register A to register B. Therefore, register B still contains the segment P during the fourth clock instant. The segment P is therefore at the disposal of the deflection circuit for three clock instants and this third segment P is the second of the two segments P which are automatically generated. It will also be noted that the inverse segment P has been replaced by the segment Q transferred by offset from the first stage of the shift register 10 to the register A.

It will be noted that the flip-flop 21 switches again for a short time interval, then is restored at the start of the fourth clock instant due to the fact that the signal present on the line 23 is at the high level and remains at this level until segment offset has ended. When this high level signal disappears, at the instant when the output signal of the comparison circuit B goes to the low level, the input CLR of the flip-flop 21 no longer receives a positive input and this flip-flop is restored .

At the beginning of the fifth clock instant, the different codes contained in the stages of the shift register 10 and in the registers A and B are subject to a shift. The flip-flop 21 remains restored and none of the comparison circuits A and B provides a high level output signal.

At the sixth clock instant, the comparison circuit A detects the presence in the first stage of the shift register 10 of a segment whose orientation is the opposite of that of the segment contained in the register A. As in the example relating to the segment P and the inverse segment P, at the beginning of the seventh clock instant, the codes are shifted in the register 10 and in the registers A and B. The flip-flop 21 switches and provides a high level signal on line 24 so as to prevent any shift at the start of the eighth clock instant. During the seventh clock instant, the comparison circuit B detects the presence in the register A of a segment whose orientation is the opposite of that of the segment contained in the register B and generates on line 23 a signal of high level which has the effect of restoring the flip-flop 21 at the start of the eighth instant of the clock. During the seventh clock instant, the segment S is available to the deflection circuit, as well as during the eighth clock instant. The segment S which is thus available during the eighth clock instant is the first of the two segments S which are automatically generated in response to the detection of the inverse segment S which immediately follows the segment S in the series of segments initially stored.

Since the flip-flop 21 is now restored, at the beginning of the ninth clock instant the segments are shifted in register 10 and in register A. However, since the comparison circuit B has continued to generate a high level signal during eighth clock instant, the reverse segment S is not transferred by shift from register A to register B. During this ninth clock instant, the second of the two segments S automatically generated is available to the deflection circuit. However, comparison circuit B continues to generate a high level output during this time interval due to the fact that the second inverse segment has now been transferred by shift to register A. At the ninth clock instant, the flip-flop 21 is engaged due to the fact that the high level signal continues to be generated on line 23 by the comparison circuit B. Thus, at the tenth time of the clock, the codes are not subject to any shift in register 10 and in register A. Due to the presence on line 23 of the high level signal generated by the comparison circuit B, the inverse segment S is not transferred by shift from register A to register B.

During the ninth clock instant, the second of the two automatically generated segments S is made available to the deflection circuit due to the presence of the first inverse segment S immediately consecutive to the segment S in the series of segments initially stored. During the tenth clock instant, the first of two segments S which are automatically generated again is made available to the deflection circuit. This second pair of segments S is automatically generated due to the second inverse segment S which was present in the series of segments which had been stored.

During the tenth clock instant, a segment S is made available to the deflection circuit. At the beginning of this clock instant, the flip-flop 21 is again restored. Thus, at the eleventh clock instant, the content of the shift register 10 and that of the register A are shifted, so that the register A now contains a new segment. The inverse segment S which was previously in the register A is not transferred to the register B because of the high level signal generated by the comparison circuit B which was present on the line 23 at the beginning of this clock instant. During the latter, the second segment of the second pair of automatically generated segments S is available to the deflection circuit. At the beginning of the eleventh clock instant the flip-flop 21 is activated for a short period of time and then restored in the same way as it had been at the beginning of the fourth clock instant. At the twelfth clock instant, another shift in the content of all the registers occurs and the last segment forming part of the stored sequence is available to the deflection circuit.

As previously mentioned, nine segments at a time are loaded into the shift register 10 and into the register A of Figure 1. As shown in Figure 2, for these nine segments, twelve segments have been put available to the deflection circuit in this example. It is therefore obvious that, in this example, compressing and decompressing the data stored in the manner just described makes it possible to achieve a saving of 25% as regards the dimensions of the memory.

It emerges from the above that the comparison circuit A triggers an automatic operation in response to the detection of a series of reverse segments, while the comparison circuit B maintains this automatic operation. This may result in a restriction in the preferred embodiment of the invention. Indeed, since the last segment of a word composed of nine segments is introduced into register B when loading a new word, it is not possible to detect the presence of reverse segments during the passage of one word to another, and the series of segments stored in the memory of segments for each character or symbol that one wishes to display must comply with this restriction. However, the latter can easily be avoided by using a third comparison circuit connected so as to be able to determine whether the first segment of the next word contained in the segment memory and which must be transferred to the decompression logic is an inverse segment of the segment. contained in register A.

FIG. 4 shows schematically the part of a typical device for displaying character segments with which the present invention can be advantageously used, said part relating to the deviation of the characters. During each regeneration cycle of the display obtained on the screen of the cathode-ray tube, each of the codes representing the alpha-numeric symbols which it is desired to display is transferred from a regeneration memory to a consultation memory 30 by the through a line 29. The memory 30 can be produced, for example, in the form of an unalterable memory comprising tables so as to be able to supply a starting address to the address counter 31 which addresses the memory of segments 32 so that it provides as many nine-segment words as necessary to draw a character or an alpha-numeric symbol corresponding to each of the codes accessed in the regeneration memory. The nine-segment words from the segment memory 32 are applied to the decompression logic 33 which constitutes the essence of the present invention shown in Figures 1 to 3. The output of the latter logic consists of a signal which is transmitted on line 25 and which controls the application or suppression of the video beam, and a three-bit signal which is transmitted on line 26 and which controls the orientation of a segment. These last two signals are applied to both the original decoder 34 and the segment decoder 40.

The decoder 34 decodes the first segment of each character or alpha-numeric symbol so as to control the accumulators x and y 41 and 43 in order to direct the beam towards the correct starting position for the tracing of the character or of the particular alpha-numeric symbol which it is about. All the following segments are applied to the decoder 40 in order to increment and decrement the accumulators 41 and 43 and according to the data relating to the segments, so that the beam moves correctly to form the character or the alpha-numeric symbol. At each segment, the signal transmitted on line 25 controls the application or suppression of the beam in an appropriate manner. The increment or decrement values x and y of the accumulators 41 and 43 are respectively applied to the digital / analog converters 42 and 44, whose output signals respectively transmitted on lines 50 and 51 are applied to the deflection coils of so as to ensure correct and precise positioning of the cathode beam.

Figure 4 is given only for reference, it being understood that it is the decompression logic described above and shown in detail in Figures 1 to 3 which constitutes the essence of the present invention.

The invention therefore makes it possible to reduce the amount of memory required to specify groups of sequences of segments corresponding to any of the characters or symbols of a chosen alpha-numeric assortment. The logic circuits make it possible to determine the presence of a segment whose video state (application or suppression of the beam) is the same as that of the segment which immediately precedes it and whose orientation is the reverse of that of the latter, so as to cause in such a case the generation of a predetermined number of additional segments identical to the previous segment, instead of using the reverse segment to return the beam to the position it occupied immediately before the tracing of the previous segment. Thanks to this technique, there is no need to assign a particular code acting as flag to cause this automatic operation, which flag could not also be used as a segment. It will also be noted that the use of two additional segments generated in response to the detection of a reverse segment constitutes only an example used for the purposes of the description of the present invention and does not constitute a limitation, said detection possibly being used to trigger any other type of automatic operation.

Although the essential characteristics of the invention applied to a preferred embodiment of the invention have been described in the foregoing and represented in the drawings, it is obvious that a person skilled in the art can provide all of them. modifications of form or detail which he judges useful, without departing from the scope of said invention.

Claims (10)

1. A segmented display system in which a sequence of strokes defines individual symbols, characterized in that it includes :

detection means (10, 13, 16) for generating a signal upon detection of a first stroke that immediately precedes a second stroke of opposite direction and of the same video state as said first stroke ; and

means (9, 15) responsive to said first signal for automatically initiating a new operating cycle of the display system.

2. A segmented display system according to claim 1, characterized in that said detecting means comprise look ahead means (16) for generating said signal before said second stroke has been executed by said display system.

3. A segmented display system according to claim 2, characterized in that it further includes means (9) which, in response to said signal, inhibit the execution of said second stroke.

4. A segmented display system according to claim 3, characterized in that said means for automatically initiating a new operation cycle of the display system further comprise means (27, 28) for generating a predetermined number of strokes identical with said first stroke an immediately following said first stroke.

5. A segmented display system according to claim 4, characterized in that said predetermined number is two.

6. A segmented display system of the type wherein a sequence of strokes defines individual symbols, characterized in that it includes :

first storage means (10) for storing strokes ;

second storage means (13) for storing at least one stroke ;

means (14) for loading a first stroke of said sequence of strokes into said second storage means and the remaining strokes of said sequence of strokes into said first storage means ;

means (16) for comparing the direction and video state of said first stroke stored in said second storage means with a second stroke stored in said first storage means ;

means (16) for generating a signal (22) upon detection by said comparison means that said first stroke and second stroke are of opposite direction and of the same video state ; and means (17, 18, 23, 9) which, in response to said signal, automatically initiate a new operating cycle of the display system and inhibit the execution of said second stroke.

7. A segmented display system according to claim 6, characterized in that it further includes a third storage means (15) to which said first stroke is transferred, and wherein said means which, in response to said signal, inhibit the execution of said second stroke, include means (9) for inhibiting the transfer of said second stroke to said third storage means.

8. A segmented display system according to claim 7, characterized in that said means which, in response to said signal, inhibit the execution of said second stroke, include second comparison means (17) for comparing the direction and video state of said first stroke and said second stroke stored in said third storage means and said second storage means, respectively.

9. A segmented display system according to claim 8, characterized in that said first storage means (10) comprise a multiple-stage shift register.

10. A segmented display system according to claim 9, characterized in that said second storage means (13) comprise a single-stage shift register.

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