EP0015342A1 - Substrat-Vorspannungsregler - Google Patents

Substrat-Vorspannungsregler Download PDF

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Publication number
EP0015342A1
EP0015342A1 EP79302875A EP79302875A EP0015342A1 EP 0015342 A1 EP0015342 A1 EP 0015342A1 EP 79302875 A EP79302875 A EP 79302875A EP 79302875 A EP79302875 A EP 79302875A EP 0015342 A1 EP0015342 A1 EP 0015342A1
Authority
EP
European Patent Office
Prior art keywords
transistor
substrate
voltage
coupled
field effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP79302875A
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English (en)
French (fr)
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EP0015342B1 (de
Inventor
Jerry Dale Moench
Rodney Clair Tesch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
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Motorola Inc
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Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of EP0015342A1 publication Critical patent/EP0015342A1/de
Application granted granted Critical
Publication of EP0015342B1 publication Critical patent/EP0015342B1/de
Expired legal-status Critical Current

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/205—Substrate bias-voltage generators

Definitions

  • This invention relates, in general, to semiconductor substrate bias circuits, and more particularly, to a regulator to regulate substrate bias voltage generators.
  • RAM dynamic random access memories
  • nodes are charged to a given voltage. These nodes do not have a current source and must therefore be periodically, e.g. every 2 milliseconds, refreshed or recharged. These nodes are capacitively coupled to the semiconductor substrate and since much of the capacitance associated with these nodes is substrate capacitance, the voltage on the nodes will change approximately directly with substrate voltage changes.
  • Another object of the present invention is to provide a substrate bias regulator which is useful in minimizing the high output impedance effects of a substrate bias voltage generator.
  • Yet another object of the present invention is to provide a substrate bias voltage which varies percentage wise the same amount as the supply voltage varies.
  • a substrate bias regulator for controlling the output of an oscillator and a substrate bias voltage generator.
  • the regulator comprises a series of field effect transistors for producing an output bearing a relation to the substrate voltage.
  • One of the series of field effect transistors has its source electrode coupled to the substrate for sensing the voltage of the substrate.
  • This same field effect transistor or another one of the series of field effect transistors has its gate electrode coupled to a reference.
  • the series of field effect transistors produce an output which is coupled to an amplifier. The amplifier amplifies the output so that the output may be useful in controlling the output of the oscillator and the output of the substrate bias voltage generator.
  • FIG. 1 there is illustrated in block diagram form a system for generating a substrate bias voltage for substrate 10.
  • Substrate 10 would typically be a substrate for a semiconductor chip.
  • the circuitry for the semiconductor chip is formed upon substrate 10.
  • a variable output oscillator 12, such as a ring type oscillator, provides an output whose voltage varies in time thereby driving substrate bias voltage generator 13.
  • Oscillators and bias generators useful for oscillator 12 and generator 13 are well known in the art.
  • Bias generator 13 preferably generates a negative voltage which is coupled to substrate 10.
  • Bias generator 13 can be of the type which couples the output of oscillator 12 through a capacitor to diodes arranged in a voltage doubling manner to generate a negative voltage.
  • Substrate bias voltage regulator 11 monitors the negative voltage of substrate 10 through connection-14.
  • Regulator 11 provides an output to oscillator 12 which can control the output of oscillator 12 by inhibiting the output from oscillator 12 or else by simply controlling one of the stages of oscillator 12 to thereby reduce its output.
  • regulator 11 is illustrated as controlling oscillator 12 it will be understood that the output of regulator 11 could also be used to control the output from substrate bias generator 13.
  • regulator 11 and oscillator 12- can be powered from the single supply and generator 13, which is powered by the oscillator, can be used to generate a negative voltage for substrate 10.
  • FIG. 2 illustrates in schematic form a regulator which can be used for substrate bias voltage regulator 11 of FIG. 1.
  • the circuit of FIG. 2 shows two series connected transistors 16 and 17 which sense the voltage of substrate 10 and provide an output Vl bearing a relationship to the voltage of subsrate 10.
  • Transistor 17 has its gate and drain connected to voltage terminal V DD .
  • Transistor 17 has its source connected to the drain of transistor 16 forming a node providing output Vl.
  • the source of transistor 16 is used to sense the voltage of substrate 10.
  • Transistor 16 has its gate connected to a reference potential terminal illustrated as ground.
  • ground There are several advantages to using ground as a reference. The first is that the substrate bias voltage is not dependent upon threshold values of the transistors. Also the equations for calculating voltage V1 are easier to solve if the gate electrode of transistor 16 is tied to ground. And with the gate of transistor 16 tied to ground, transistor 16 operates in the saturated region as does transistor 17, and this makes the voltage equations solve nicely without being threshold dependent.
  • Voltage Vl is coupled to the gate electrode of transistor 18.
  • Transistor 18 has its source connected to reference potential ground.
  • Transistor 19 is connected in series with transistor 18 and has its gate and drain electrodes connected to voltage terminal V DD .
  • the source of transistor 19 is connected to the drain of transistor 18 to form a node from which voltage V2 is obtained.
  • Voltage V2 is illustrated as going to a gate electrode of transistor 21.
  • Transistors 21 and 22 are in series between reference potential ground and voltage terminal V DD .
  • Transistor 22 has its gate electrode connected to its drain electrode.
  • Transistors 21 and 22 serve as a buffer and receive voltage V2 as an input and provide voltage V3 as an output. It should be noted that voltage V2 can serve as an output from the circuitry of FIG.
  • Transistor 18 is preferably of a larger size than transistor 19 to provide a gain through transistors 13 and 19. Transistors 18 and 19, as illustrated, serve as an inverting amplifier by amplifying voltage V1 and providing it as an inverted voltage V2.
  • the circuit illustrated in FIG. 2 will provide an output voltage of approximately minus V DD divided by 2.
  • transistor 18 When voltage V1 is higher than the threshold voltage of transistor 18, transistor 18 will conduct thereby making voltage V2 low, which will inhibit the conduction of transistor 21 to provide a high output voltage V3.
  • voltage Vl When voltage Vl is below the threshold voltage of transistor 18 then transistor 18 will not be enabled and voltage V2 will be high, or in other words, equal to the voltage appearing at terminal V DD minus the threshold voltage of transistor 19.
  • transistor 21 When voltage V2 is high, transistor 21 will be enabled thereby rendering voltage V3 low or approximately equal to the voltage at the source of transistor 21, which, as illustrated, is ground.
  • the circuit of FIG. 2 provides the most useful regulating output when voltage VI equals the threshold voltage plus a small ⁇ V.
  • the ⁇ V is caused by the ratio of transistors 18 and 19 and can therefore be minimized by selection of the ratio.
  • the current through transistor 17 can be approximated by the following equation: where I 17 equals the current through transistor 17; K 17 is a constant associated with transistor 17 which is determined by width, length, and other parameters of transistor 17; V DD is the voltage at terminal V DD ; V T is the threshold voltage of transistor 17; and ⁇ V is a slight increase of voltage needed over the threshold voltage to make transistor 18 conduct.
  • the current through transistor 16 will be the same as the current through transistor 17 since they are both in series and can be set out as: where I 16 equals the current through transistor 16; K 16 is the constant associated with transistor 16; and V SUB is the voltage in substrate 10; and V T is the threshold voltage of transistor 16. If transistors 16 and 17 are made such that K 16 equals 4K 17 the two equations can be combined as follows:
  • transistor 19 is made much, much smaller.than transistor 18 then ⁇ V will be much, much smaller than V DD and the equation can be further reduced to
  • the substrate voltage can be controlled to within approximately one-half of the voltage applied to terminal VDD.
  • the substrate voltage can be controlled to within the same percentage as the voltage V DD . For example, if voltage V DD changes 10 percent the substrate voltage will change 10 percent also.
  • FIG. 3 illustrates another embodiment for the substrate bias voltage regulator 11 in FIG. 1.
  • the regulator of FIG. 3 is capable of regulating the substrate voltage to approximately a negative V DD .
  • Three series transistors 31, 32, and 33 are connected between substrate 10 and voltage terminal V DD to provide an output at node 35 which can be used to regulate the voltage at substrate 10.
  • Transistor 31 has its source coupled to substrate 10 and its gate and drain electrodes connected together to form node 34.
  • Transistor 32 has its source connected to node 34 and its gate electrode connected to reference potential ground.
  • Transistor 33 has its drain and gate electrodes connected to voltage terminal V DD and its source electrode connected to the drain electrode of transistor 32 to form node 35.
  • Transistors 36 and 37 are in series and take the signal at node 35 which is coupled to the gate electrode of transistor 37 and provide an amplified inverted output at node 40.
  • the drain of transistor 37 is tied to the source of transistor 36 to form node 40.
  • Transistor 36 has its gate and drain electrodes connected to voltage terminal V DD .
  • Transistors 38 and 39 form a buffer for the signal at node 40 and provide output V 0 .
  • the output V o will be in-phase with the signal at node 35. If the in-phase signal is not needed to control an oscillator or voltage bias generator then the output from node 40 can be used.
  • the equations determining the substrate voltage that will be provided by the regulator of FIG. 3 are similar to the equations for FIG. 2. If transistor 31 is much greater in physical size than transistor 32 the voltage at node 34 will equal the substrate 10 voltage plus the threshold voltage of transistor 31. The slight increase of voltage needed to overcome the threshold voltage will be neglected since as shown hereinbefore it is much much smaller than V DD .
  • the current through transistor 33 can be expressed by the following equation: where K3 3 is the constant for transistor 33; V DD is the voltage at voltage terminal V DD ; and V T is the threshold voltage.
  • the current through transistor 32 will equal the current through transistor 33 and can be expressed by the following equation: K 32 is the constant for transistor 32; V SUB is the voltage of substrate 10; and VT is the transistor threshold. If K 33 equals K 32 the equations can be quickly reduced in the same manner as the equation of FIG. 2 were reduced to show that V DD equals approximately minus V SUB .

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Semiconductor Integrated Circuits (AREA)
EP79302875A 1979-03-05 1979-12-12 Substrat-Vorspannungsregler Expired EP0015342B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US1752379A 1979-03-05 1979-03-05
US17523 1993-02-16

Publications (2)

Publication Number Publication Date
EP0015342A1 true EP0015342A1 (de) 1980-09-17
EP0015342B1 EP0015342B1 (de) 1984-01-25

Family

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EP79302875A Expired EP0015342B1 (de) 1979-03-05 1979-12-12 Substrat-Vorspannungsregler

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EP (1) EP0015342B1 (de)
JP (1) JPS55120158A (de)
DE (1) DE2966592D1 (de)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0032588A2 (de) * 1979-12-27 1981-07-29 Kabushiki Kaisha Toshiba Substratvorspannungsgeneratorkreis
FR2555774A1 (fr) * 1983-11-30 1985-05-31 Ates Componenti Elettron Circuit regulateur de la tension de polarisation du substrat d'un circuit integre a transistors a effet de champ
EP0143879A1 (de) * 1983-10-27 1985-06-12 International Business Machines Corporation Substratvorspannungsgenerator
EP0293045A1 (de) * 1987-05-29 1988-11-30 Koninklijke Philips Electronics N.V. Integrierter CMOS-Kreis mit Substratvorspannungsregler
US5233289A (en) * 1991-04-23 1993-08-03 Harris Corporation Voltage divider and use as bias network for stacked transistors
US5670907A (en) * 1995-03-14 1997-09-23 Lattice Semiconductor Corporation VBB reference for pumped substrates

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4638464A (en) * 1983-11-14 1987-01-20 International Business Machines Corp. Charge pump system for non-volatile ram
JP2639473B2 (ja) * 1993-09-13 1997-08-13 株式会社日立製作所 半導体記憶装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3609414A (en) * 1968-08-20 1971-09-28 Ibm Apparatus for stabilizing field effect transistor thresholds
FR2235417A1 (de) * 1973-06-29 1975-01-24 Ibm
US3913006A (en) * 1974-05-20 1975-10-14 Rca Corp Voltage regulator circuit with relatively low power consumption
US4049980A (en) * 1976-04-26 1977-09-20 Hewlett-Packard Company IGFET threshold voltage compensator
US4072890A (en) * 1976-10-18 1978-02-07 Honeywell Inc. Voltage regulator

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4229667A (en) * 1978-08-23 1980-10-21 Rockwell International Corporation Voltage boosting substrate bias generator
US4260909A (en) * 1978-08-30 1981-04-07 Bell Telephone Laboratories, Incorporated Back gate bias voltage generator circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3609414A (en) * 1968-08-20 1971-09-28 Ibm Apparatus for stabilizing field effect transistor thresholds
FR2235417A1 (de) * 1973-06-29 1975-01-24 Ibm
US3913006A (en) * 1974-05-20 1975-10-14 Rca Corp Voltage regulator circuit with relatively low power consumption
US4049980A (en) * 1976-04-26 1977-09-20 Hewlett-Packard Company IGFET threshold voltage compensator
US4072890A (en) * 1976-10-18 1978-02-07 Honeywell Inc. Voltage regulator

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, Vol. 19, December 1976 New York US E. BLASER: "Substrate Compensation for Depletion-Mode FET Circuits", page 2530 and page 2531 * The whole article * *
IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, Digest on Technical Papers, Vol. 19, February 18, 1976 New York US E. BLASER: "Substrate and Load Gate Voltage Compensation", pages 56 and 57. * The whole article * *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0032588A2 (de) * 1979-12-27 1981-07-29 Kabushiki Kaisha Toshiba Substratvorspannungsgeneratorkreis
EP0032588B1 (de) * 1979-12-27 1986-04-23 Kabushiki Kaisha Toshiba Substratvorspannungsgeneratorkreis
EP0143879A1 (de) * 1983-10-27 1985-06-12 International Business Machines Corporation Substratvorspannungsgenerator
FR2555774A1 (fr) * 1983-11-30 1985-05-31 Ates Componenti Elettron Circuit regulateur de la tension de polarisation du substrat d'un circuit integre a transistors a effet de champ
GB2151823A (en) * 1983-11-30 1985-07-24 Ates Componenti Elettron Polarization voltage regulating circuit for field-effect transistor integrated circuit substrate
EP0293045A1 (de) * 1987-05-29 1988-11-30 Koninklijke Philips Electronics N.V. Integrierter CMOS-Kreis mit Substratvorspannungsregler
US5233289A (en) * 1991-04-23 1993-08-03 Harris Corporation Voltage divider and use as bias network for stacked transistors
US5670907A (en) * 1995-03-14 1997-09-23 Lattice Semiconductor Corporation VBB reference for pumped substrates

Also Published As

Publication number Publication date
JPS55120158A (en) 1980-09-16
EP0015342B1 (de) 1984-01-25
DE2966592D1 (en) 1984-03-01

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