EP0000427A1 - Road vehicle electrical systems - Google Patents

Road vehicle electrical systems Download PDF

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Publication number
EP0000427A1
EP0000427A1 EP78300099A EP78300099A EP0000427A1 EP 0000427 A1 EP0000427 A1 EP 0000427A1 EP 78300099 A EP78300099 A EP 78300099A EP 78300099 A EP78300099 A EP 78300099A EP 0000427 A1 EP0000427 A1 EP 0000427A1
Authority
EP
European Patent Office
Prior art keywords
circuit
output
register
data
code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP78300099A
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German (de)
English (en)
French (fr)
Inventor
Kenneth Richard Bradbury Reed
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ZF International UK Ltd
Original Assignee
Lucas Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lucas Industries Ltd filed Critical Lucas Industries Ltd
Publication of EP0000427A1 publication Critical patent/EP0000427A1/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q9/00—Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
    • H04Q9/14—Calling by using pulses
    • G—PHYSICS
    • G08—SIGNALLING
    • G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
    • G08C25/00—Arrangements for preventing or correcting errors; Monitoring arrangements
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60R—VEHICLES, VEHICLE FITTINGS, OR VEHICLE PARTS, NOT OTHERWISE PROVIDED FOR
    • B60R16/00—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for
    • B60R16/02—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric constitutive elements
    • B60R16/03—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric constitutive elements for supply of electrical power to vehicle subsystems or for
    • B60R16/0315—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric constitutive elements for supply of electrical power to vehicle subsystems or for using multiplexing techniques

Definitions

  • This invention relates to road vehicle electrical systems of the general type wherein a plurality of loads " at different positions in the vehicle are controlled by a cyclically repeated signal sequence, power being supplied to the load by common conductors extending to all the loads in the system.
  • the present invention makes use of pulse code modulated signal both to identify the loads or groups of loads to be controlled and also to provide signals for controlling the loads.
  • a vehicle electrical system in accordance with the invention comprises a plurality of switch devices, a multiplicity of load devices each controlled by a corresponding load control device arranged in a number of groups, a pulse code modulated signal generating device cyclically generating on a data rail a pulse train consisting of a series of digital words, each word including one set of bits defining an address code for the various groups of load control devices and a further set of bits defining a utilization code indicating the required state of the load control devices in the group in accordance with the condition of associated ones of the switch devices, each group of load control devices having an associated digital control circuit connected to said data rail including address code recognition means and storage means for storing the utilization code associated with its address code in the pulse train, said storage means providing output signals to the load control devices of the group and means for updating the utilization code stored in the storage means only when the same utilization code is received by the digital control circuit in two successive cycles of the signal generating device.
  • the system may also include a clock signal rail on which there are provided synchronising signals.
  • the individual groups of load control devices preferably each have an internal clock which is reset periodically by the signals on the clock signal rail so that its frequency need only be approximately matched with a master clock which is used in the p.c.m. signal generating device.
  • the system includes a data rail 10, a master clock rail 11 and a supply rail 12 which extend from a pulse code modulated signal generator 13 to a plurality of digital control circuits 15, 16, 17 18 etc., Each digital control circuit controls four different loads in the vehicle system in accordance with signals it receives from the generator 13 which are in turn determined by the settings of switches in a switch matrix 19.
  • the generator makes use of an 8-channel data selector 20 (Motorola CMOS integrated circuit type MC 14512) to generate signals at its Z data output terminal according to the binary code applied to its A, B and C input terminals and the corresponding inputs at its X o ............X7 data input terminals.
  • a four bit binary counter 21 is driven by a clock 22 so that the signals at its A, B, C and D output terminals progress through the usual binary counting sequence 0000,0001 0010........etc.
  • the A and B output terminals of the counter 21 are connected to the A and B input terminals of the selector 20, but the C and D output terminals of the counter 21 are connected to two input terminals of an OR gate 23, the output terminal of which is connected to the C input terminal of the selector 21.
  • the INHIBIT input terminal of the selector 20 is connected to a CLOCK terminal of the clock 22, so that spurious signals occurring during changes in the counter state are not transmitted.
  • the C and D output terminals of the counter 21 are also connected to two input terminals of an AND gate 24, the output terminal of which is connected to the CLOCK terminal of another 4-bit binary counter 25 and also to the DISABLE terminal of the selector 20.
  • the A, B, C, and D output terminals of the counter 25 are connected to the X 09 X 1 , X 2 and X 3 data input terminals of the selector 20.
  • the logic circuit 30 is seen to comprise sixteen quadruple two input AND gates 31 a ??31 g .
  • Each group of AND gates has an input from an associated one of the outputs of the decoders 26, 27 and also has four inputs from the switch matrix 19.
  • One example of a connection to the switch matrix is shown.
  • a switch 32 is connected to four different AND gate input terminals. This switch 32, may for example, be a switch intended to control the vehicle parking lamps. Further explanation will be given hereinafter in the discussion of the operation of the system.
  • each four bit binary output of the counter 25 represents the address code of one of the digital control circuits 15, 16, 17, 18 etc of Figure 1 and output of the logic circuit 30 represents the utilization code of that group.
  • the C input of selector 20 is 0 so that the data at X o (i.e., the least significant bit of the address code) appears at the Z data output terminal.
  • the counter 21 output changes to 0001, the X 1 data appears at Z, at 0010 the X 2 data appears at Z, and at 0011 the X 3 data appears at Z.
  • the address code appears in pcm form at the Z output.
  • the Z data output terminal of the selector 20 is connected by two logical inverters 40, and a resistor 41 to the base of a pnp transistor 42 the emitter of which is connected to the supply rail 12 and the collector of which is connected to the data rail 10.
  • the master clock rail 11 is controlled by another transistor 45 with its base connected via a resistor 46 to the C output terminal of the counter 21, its emitter connected to the supply rail 12 and its collector connected to the rail 11.
  • the signal on the master clock rail 11 is high during transmission of the address code and during the second transmission of the utilization code, but low during the other two quarters of the cycle of counter 21.
  • Figure 2 also shows some components of a failure warning system which will be described hereinafter.
  • the digital control circuit includes a shift register 50 and two 4 bit latches 51 and 52.
  • the shift register 50 may be regarded as an input register since it receives data from the data rail 10 under the control of a control logic circuit 53 and a local clock 55.
  • the logic circuit 53 acts to admit data pulses from the data rail 10 to the register 50 whilst the signal on the master clock rail 11 is high.
  • the latches 51 act as a buffer register which receives data from the register 50 at certain instants as will be explained hereinafter.
  • the latches 52 act as an output register which receives data from the latches 51 and provides output signals actually controlling the load control devices 55.
  • the register 50 also receives data at one stage in the cycle from data outputs associated with the load control devices (see Figure 5) and this data is subsequently clocked out on to the data rail 10 under the control of the logic 53.
  • the "parallel enable" terminal of the register 50 is controlled by address recognition circuit 56 which produces an output whenever the address code in the register 50 is the same as the code set up on four switches 57 (or conductive liruts) of the control circuit.
  • a command verification logic circuit 58 For controlling loading the latches 51 and 52 there is a command verification logic circuit 58 the output of which goes high at an appropriate instant in the cycle if the codes stored at that instant in the register 50, and the latches 51 are identical.
  • One output terminal of circuit 58 is! connected directly to the LOAD terminal of the latches 52 and another to the LOAD terminal of the latches 51.
  • the master clock rail 11 signal goes high thereby resetting the local clock.
  • the local clock 54 is approximately synchronised with the clock 22 to a degree of accuracy sufficient to ensure that during the first twelve counts of the local clock 22, the local clock signal goes high whilst the signal from clock 22 is high. Greater accuracy of synchronisation is unnecessary.
  • Each local clock signal causes the data present on the data line to be clocked into the register 50.
  • the register 50 contains the address code.
  • the address recognition logic circuit 56 provides a pulse to the "parallel enable" terminal of the register 50, if (and only if) the address code in the register 50 matches the address of that group as set up on the switches 57.
  • the data from the load control devices 55 is thus loaded into the register 50 so that the next four pulses of the clock cause this data to be fed serially from the last stage of the register to the data rail 10 via the logic circuit 53 (the master clock rail 11 signal being low at this stage).
  • the next four clock pulses cause the utilization code to be fed serially into the register 50 and circuit 58 causes the latches 52 to receive data from the latches 51 if the contents of register 50 and the latches 51 are the same or the latches 51 to receive data from the register 50 if not.
  • each of the load control devices includes an npn Darlington transistor 60 a 60 b 60 c 60 d with its emitter earthed and its base connected by a resistor 61 a , 61 b , 61 c , 61 d , to the appropriate output terminal of the register 52.
  • the collector of each such transistor is connected by a relay winding 62a, 62b, 62c, or 62d, to the supply rail 12.
  • the load devices L 1 , L 29 L 3 and L 4 are connected in series with normally open contacts of respective ones of the relays between the supply rail 12 and earth.
  • the load condition data signals are derived from connections to the junctions of the loads with their respective control contacts, such contacts being bridged by resistors 63a, 63b, 63c, and 63d so that these signals are high when the contacts are closed, but low when the contacts are open.
  • a "failsafe" circuit 66 which is normally held inactive by pulses from the command verification logic circuit 58.
  • the "failsafe" circuit includes an input capacitor 75 connecting the output terminal of the circuit 58 to the anode of a diode 67, with its cathode connected to one side of the capacitor 68 the other side of which is grounded, a resistor 69 being connected across this capacitor.
  • a further diode 76 has its cathode connected to the anode of diode 67 and its anode grounded.
  • the cathode of the diode 67 is also connected to the base of a pnp transistor 70 via a resistive potential divider 77, 78 the emitter of which is connected to the supply rail.12 and the collector of which is connected via resistive potential divider 79, 80 to the base of an npn transistor 71.
  • the emitter of the transistor 71 is connected to the earth rail and its collector is connected by a load resistor 72.
  • the collector of the transistor 71 is also connected to the cathodes of-three diodes 73a, 73b, 73c and 73d associated with the load control devices of the loads L 1 , L 2 , L 3 and L 4 respectively.
  • Diodes 73a and 73b therefore have their anodes connected to the collectors of the transistors 60a and 60b, whilst diodes 73c and 73d have their anodes connected to the bases of the transistors 60c and 60d.
  • a further diode 74 has its anode connected to the cathodes of the diodes 73a to 73d and its cathode connected to the supply rail 12. This diode 74 provides a path for recirculating current when any of the transistors 60 L to 60d is switched off.
  • this circuit includes an AND gate 100 with inputs from the clock 22 and from the C output terminal of the counter 21.
  • the output of this gate 100 is applied to two further AND gates 101, 102.
  • Gate 101 has an input from the Z terminal of the selector 20 and another input via an inverter 103 from the data rail 10.
  • Gate 102 has a direct input from the data rail 10 and an input from the terminal Z via an inverter 104.
  • the failure warning circuit is operative during the first transmittal of utilization code, at which time the signals on the data rail 10 are those derived from the load control devices. If at any time whilst gates 101 and 102 are enabled by gate 100 (i.e. during the four clock pulses whilst C is high) the Z output is high but the data rail signal is low gate 101 will produce an output, indicating a filament or actuator failure. Similarly if the Z output is low whilst the data rail signal is high gate 102 will produce an output, indicating a system failure.
  • the system described above provides a multiplex control system for a plurality of separate loads which overcomes many of the prior art shortcomings.
  • the system has very high immunity to interference and also incorporates simple fault monitoring and failsafe functions.
  • an oil pressure warning switch may be connected appropriately to one of the groups of "load control" devices so that when that group is addressed om of the bits of the four-bit code transmitted back to the central unit will indicate whether this switch is open or closed.
  • the data line can also be used for the transmission of analog signals such as fuel gauge signals.
  • one of the stages of the shift register 50 may be capable of receiving and storing analog signals instead of just digital signals.
  • the analog signal is received by this stage of the register 50 and then transmitted back to the central unit along with the other three digital signals.
  • the stage which is suitable for analog signals is that from which the output to the data rail is taken.
  • CMOS hardward the function can also be carried out conveniently utilising a suitably programmed micro-processor unit.
  • the same unit can be used to process the data received from the individual groups A, B, C, D, etc and provide a suitable display.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Selective Calling Equipment (AREA)
  • Electric Propulsion And Braking For Vehicles (AREA)
EP78300099A 1977-07-09 1978-06-28 Road vehicle electrical systems Withdrawn EP0000427A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB2889777 1977-07-09
GB2889777 1977-07-09

Related Child Applications (2)

Application Number Title Priority Date Filing Date
EP79200406.1 Division-Into 1978-06-28
EP79200405.3 Division-Into 1978-06-28

Publications (1)

Publication Number Publication Date
EP0000427A1 true EP0000427A1 (en) 1979-01-24

Family

ID=10282952

Family Applications (3)

Application Number Title Priority Date Filing Date
EP79200405A Ceased EP0011312A1 (en) 1977-07-09 1978-06-28 Road vehicle electrical systems
EP78300099A Withdrawn EP0000427A1 (en) 1977-07-09 1978-06-28 Road vehicle electrical systems
EP79200406A Withdrawn EP0011313A1 (en) 1977-07-09 1978-06-28 Road vehicle electrical systems

Family Applications Before (1)

Application Number Title Priority Date Filing Date
EP79200405A Ceased EP0011312A1 (en) 1977-07-09 1978-06-28 Road vehicle electrical systems

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP79200406A Withdrawn EP0011313A1 (en) 1977-07-09 1978-06-28 Road vehicle electrical systems

Country Status (3)

Country Link
EP (3) EP0011312A1 (it)
JP (1) JPS5440414A (it)
IT (1) IT1105753B (it)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0013103A1 (en) * 1978-12-22 1980-07-09 LUCAS INDUSTRIES public limited company Motor vehicle electrical system
FR2477738A1 (fr) * 1980-03-10 1981-09-11 Control Data Corp Appareil de commande et de controle destine a etre utilise entre un poste central de calculateur et des postes terminaux
EP0136398A2 (de) * 1983-10-04 1985-04-10 WABCO GmbH Einrichtung zum Abfragen und Steuern von mehreren Konponenten einees Fahszeugs
EP0751454A2 (en) * 1995-06-29 1997-01-02 Yazaki Corporation Control-specification design system used for load control devices
EP0788929A1 (en) * 1996-02-12 1997-08-13 Applied Power Inc. Communication system for data transmission in a control device of a car

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2514522A1 (fr) * 1981-10-09 1983-04-15 Commissariat Energie Atomique Dispositif de securite entre un systeme de commande d'un actionneur de surete et un circuit logique de commande de cet actionneur
US4398233A (en) * 1982-03-03 1983-08-09 Electronics Corporation Of America Fail-safe device for electronic control circuit
US4524449A (en) * 1982-09-28 1985-06-18 Framatome & Cie. Safety device
JPS59117395A (ja) * 1982-12-24 1984-07-06 Hitachi Ltd 端末処理装置
US4847613A (en) * 1986-07-15 1989-07-11 Matsushita Electric Industrial Co., Ltd. Data transfer apparatus
GB8710197D0 (en) * 1987-04-29 1987-06-03 Lotus Group Plc Intelligent wiring system
DE3730468A1 (de) * 1987-09-08 1989-03-16 Bergmann Kabelwerke Ag Bordnetz fuer kraftfahrzeuge und verfahren zum betrieb des bordnetzes
DE68926677T2 (de) * 1988-02-29 1996-11-14 Komatsu Mfg Co Ltd Datenaufnahmeschaltung für serielle kontrolleinheit
EP0424907A3 (en) * 1989-10-24 1992-04-08 Nissan Motor Co., Ltd. System and method for communicating data between master and slave stations utilizing time division multiplex mode with failsafe provision applicable to automotive vehicles
GB2277618B (en) * 1993-04-28 1996-08-07 Henlys Group Plc Motor vehicle
US5553070A (en) * 1994-09-13 1996-09-03 Riley; Robert E. Data link module for time division multiplexing control systems
PL3644999T3 (pl) 2017-06-30 2023-05-08 Celgene Corporation Kompozycje i sposoby zastosowania 2-(4-chlorofenylo)-n-((2-(2,6-dioksopiperydyn-3-ylo)-1-oksoizoindolin-5-ylo)metylo)-2,2-difluoroacetamidu

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3864578A (en) * 1973-12-26 1975-02-04 Texas Instruments Inc Multiplex system for a vehicle
DE2433025A1 (de) * 1974-07-10 1976-01-22 Bosch Gmbh Robert Verfahren und vorrichtung zum steuern und kontrollieren von elektrischen schaltvorgaengen, insbesondere in kraftfahrzeugen

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1588397C3 (de) * 1964-03-10 1975-08-07 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Fernwirkempfänger für den Empfang von zeitmultiplex übertragenen pulscode modulierten Wörtern
US3699522A (en) * 1966-09-20 1972-10-17 Gen Signal Corp Locomotive radio control system with address and command signals
DE1966370C3 (de) * 1969-09-17 1979-12-13 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Anordnung zum Empfang und zur Aussendung einer binär codierten Information
AT327287B (de) * 1972-09-20 1976-01-26 Siemens Ag Einrichtung zum selbsttatigen auslosen eineszustandes hoherer sicherheit in von einer zentrale zyklisch aufgerufenen unterstationen sicherungstechnischer anlagen, insbesondere eisenbahnanlagen, bei unterschiedlichen ubertragungsstorungen

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3864578A (en) * 1973-12-26 1975-02-04 Texas Instruments Inc Multiplex system for a vehicle
DE2433025A1 (de) * 1974-07-10 1976-01-22 Bosch Gmbh Robert Verfahren und vorrichtung zum steuern und kontrollieren von elektrischen schaltvorgaengen, insbesondere in kraftfahrzeugen

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0013103A1 (en) * 1978-12-22 1980-07-09 LUCAS INDUSTRIES public limited company Motor vehicle electrical system
FR2477738A1 (fr) * 1980-03-10 1981-09-11 Control Data Corp Appareil de commande et de controle destine a etre utilise entre un poste central de calculateur et des postes terminaux
EP0136398A2 (de) * 1983-10-04 1985-04-10 WABCO GmbH Einrichtung zum Abfragen und Steuern von mehreren Konponenten einees Fahszeugs
EP0136398A3 (en) * 1983-10-04 1987-10-07 Wabco Westinghouse Fahrzeugbremsen Gmbh Questioning and controlling device for several vehicle components
EP0751454A2 (en) * 1995-06-29 1997-01-02 Yazaki Corporation Control-specification design system used for load control devices
EP0751454A3 (en) * 1995-06-29 1997-03-05 Yazaki Corp System for designing control specifications for devices for controlling loads
US6522935B1 (en) 1995-06-29 2003-02-18 Yazaki Corporation Control-specification design management system used for load control devices
EP0788929A1 (en) * 1996-02-12 1997-08-13 Applied Power Inc. Communication system for data transmission in a control device of a car

Also Published As

Publication number Publication date
IT1105753B (it) 1985-11-04
EP0011312A1 (en) 1980-05-28
IT7850203A0 (it) 1978-07-07
JPS5440414A (en) 1979-03-29
EP0011313A1 (en) 1980-05-28

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Inventor name: REED, KENNETH RICHARD BRADBURY