EA028368B1 - Device for calculation of unitary codes modulo three - Google Patents

Abstract

The present invention relates to the field of computer engineering and microelectronics and can be used for constructing hardware control devices and digital devices operating in a residual class system. The device for calculation of unitary codes modulo three contains three elements EQUIVALENCE, four inputs and three outputs. The complexity of the device in terms of the number of inputs of logical elements is 10, and the speed of operation determined by the depth of the circuit is equal to 2τ, where τ is the delay to the logical element. The device has seven external terminals. The device is designed for calculation in the unitary codes of the operation A+B+AB=S (mod 3) and works as follows. The inputs of the device receive the values of bits "equal to zero", "equal to one" of the unitary binary code of the first operand A=(a, a, a) and values of bits "equals to zero", "equal to one" of the unitary binary code of the second operand B=(b, b, b), where a, a, a, b, b, b∈{0,1}. Here, a=1 and b=1 if and only if A=k (mod 3) and B=k (mod 3), where k=0, 1, 2. At the outputs of the device, a unitary binary code of the result of the operation A+B+AB=S (mod 3) is formed, where S=(s, s, s), s, s, s∈{0,1} and s=1 if and only if A+B+AB=k (mod 3) and k=0, 1, 2.

Description

The present invention relates to the field of computer engineering and microelectronics and can be used to build hardware controls and digital devices operating in a system of residual classes.

Known computing device for the multiplication of unitary codes modulo three, which contains an OR element, two elements EXCLUSIVE OR with a threshold of three, six inputs and three outputs [1].

The device is designed to calculate in unitary codes the operation of multiplication ΑΒ = δ (volume 3). The complexity of the device (by the number of inputs of logic elements) is equal to 14.

The disadvantages of the known device are the narrow functionality, since the device does not allow to calculate the arithmetic operation Α + Β + ΑΒ = δ (volume 3), and high structural complexity.

The closest in functionality and design the technical solution to the proposed device is the adder of unitary codes modulo three, which performs the operation Ά + Β = δ (volume 3) [2].

The prototype device contains three OR elements, three EQUIVALENCE elements, six inputs and three outputs. The adder difficulty is 12.

The prototype device, like the present invention, contains from the first to the third elements of SIGNIFICANCE, the output of the ΐ-th of which, where 1 = 1, 2, 3, is connected to the output is ΐ-1 of the result.

The disadvantage of the prototype device is the narrow functionality, since the adder is not designed to perform the operation Α + Β + ΑΒ = δ (volume 3).

The invention is aimed at expanding the functionality of the prototype device due to the implementation in unitary codes of the arithmetic operation Α + Β + ΑΒ = δ (volume 3).

The modular three computing device of unitary codes contains from the first to the third elements the UNIVERSITY, the output of the ΐ-th of which, where 1 = 1, 2, 3, is connected to the output is ΐ-1 of the result.

Unlike the prototype, the first direct inputs of the first and second elements of the UNIVERSITY are connected to the input equal to zero of the first operand, the input of which is equal to one is connected to the first inverse inputs of the first and second elements of the UNIVERSITY.

The input is zero the second operand is connected to the second direct input of the first element of the UNIVERSITY and to the second inverse input of the second element of the UNIVERSITY.

The input is equal to the unit of the second operand is connected to the second inverse input of the first UNIVERSITY element and to the second direct input of the second UNIVERSITY element.

The output of the second UNIVERSITY element is connected to the first input of the third UNIVERSITY element, the second input of which is connected to the output of the first UNIVERSITY element.

The named technical result is achieved by removing OR logic elements from the prototype device circuit and changing the connections between the elements of the device logical circuit.

The drawing (Fig. 1) shows a logical diagram of a computing device unitary codes modulo three.

The unitary computing device modulo three contains three elements SIGNIFICANCE 1, 2 and 3, four inputs 4-7 and three outputs 8, 9 and 10.

A computing device designed to perform the operation Α + Β + ΑΒ = δ (volume 3) in unitary codes works as follows.

The inputs of device 4 and 5 receive the values of the bits equal to zero and equal to the unitary binary code of the first operand Α = (α ₀ , and ₁ , and ₂ ), to the inputs 6 and 7 - the values of the bits are zero and equal to the unitary binary code of the second operand B = (b ₀ , b ₁ , b ₂ ).

At the outputs of the device 8, 9 and 10, a unitary binary code of the result of the operation Α + Β + ΑΒ = δ (that 3) is formed, where δ = (δ ₀ , δ ₁ , δ ₂ ) and δ ₀ , δ ₁ , δ ₂ e {0, 1}. Here 8 _k = 1 if and only if Α + Β + ΑΒ = Ε (of that 3).

The logic diagram (see Fig. 1) of the device for calculating the operation Α + Β + ΑΒ = δ (volume 3) in unitary codes is synthesized based on the use of the following analytical expressions of the functions δ ₀ , δ ₁ , δ2:

1, if a§ + b§ + a _} + 6 ₁ = 0 or α _ϋ + δ ₀ + α, + ^ = 4, 0 - otherwise, ^ 1 =

1, if a ₀ + b _о -m <7 ₁ + b _x = 0 or a ₀ + b _о + a _} + b _} = 4, 0 otherwise, and 8 ₂ = 5 _θ ~ 5, where ~ - logical operation equivalence.

The truth table of the logical functions δ ₀ , δ ₁ and δ ₂ , describing the operation of the computing device of unitary codes modulo three, is presented through the table (see Fig. 2).

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The main advantage of the claimed computing device unitary codes modulo three are wide functionality. The structural complexity of the device (by the number of inputs of logic elements) is 10.

Sources of information taken into account during the examination

1. Patent RB No. 12000, IPC Θ06Ρ 7/38, BI No. 3 (68), 2009, p. 167.

2. Patent RB No. 3270, IPC С06Р 7/49, BI No. 1 (24), 2000, p. 187 (prototype).

Claims (1)

CLAIM The computing device of unitary codes modulo three, containing the first to third elements of UNIVERSITY, the output of the ΐ of which, where 1 = 1, 2, 3, is connected to the output is 1-1 of the result, characterized in that the first direct inputs of the first and the second elements of the UNIVERSALITY are connected to the input equal to zero of the first operand, the input of which is unity connected to the first inverse inputs of the first and second elements of the UNIVERSITY, the input is zero to the second operand is connected to the second direct input of the first element of the UNIVERSITY waist EQUIVALENCE gate input of the second element, the input unit is equal to the second operand is connected to the second inverted input of the first element and a second EQUIVALENCE direct input of the second element EQUIVALENCE gate whose output is connected to a first input of the third element EQUIVALENCE gate, a second input coupled to an output of the first element equivalent.