EA001361B1 - Multiplier circuit for power measurement equipment and method for measuring momentary value of power - Google Patents

Abstract

1. A multiplier circuit for power or energy measurement equipment (P, W, 30, 40), comprising (a) a first measured (9) analog signal (u(t)) is supplied to a first sigma-delta converter (SDM1; 10), whose output controls a multiplier (20; 20a, 20b, 20c, 20d; 21a, 21b, 22a, 22b), wherein (b) a second measured (9) analog signal (i(t)) is supplied to the multiplier (20), and (c) the output of the multiplier (20) is supplied to a second sigma-delta converter (SDM2; 30) which generates at its output an output signal (p(t)) which represents the momentary value of the product of the first and the second analog signals (u(t), (i(t)), characterized in that (d) two digital inverter stages (50a, 50b) are arranged before the multiplier (20), and after the second sigma-delta converter (30) and are synchronously driven at a low-frequency (fc), wherein (e) the operating frequency of the sigma-delta converters (10, 30) lies in the MHz range, frequencies of alternating analog signals (fu, fi) lie in the 20 to 1000 Hz range, and the switching frequency of the digital inverter stages lies below 10 Hz, to maintain operation of both sigma-delta converters (10, 30) for measuring the output signal (p(t)) the switching frequency of the digital inverter stages is selected to compensate the offset of the two sigma-delta converters at a frequency that is markedly lower than the frequencies of the measured analog signals. 2. The multiplier circuit according to claim 1, characterized in that (a) the operating value of the first signal (u(t)) is less than the AC variable signal, in particular, of the signal which is the network voltage (uNetz(t)), and (b) the operating value of the second signal (i(t)) is considerably higher of the AC variable signal, in particular, of the signal which is the network current (iNetz(t)). 3. The multiplier circuit according to claim 2, characterized in that the network voltage and the current are measured from 110V, 220V or 380V. 4. The multiplier circuit according to any preceding claim, characterized in that the output signal (p(t)) is supplied to an analog or digital integrator (40), in particular, a reversible counter, the counter levels of which are operable to read at least one period, preferably two or more periods of the alternating analog signals (u(t), (i(t) and reading the binary output signal of the second sigma-delta converter (30) without overflowing , so that the integrator output (40) calculates continuously the work (w(t) performed by both analog signals. 5. The multiplier circuit according to any preceding claim, characterized in that the first and the second digital inverter stages (50a, 50b) are "exclusive OR" circuits. 6. The multiplier circuit according to any preceding claim, characterized in that the multiplier has two outputs and (a) comprises four analog switches (20a, 20b, 20c, 20d) connected by a bridge-type circuit, wherein the bridge arm is an output, and the upper, and correspondingly, the lower bridge arm are the first input of the multiplier (20), wherein the second input of the multiplier (20) is a digital input, which closes and breaks simultaneously two corresponding analog switches (20f, 20d, 20b, 20c), wherein simultaneously closed and broke analog switches are accordingly one upper analog switch of one bridge arm and one lower analog switch of the other bridge arm, so, independently from the output signal (ux) of the first sigma-delta converter (10) to actuate the analog switches and transmit the second analog signal (i(t) in accordance with the position of the analog switches directly or with an inverted polarity; or (b) has two multiplexes, the multiplex outputs of which are connected together and form the second input of the multiplier (20), to which the output signal of the first sigma-delta converter (10) is supplied, wherein the first input (21a, 21b) of the multiplier (20) has two analog switches (22a, 22b), which, depending on the output signals of the multiplexes gate either the second analog signal (i(t) or the analog-inverted second analog signal (-i(t) as an output signal of the multiplier (20), wherein opposite frequency signals (f1, f2; f2, f1) are continuously supplied to both multiplexes on their multiplication inputs which are not overlapping clock signals for control the analog switches of the sigma-delta converters (10, 30) in switched capacitor circuity. 7. The multiplier circuit according to any preceding claim, characterized in that the sigma-delta converters (30, 10) generate currency density in bits proportional to the analog input signal (u(t), (i(t) as the sigma-delta converters of the first degree where the ratio of the logical unit level to the logical zero level is proportional to the momentary value of the input signal. 8. The multiplier circuit according to claim 5, characterized in that the frequency of the low frequency switching (fc) is considerably lower of the frequency (fu, fi) of the alternative analog signals (u(t), (i(t), if the signals of AC current are used as the input signals. 9. A method for measuring the momentary value of the power in a measurement equipment, in particular, for both voltage and current in the network, in which (a) the digital flow current in bits of the high frequency (ux) is controlled by the density of both logical levels proportionally to the first analog signal (u(t), the frequency of which is substantially lower the current frequency in bits, (b) the first digital flow current in bits (ux) switches the sign or the polarity (20) of the second analog signal (i(t), the frequency of which (fi) coincides by the order of values with the frequency of the first analog signal to obtain the basic signal with a switchable high frequency polarity (uy), which is suitable for determining the multiplication signal (uz), characterized in that (c) operating currencies (f1, f2) of the density control and switching (10, 20) mainly higher than the frequencies (fu, fi) of the analog signals by 10<5> - 10<6>, but if direct analog signals are used then the operating frequencies (f1, f2) are above 1 MHz. 10. The method according to claim 9, characterized in that the multiplier (20) is the multiplier of the sign inversion. 11. The method according to claim 9 or 10, characterized in that the basic signal (uy) is evaluated without analog-digital conversion using parallel output or without forming the product respective its low-frequency component, in particular using the secondary sigma-delta converter (30), which generates at the output the multiplication signal (uz = p(t). 12. The method according to claims 9 to 11 characterized in that the first analog signal is measurable voltage (u(t), in particular, domestic network voltage, and the second analog signal is measurable current (i(t) in said network in case of calculating the momentary value of the power taken from the network. 13. The method according to claims 9 to 11 characterized in that the analog signals are the alternative analog signals.

Description

The invention relates to a technique for measuring power, with which the instantaneous value of the power actually taken from the network is calculated, and the current and voltage of the network are variable values, the voltage is less, however, noticeable, and the current is more noticeable, since its effective value is Significantly determines the power, namely, either the current is taken with a certain value (there is a withdrawn power) or the current is almost zero (no power is taken).

Sigma-delta converters are described in EP 90313050.8, they are described there in connection with a power measurement device, however, in this level of technology, an analog-to-digital converter (ΑΌυ) (indicated by the position 5 there) is used which adversely affects the cost of an instrument manufactured in large quantities .

The objective of the invention is to reduce the cost of such an instrument while maintaining accuracy or even increasing it. The problem is solved using a multiplication circuit for a device measuring power or energy.

The output of the sigma-delta converter (or modulator) with its current in bits is used to switch the polarity sign of the second analog signal proportional to the current density in the output bits of the first modulator (8ΌΜ). Switching the sign is performed by a multiplication device, which, however, is not an analog multiplier in the usual circuit design sense, but can be made in the form of alternative solutions (a) and (b) according to claim 6 of the claims.

With the help of the invention, it is achieved that it is possible to dispense with an analog multiplier for analog current and voltage measuring signals, without an analog-digital converter with parallel output and, as a result, also called the latter without a digital multiplier, if it is necessary to measure the instantaneous power value.

In the method according to claim 10 of the claims work with the first current in bits of high frequency, which is the digital current in bits. This current in bits modulates the (second) analog signal and thus creates a base signal and _y , which is influenced by the first analog signal, as well as the second signal, and thus the premise of determining the υ _ζ multiplication signal from it is fulfilled. If you select the first analog signal that determines the current density in the sigma-delta modulator bits proportional to the voltage, and choose the second analog signal proportional to the current, the multiplication signal produces power that appears when you evaluate the low-frequency part of the base signal with high-frequency switching polarity.

The multiplication mentioned above, which in conventional power measurement instruments is present as an analog multiplier, is limited with the above principles to what is a sign change or multiplication by ± 1, which can be achieved using simple circuit technology at low cost. You can also opt out of a complex digital multiplier, which, although it can be created without the offset problems inherent in analog multipliers, however, is associated with significant circuit costs and requires many binary digits to achieve still sufficient accuracy.

Thus, the input value of the second sigma-delta converter corresponds to the instantaneous power, it is converted by the modulator into the digital plane and can be converted by using a reversible counter into the selected energy (kW / h, so-called work). The integrator can be made analog or digital (clause 4 of the claims), preferably mentioned is a reversible counter.

It is important to note that the proposals according to the invention can be used not only for analog signals of alternating voltage (mains voltage, mains current), but also for such variable voltages that have a very low frequency, even to zero frequency. Thus, the circuit is also suitable for multiplying the DC voltage signals with each other without using an analog multiplier or analog-to-digital converter, which, based on the sampling memory block, provides the reading value of the analog value stored in the memory block. The latter-mentioned blocks are expensive and complex and can be abandoned in the solution according to the invention.

The multiplication of the sign can be achieved in a simple way using a bridge circuit of four analog switches (claim 6, first alternative), while the analog switches are unlocked and locked crosswise, so that the input analog signal is passed through a very low impedance direct resistance of the first pair of analog switches, or the input conductors are replaced and the signal is transmitted inverted through another pair of low-impedance analog switches as a signal multiplied by -1.

The offset and nonlinearity problems of analog switches can be solved by circuit-technical methods and they cannot negatively affect the circuit according to the invention.

Using the circuit according to the invention, it is possible to achieve a high class of accuracy of power measurement instruments.

You can also create a bias suppression circuit by type DC amplifier with modulation and signal demodulation, if you place two inverting stages on the digital level before the sign inverting device and after the second sigma-delta modulator and turn them on synchronously inverting or not inverting (paragraph 5 and 9 claims).

The invention is illustrated and supplemented below in several exemplary embodiments using the drawings, in which FIG. 1 is a block diagram of a voltage and current multiplier for an AC voltage multiplier. The input signals a '(1) and b' (1) can also be direct current signals (alternating voltage with frequency zero);

FIG. 2 is a detailed diagram of FIG. 1, in the lower part of which an analog switch is shown (left) and a non-overlapping clock cycle for an analog switch (right), in the example of switch 20a;

FIG. 2a is a view of the modulation signals measured in FIG. one ;

FIG. 3 is a circuit with digital offset correction using two exclusive OR circuits 50a, 50b and frequencies 1 _sec. 6 Hz. Clocks 11, 1 ₂ for the logic circuit with switched capacitors and the correction frequency of 1 _s are shown below;

FIG. 4 - an alternative embodiment of a multiplier 20 which performs a sign change, controlled by the signal current density in bits and _x, a first inverter 1 0 sigma-delta, the alternate embodiment is provided with two multiplexers 21a, 21 b, which are controlled by both frequencies £ _v 1 ₂ (in the MHz range), which also control the circuit of FIG. 1 as a circuit with switched capacitors. You can use a single schema concept.

The power measurement circuit of FIG. 1 consists of two modulators 10, 30 sigmadelta, an analog AM modulator, a clock generator and a battery of pulses, which are connected according to FIG. 1. The analog input signal and (1), which is proportional to the measured voltage, is converted using the first modulator 10 into a digital current and _x (1) in bits. Equipped with one analog input modulator (AM) is controlled by two signals. On the analog side, it is proportional to the current 1 (1) signal and on the digital control side is the signal and _x (1) current in bits. The modulator multiplies the sign and _x (1) with an analog input signal. Thus, the modulator output signal in its average value is proportional to the product 1 (1) and and (1), since _x (1) in its average value corresponds to (1). Then, the modulator output signal is fed to the second sigma-delta modulator 30. Thus, the output pulse current in its estimate is also proportional to the product 1 (1) and and (1). The resulting pulse current and ₂ (1) at the output of the second modulator sigma-delta is supplied to the accumulator input of the adder 40 (for example, a reversible counter). The battery output is a low-frequency current in bits that corresponds to average power. Through integration, the high-frequency quantization noise of the modulators is largely suppressed.

Both identical circuit blocks are composed of first-order synchronous sigma-delta modulators. In addition to both sigma-delta modulators, almost no other circuit elements are required. This is an advantage.

A conventional first-order sigma-delta modulator contains an integrator, a 1-bit quantizer (comparator), one output that is read at a reading frequency of RB. and 1-bit digital-to-analog converter, which gives +/- to YGA! in accordance with the sign of the read signal of the comparator. At each reading point, the integrator integrates the difference (error signal) between the input and (1) and the output of the converter. The sign of the difference during the reading period is stored in the quantizer. If the output of the comparator at (1) is logical 1, then the positive voltage + Ie £ is fed back to the input of the integrator. The signal fed back in its pulse sequence is proportional to the input signal, since the integrator error is adjusted to zero. As a Ζ-transformed signal, the function of the modulator can be described by the following formula:

Y (x) = χ (ζ) + (1-ζ ^-1 ) x Ο (ζ), where 0 (ζ) is the quantization noise of the modulator. The spectrum of the second term of the equation is in the high-frequency range slightly below the base range and can therefore be easily suppressed using digital filtering, as well as, for example, using integration.

The big advantage of sigma-delta modulators is their good integrability in conventional integrated circuit technologies. Typical sigma-delta modulators use conventional integrated circuits with switched capacitor integrators. This represents one of the most efficient microelectronics technologies, since switching capacitor circuits can be easily manufactured with high quality using mass production technology, such as CMOS.

The principle of operation of circuits with switched capacitors uses charge transfer between capacitors switched with analog switches. In this case, the switching frequency is chosen so that it is significantly higher than the frequency of the input signals. In the example of a current meter, the read frequency is typically in the MHz range compared to the 50 or 60 Hz frequency of the input signals. An analog switch in circuits with switched capacitors is controlled by non-overlapping rectangular signals with opposite phase (see, for example, Fig. 2 below). The clock generator circuit is constructed so that the switching fronts of the signals do not overlap with each other with an adequate margin. This prevents loss of charge during transmission. During one phase of the clock signal, one part of the capacitors is connected to a voltage source and charged to this voltage. During the second phase of the clock signal, charges are transferred by analog switches and operational amplifiers to other capacitors. As a result, the output signal can be described using a mathematical operation with the input signal, such as addition, subtraction, multiplication with constant coefficients, delay or integration, for which only capacitors with different ratios are needed, analog switches and operational amplifiers. For example, a high resistance can be approximated using a small capacitor C3, which switches with the switching frequency Pz. Equivalent resistance corresponds to 1 / (Pz-Cz). If this signal is connected to a non-switched capacitor Spi or to a summing node of an operational amplifier with a non-switched capacitor in the feedback circuit, then using this resistance you can set the time constant To · С = [(StG (СзГз)]), which is determined only by the ratio of capacitors and switching frequency. This is a big advantage of switched capacitor circuits, since using conventional integrated circuit technology, the ratio of capacitors can be very accurate. m, while the absolute values of capacitors using conventional integrated circuit fabrication techniques can only be performed not accurately, this is why switching circuit capacitor technology is used in many transformation principles with a high degree of resolution.

FIG. 2 shows the possible implementation of the scheme according to the invention. In typical cases, such circuits are completely differential in the analog data branch. To simplify the image, only an asymmetric circuit with switched capacitors is shown here. The analog modulator is represented by four cross-connected analog switches 20a - 20ά, which allow you to invert the polarity of the input signal (ΐ). The input signal of the first modulator sigma-delta 3ΌΜ1 produces the output signal and _x (1). If the signal is logical zero, then the modulator output and _y (1) =-у (ΐ). If _x (1) = -1, the modulator output signal corresponds to the input signal and _y (1) = ΐ (ΐ). Schemes of individual sigma-delta modulators are shown inside the dashed boxes. Modulators 3ΌΜ1 and 3ΌΜ2 use a well-known technique of circuits with switched capacitors with automatic zero with two differential inputs and consist of operational amplifiers OA2 and OA1, input switched capacitor C1, reference switched capacitor C2, integrating capacitor C3 and various switches that are controlled by two non-overlapping each on the other clock signals ί) and ί ₂ . The sign of the integrated differential signal between the modulator input and the output of the DAC during one switching period is determined by a comparator K1 or K2 and stored for one period of clock pulses in the-trigger. The comparator output, consisting of two AND schemes, controls, via the DAC, a source of reference voltages (+ Uge £ or-UTEG), which are integrated in the next readout period. Additionally, using the 8 И2 modulator And 30 circuits, the output pulse currents are separated so that one represents the instantaneous positive measured power and ₂ (1) and the second output represents the negative measured power. Two pulse currents are accumulated in a η-bit reversible counter. The output of the counter gives a pulse current \ y (!) With a density of pulses that corresponds to the average value of the active power.

and (’b) x 1 (C)

RD1) ~ ------------------------- x Ps.

ϋκθί ²

The sigma-delta modulator input (for example, and (1) or _y (1)) is switched to the differential inputs of the integrator. The integrator reference input is switched with the output of the DAC (+ Uge £ or Ugr) using a common switch that connects the integrator and the DAC. The switched capacitor integrator contains a self-tuning to zero (automatic zero setting), which reduces the bias voltage of the operational amplifiers and low-frequency noise. This is achieved by using a correlated double reading. With correlated double reading, each reading period is divided into two subgroups. During the first subgroup, the offset is read and during the second subgroup the offset is subtracted from the input signal. Due to this, it is possible to achieve effective suppression of bias voltages, which are technologically unavoidable.

The offset reading is performed during the E1 phase due to the closure of the feedback switch between the inverting input and the output of the operational amplifier. Thus, the capacitors C1 and C2 are charged to the input bias voltage of the operational amplifiers (Vo). The second pole of the capacitors is charged from one side to the positive input voltage V1n + (k) of the modulator (where k is the constantly increasing number of the readout period) and in the other capacitor to zero voltage. During phase E1, capacitor C3 is separated from the input of the operational amplifier and the integrator holds the charge that was previously transferred to capacitor C3.

During phase E2, capacitor C1 is discharged to negative input voltage V1n- (k), while the right side of capacitor C1 is held approximately at the bias voltage of the operational amplifier, because the input of the operational amplifier remains unchanged due to feedback through capacitor C3. This means that during phase E2, the charge accumulated in capacitor C1 (C1p (k) * C1) is recharged to capacitor C3, regardless of the bias voltage of the operational amplifier. At the same time, the voltage ± T2 * C2, regardless of the offset, is recharged from C2 to C3, and this happens depending on the sign of the integrator's output signal in the preceding reading period. Therefore, the bias voltage does not affect the transfer from the integrator input to the output.

With this in mind, in each read cycle during the E2 phase, part of the charge is transferred from the signal input and the reference voltage and integrated in capacitor C3, and then the integrator output voltage is updated. The output voltage of the integrator U1 (k) at the end of the integration phase E2 after the k-th cycle changes by the value of delta k and can be described by the following equation

A (k) = Ut1 (k) -Upy (k-1) = [Ush (k) x (C1 / Sz) + 8O (k-1) xi _Ke gx (S2 / Sz)], k

Us1 (k) = £ [Δ (η)] + Vo8, where 8I (k-1) = sign [Usotr (k-1)] = ± 1 - the sign of the integrator's output, which during the negative front E2 is in k-1 The reading cycle corresponds to phase E2.

Comparators K1 and K2 simultaneously detect the sign of the comparator output, and the value at the end of each integration phase E2 is used only as a feedback signal for the next period. Therefore, the comparator output voltage is read only on the negative front E2 and its sign is stored in the три-flip-flop at this instant of time, thereby creating 8I (k). In practice, it is possible to combine an три-trigger, a comparator, and a read logic circuit in one circuit.

Outputs Ό-flip-flop, which remember the previous state of the trigger, determine the sign of the output of the source of the DAC during phase E2 in the clock cycle. FIG. 2a shows typical modulator signal characteristics for a positive input voltage. Trigger output 8Ό (ΐ) corresponds to the modulator output signal. Significant errors arise from quantization noise in the high frequency range, which can be effectively suppressed using digital filtering. With the help of appropriate filters, a resolution of 20 bits or more is currently achieved in sigma delta modulators.

Poi1 (1) ~ (C1 / C2) x (Ρδ / υ _Η6ί ) x Ush (1).

In actual use, the accuracy of sigma-delta modulators is limited to non-ideal components. This includes, for example, not infinitely large amplification of operational amplifiers, injection of charges from analog switches, thermal noise, flicker noise, cross modulation of digital circuit components due to substrate effects, etc. Due to these interference sources, the resolution of a real modulator is typically limited to about 15 bits. There are a number of attempts to improve non-ideal components. Using fully differential analog circuits, compensated for integrator gain, complex phase generation, etc. significant improvements can be achieved. To make current class 1 and higher meters, a resolution of more than 17 bits is required, i.e. for this, input noise and input bias voltage must be in the microvolt range. To do this, usually use complex filters of a higher order for modulators of sigma-delta of a higher order. This leads in the normal case to the fact that significantly increased hardware requirements for high-precision sigma-delta modulators. In the embodiment according to the invention, such measures can be waived.

FIG. 3 shows an augmented version of a power measurement device. It uses increased accuracy with a stabilizer with a DC amplifier of the modulator-demodulator type, with the input sign of the second sigma-delta 8ΌΜ2 modulator and the output signal simultaneously modulated by a low-frequency rectangular function. Modulation is carried out using an exclusive OR function circuit with an input frequency £ _c and output signals 8-1, 8Ό2 of both modulators. Due to this, the offset voltage Wo2 of the modulator 8ΌΜ2 during one period of the signal £ _s is considered up, for example, positively in the digital integrator, while in the other part of the period it is integrated with a negative sign. With an exact symmetry of the clock period £ _c , which is easily achieved with the help of digital dividers, offsets are very effectively suppressed. Due to this, it is possible to significantly improve the accuracy of the circuit with several additional logic circuits in terms of bias and noise.

Considering that it is advisable to make the analog circuit as simple as possible to reduce the effects of cross-modulation and substrate noise, the following modification is proposed. The power measurement unit of FIG. 4 is distinguished by the conversion of analog modulation 20. Replacing the control inputs in the input switch 8-2 by two digital multiplexers 22a, 22b instead of the cross-linked analog switches 20a 206 reduces the analog error that may occur during switching. In this case, by changing the control phases P1 and P2 of the input switches 22a, 22b in the integrator with switched capacitors, the polarity of the input signal is inverted. Due to this, a further increase in the accuracy of the circuit is achieved without complicating the hardware.

The result of the invention is a very simple circuit that requires only two basic blocks of a conventional sigma-delta modulator and very simple digital filters (reversible counter).

Claims (13)

1. A multiplication circuit for a power or energy measuring device (P, A, 30, 40), containing (a) a first sigma-delta converter (8ΌΜ1; 10), to the input of which a first measured analog signal (9) (and (1 )), and its output controls the device (20; 20a, 20b, 20c, 206; 21T, 21b, 22a, 22b) of multiplication, while (b) the second measured signal (19) is supplied to the multiplication device (20) (ί ( ΐ)), and (c) the output of the multiplication device (20) is connected to the second sigma-delta converter (8ΌΜ2; 30), at the output of which an output signal is generated (p (1)), which represents the product of the first and second analog signals (and (1), ί (ΐ)), characterized in that (6) one digital inverting stage (50a, 50b) is located before the multiplication device (20) and, accordingly, after the second sigma-delta converter (30) which are synchronously controlled at a low frequency (£ _s ), with (e) the operating frequency of the transducers (10, 30) the sigma-delta selected in the MHz band, the frequencies of the analog AC signals (£ _and , 1]) selected in the range 20 - 1000 Hz, and the switching frequency of the digital inverting stages is less than 10 Hz so that you can measure one signal (p (1)) to ensure operation of both converters (10, 30) and compensation sigmadelta their displacement from one frequency is much higher and accordingly a different frequency is clearly lower than the frequencies of the measured analog signals. 2. The circuit according to claim 1, characterized in that (a) the effective value of the first signal (and (1)) is less than a variable AC signal, in particular, a signal representing the mains voltage (in _e12 (1)), and (b ) the effective value of the second signal (ί (ΐ)) is much stronger than the changing AC signal, in particular, the signal representing the mains current (ί _{Ν (! 1ζ} (ΐ)). 3. The circuit according to claim 2, characterized in that the network voltage and network current are measured from a level of 110 V, 220 V or 380 V. 4. A circuit according to any one of claims 1 to 3, characterized in that the output signal (p (1)) is supplied to an analog or digital integrator (40), in particular, a reversible counter, the counting steps of which are configured to read at least at least one period, preferably two or more periods of analog AC signals (and (1), ί (ΐ)), and reading the binary output signal of the second sigma-delta converter (30) without overflow, so that the output of the integrator (40) is continuous represents the work (ν (1)). performed by both analog signals. 5. The circuit according to any one of claims 1 to 4, characterized in that the first and second digital inverting stages (50a, 50b) are exclusive OR circuits. 6. A circuit according to any one of claims 1 to 5, characterized in that the multiplication device (20) has two outputs and (a) contains four analog switches (20a, 20b, 20c, 206) connected in a bridge circuit, with the bridge arm is the output, and the upper and accordingly lower end of the bridge are the first input of the multiplication device (20), and the second input of the multiplication device (20) is a digital input that simultaneously closes and simultaneously opens two corresponding analog switches (£ 20, 206; 20b, 20s ), while simultaneously closing or simultaneously continuously which can be opened analog switches are respectively one upper analog switch of one half bridge and one lower analog switch of the other half of the bridge, so that regardless of the output signal (u _x) of the first transducer (1 0) sigma-delta actuate analog switches and transmit a second analog signal (ί (ΐ)) in accordance with the switching position of the analog switches directly or with inverted polarity; or (b) has two multiplexers whose multiplex inputs are connected together and form the second input of the multiplication device (20), onto which the output signal of the first sigma-delta converter (10) is supplied, while the first input (21a, 21b) of the device (20) multiplication has two analog switches (22a, 22b), which, depending on the output signals of the multiplexers, pass either the second analog signal (ΐ (ΐ)) or the analog inverted second tax signal (-ΐ (ΐ)) as the output signal of the device (20) multiplication, and to both mules opposite frequency signals I & ί2, ί1), which are non-overlapping clock signals for controlling the analog sigma-delta converters (10, 30), made according to the circuit with switched capacitors, are constantly fed to the multiplexers at their multiplication inputs 7. The circuit according to any one of claims 1 to 6, characterized in that the sigmadelt transducers (30, 10), as first-order sigma-delta modulators, output proportional to the analog input signal (and (1), ± ΐ (ΐ) ) the current density in bits, in which the ratio of the level of the logical unit to the level of the logical zero is proportional to the instantaneous value of the input signal. 8. The circuit according to claim 5, characterized in that the low-frequency switching frequency (£ _s ) is significantly lower than the frequency (1 _and , I,) of the analog AC signals (and (1), ΐ (ΐ)), if the AC signals are used as input signals. 9. A method for measuring the instantaneous power value (ρ (ΐ)) in a measuring device, in particular, for the mains voltage and mains current, at which (a) the digital current is controlled in bits of high frequency (and _x ) by the density of both logical levels in proportion the first analog signal (and (1)), whose frequency is much lower than the current frequency in bits; (b) the first digital current in bits (and _x ) switches the sign or polarity (20) of the second analog signal (ΐ (ΐ)), whose frequency (|) coincides in order of magnitude with the frequency of the first analog signal to obtain a basic signal with a switchable with a high frequency polarity (and _y ), which is suitable for determining the multiplication signal (and ₂ ), characterized in that (c) the operating frequencies (D, 12) of the density control and switching (1 0, 20) are basically more frequencies (1 _and, |) analog signals by a factor of 1 0 ⁵ - 0 1 ^6, however, when an analog signal tinuous current, the operating frequencies (£ _1, 12) above 1 MHz. 10. The method according to claim 9, characterized in that the multiplication device (20) is a sign inverting device. 11. A method according to claim 9 or 10, characterized in that the base signal _(and) without analog-conversion using parallel output or product formation with respect to its low-frequency component is evaluated, in particular by the second converter (30) sigma-delta , which gives the output a multiplication signal (and ₂ = ρ (1)) 12. The method according to any one of claims 9 to 11, characterized in that the first analog signal is the measured voltage (and (1)), in particular, the voltage of the household network, and the second analog signal is the measured current (ΐ (ΐ)) of the indicated network if the product (and ₂ ) is determined as the signal of the instantaneous value of the power consumed from the network (ρ (ΐ)). 13. The method according to any one of claims 9 to 12, characterized in that the analog signals are analog AC signals.