CN1226968A - Sigma-delta multiplier circuit for power measurement equipment - Google Patents
Sigma-delta multiplier circuit for power measurement equipment Download PDFInfo
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- CN1226968A CN1226968A CN 97196868 CN97196868A CN1226968A CN 1226968 A CN1226968 A CN 1226968A CN 97196868 CN97196868 CN 97196868 CN 97196868 A CN97196868 A CN 97196868A CN 1226968 A CN1226968 A CN 1226968A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R21/00—Arrangements for measuring electric power or power factor
- G01R21/133—Arrangements for measuring electric power or power factor by using digital technique
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06J—HYBRID COMPUTING ARRANGEMENTS
- G06J1/00—Hybrid computing arrangements
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R22/00—Arrangements for measuring time integral of electric power or current, e.g. electricity meters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/261—Amplifier which being suitable for instrumentation applications
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Abstract
Power measurement equipment is used to calculate the momentary value of the power actually taken from a network in which both current and voltage are variable, the voltage to a lesser but perceptible extent, the current in a distinct manner, as its effective value substantially determines the power, i.e. if current of a certain intensity is taken from the network, power has been taken, whereas if the current is practically zero, no power has been taken from the network. A multiplier circuit is disclosed for power or energy measurement equipment (P, W, 30, 40). A first measured (9) analogue signal (u) is supplied to a first sigma-delta converter (SDM1;10) whose output controls a multiplier (20; 20a, 20b, 20c, 20d; 21a, 21b, 22a, 22b). A second measured (19) analogue signal (i) is supplied to the multiplier (20). The output of the multiplier (20) is supplied to a second sigma-delta converter (SDM2; 30) which generates at its output an output signal (p(t)) which represents the momentary value of the product of the first analogue signal by the second analogue signal (u, i), hence the power to be measured.
Description
Technical field of the present invention is a power-measuring device, can calculate the instantaneous value that in fact obtains power by it from electrical network, wherein the electric current of electrical network and voltage are variable, voltage is little but can perceive, electric current is obvious, because determine power with the effective value of electric current in fact, no matter be with certain intensity current drawn (having absorbed power) or electric current almost nil (not absorbed power).
The Sigma-Delta converter has been described in EP90313050.8, it also is described with power-measuring device relevantly in the document, but also having used (there is represented with 5) A/D converter (ADU) in described prior art, is disadvantageous aspect its cost in this device that produces with the multicompartment number.
Task of the present invention is, reduces the cost of this device and keeps its precision simultaneously or even improve its precision.This will realize with claim 1 or claim 10.In the case, the output terminal of a Sigma-Delta converter (or modulator) will be exported its bit stream, so that make the symbol of second simulating signal be proportional to the bit stream density ground conversion of first modulator (SDM) output signal on its polarity.This sign reversing is carried out by " multiplier ", but it is not the analog multiplier of common circuit engineering definition, but can constitute replacement form (a) or (b) according to claim 6.
In the case, when power is determined with its instantaneous value, the present invention can accomplish that the analog multiplier that is not used in electric current and voltage analog measuring-signal is good, do not have and the A/D converter of line output good, and do not have digital multiplier good as the consequence of abandoning these.
According to the first bit stream work with upper frequency of the method for claim 10, this bit stream is a digital bit stream.This bit stream has been modulated (a second) simulating signal and has been produced a fundamental signal Uy thus, and it is not only by first simulating signal, and is influenced by secondary signal, can satisfy prerequisite thus, determines a long-pending signal Uz with it.If determine this first simulating signal of Sigma-Delta modulator bit stream density be directly proportional with voltage selected and this second simulating signal in ground be directly proportional with electric current selected, obtain the power as long-pending signal thus, it occurs with the low frequency component evaluation of the fundamental signal of high frequency conversion polarity the time.
Above-mentioned be included in the conventional power measurement mechanism as " multiplication " computing of analog multiplier according to above-mentioned principle only be limited in symbol change or with ± 1 be multiplied by mutually, this just can reasonably realize with simple circuit engineering cost.Equally also can abandon using complicated digital multiplier, though it may not have the problem of analog multiplier side-play amount to be implemented, its circuit cost is very high and need many number of bits when reaching enough precision.
The input value of the 2nd Sigma-Delta transducer is thus corresponding to instantaneous power, and it is transformed into digital quantity by the effect by modulator and can be converted into the energy (KWh, so-called " merit ") of absorption by the up/down counter.Integrator can be a structure (claim 4) simulation or numeral, and preferably it is described up/down counter.
Be important to note that the scheme of suggestion not only can be used for the simulating signal (line voltage, power network current) of alternating voltage according to the present invention, and to can be used for having small frequency very even frequency be zero " alternating voltage ".Thereby this circuit also is suitable for d. c. voltage signal is multiplied each other each other, and need in the structure of converter, not use analog multiplier or A/D converter, this converter is represented value according to the digital sample that a sampling/maintenance assembly is provided at storage analog quantity in sampling/maintenance assembly.This back one assembly is expensive on circuit engineering just, so should avoid using it according to the present invention.
A kind of multiplication of symbol can be realized (claim 6 simply by the bridge circuit of four analog switches, first scheme), these analog switches control conducting across and cut out, so that the simulating signal of input does not transmit by low-down first pair of analog switch conducting resistance with changing, perhaps exchange two input leads and this signal inversion ground transmitted as such signal by another analog switch to low on-resistance, this signal by with-1 multiply each other.
The side-play amount of analog switch and non-linearly on circuit engineering, grasped well and can not bring any influence to circuit of the present invention.
Utilize the high level of precision that can obtain power-measuring device in a circuit according to the invention with rational cost.
The side-play amount that also can add a kind of chopper one amplifier type suppresses circuit, at this moment the inverter stages of two digital quantities is set at the front of sign inversion device and the back and synchronous connect (claim 5,9) of the 2nd Sigma-Delta modulator anti-phasely or noninvertingly.
Below, will the present invention will be described and replenish by a plurality of embodiment.
Fig. 1 is the circuit block diagram as the voltage/current multiplier of alternating voltage multiplier.Input signal a ' (t) and b ' also may be direct current signal (frequency be zero alternating voltage) (t).
Fig. 2 is the detailed circuit diagram of Fig. 1, and bottom is to be the analog switch (left side) of example and the non-overlapped pulse (right side) that is used for analog switch with switch 20a.
Fig. 2 a is the modulation signal waveform figure that measures in Fig. 1.
Fig. 3 is the circuit with digimigration amount corrector that uses two XOR gate 50a, 50b and 6Hz frequency f c.Be used for below pulse f1, the f2 of SC logical circuit and emending frequency fc be illustrated in.
Fig. 4 is a modification structures of " multiplier " 20, and it comes control character anti-phase by the bit stream density signal Ux of a Sigma-Delta converter 10, and wherein this modification form of implementation realizes with two multiplexer 21a, 21b, and they are by two frequency f
1, f
2(MHZ scope in) control, they also in the control chart 1 as the circuit of SC technology.And can use a kind of unified circuit scheme.
By 10,30, one analog modulator AM of two Sigma/Delta modulators, a clock signal generator and a pulse totalizer are formed according to the power-measuring circuit of Fig. 1, and they connect according to Fig. 1.The analog input signal U (t) that is proportional to measuring voltage converts a digital bit stream U to by first modulator 10
x(t).The modulator (AM) that is provided with an analog input end is by two signal controlling.Be to be proportional to the signal of current i (t) and be bit stream signal U in analog side in digital control side
x(t).This modulator is with symbol U
x(t) multiply each other with analog input signal.Thus, the output signal of this modulator is proportional to the long-pending of i (t) and U (t) on its mean value, because U
x(t) on its mean value corresponding to U (t).The output signal of this modulator then is input to the 2nd Sigma/Delta modulator 30.This output pulse current also is proportional to the long-pending of i (t) and U (t) on its weight thus.The pulse current U that on the 2nd Sigma/Delta modulator output terminal, produces
z(t) will be input to the input end that adds up of adder unit 40 (for example as digital up/down counter).The output signal of this totalizer is a low frequency bit stream, and it is equivalent to average power.By integration the high frequency quantization noise of modulator is suppressed significantly.
These two identical circuit units are made up of the synchronous Sigma/Delta modulator of single order.In addition to these two Sigma/Delta modulators almost without any need for additional circuit components.This is its advantage just.
A traditional single order Sigma/Delta modulator comprises an integrator, one 1 quantizer (comparer), output terminal, it is by with sample frequency FS sampling, and one 1 figure place analog converter, it makes+/-U
RefVoltage is sampled the symbol of signal corresponding to comparer.At each sampled point upper integral device input end signal X (t) is carried out integration with poor (error signal) of converter output end signal.For a sampling period, the symbol of difference is stored in the quantizer.When comparer output y (t) is logical one, with positive voltage+U
RefFeed back to the input end of integrator.Its pulse current of this feedback signal is proportional to input signal, because the error of integrator is adjusted to zero.As the signal of transform, the function of modulator can be described by following equation:
y(Z)=X(Z)+(1-Z
-1)×Q(Z)
Q in the formula (Z) is the quantization noise of modulator.The frequency spectrum that this equation is second is arranged in the following slightly high-frequency region of base band, therefore can reach by digital filtering easily for example to be suppressed by integrator.
The big advantage of Sigma/Delta modulator is its integrability in the traditional IC technology.Typical Sigma/Delta modulator utilization has the traditional IC scheme of switch one capacitance integrator.This is the most effective a kind of microelectronics method, because switch one electric capacity (SC) circuit easy high-quality as CMOS is manufactured in large quantity.
The principle of SC circuit be utilize electric charge between the capacitor transfer and commutate by analog switch.In the case, commutating frequency is selected like this, and promptly it is more much higher than the frequency of input signal.In the example of ammeter, the input signal of relative 50Hz of sample frequency or 60Hz is typically in the MHz scope.Analog switch in switch one condenser network is controlled (for example Fig. 2, below) by two opposite square-wave signals of non-overlapping copies phase place.The clock signal generator of this circuit is designed like this, and promptly the porch of each signal has sufficient distance and be not overlapping.Charge loss when this has just been avoided continuing conducting.During a phase place of clock pulse signal, a part of capacitor is connected on the voltage source and is charged to this voltage.During second phase place of clock pulse signal, be charged on the other capacitor by commentaries on classics by analog switch and operational amplifier electric charge.As a result of, output signal can only need capacitor, analog switch and the operational amplifier of different proportion by the mathematical operation between each input signal, as adding, subtract and multiplication, delay and the integration of fixed coefficient being described for this reason.For example, a high resistance measurement can replace approx by a little capacitor C S, and this little electric capacity carries out switch with switching frequency FS.Equivalent resistance is equivalent to 1/ (CsFs).When we are connected with the capacitor C int of its signal and a non-switch control or with the summing junction feedback ground of the electric capacity of an operational amplifier and a non-switch control, just can regulate time constant R*C=[Ciht/Fs*Cs by being somebody's turn to do " resistance "], it is only determined by the ratio and the sample frequency of electric capacity.This is a big advantage of switch one condenser network, is obtained because can very accurately make in the electric capacity ratio of traditional IC technology neutral line, and on the contrary, the absolute value of capacitor or resistance can not accurately be determined in conventional IC technology.Reason that why switch one capacitance technology is used in many high resolution converters principles that Here it is.
A kind of possible form of implementation of circuit of the present invention shown in Fig. 2.Typically, this class circuit makes differential mode fully on the simulated data path.For the purpose of simplifying the description, a single-ended SC circuit is only described here.This analog modulator represents that with four cross-coupled analog switch 20a to 20d they can make the polarity of input signal i (t) anti-phase.The input signal of the one Sigma/Delta modulator SDM1 converts output signal U x (t) to.If this logical signal is zero, then the output Uy (t) of this modulator=-i (t).If Ux (t)=1, then the output signal of modulator is corresponding to input signal Uy (t)=i (t).The circuit of each Sigma/Delta modulator is indicated in the frame of broken lines.SDM1 and SDM2 modulator utilize known automatic zero set (AZS) point SC technology with two differential input ends, they are by operational amplifier OA2 and OA1, input sample capacitor C1, reference value sampling capacitor C2, integrating condenser C3 and the various switch of being controlled by two nonoverlapping clock pulse signal f1 and f2 are formed.The symbol of the differential signal that is integrated between modulator input end and the DAC output terminal is determined by comparer K1 or K2 on a switch periods, and is stored in D one trigger on a clock period.By two with the comparer output stage formed of door by DAC be controlled at the reference voltage source that is integrated in the next sampling period (be+Vref or-Vref).Separate the output pulse current in this wise with door, i.e. instantaneous positive measurement power Uz (t) of output representative, and second the negative measurement power of output representative by SDM2 modulator 30 in addition.These two pulse currents will add up in a n position up/down counter.The pulse current W (t) that the output of the output terminal of this counter has an impulse density, it is corresponding to the mean value of active power:
The input of a Sigma/Delta modulator (for example U (t) or Uy (t)) is connected with the differential input signal of integrator.The reference value input end of integrator and DAC output terminal (+Vref or-Vref) by the conversion of public switch, this switch is connected to integrator and DAC.The SC integrator comprises auto zero compensation (automatic zero set (AZS)) part, and it can reduce the offset voltage and the low frequency noise of operational amplifier.This will realize by relevant dual sampling (CDS).Each sampling period is divided into two subcycles in CDS.Sample offset amount in first subcycle, and in second subcycle, from input signal, deduct side-play amount.Can realize inhibition thus effectively to technical inevitable offset voltage.
Sampling to side-play amount is realizing by the feedback switch between closure operation amplifier's inverting input and the output terminal during the phase place F1.Capacitor C1 and C2 will be charged to the offset voltage (VOS) of operational amplifier input end thus.Second utmost point of capacitor be charged on the one hand modulator positive input voltage Vin+ (k) (k is the sampling period sequence number that increases progressively) and in another electric capacity second utmost point be charged to no-voltage.During phase place F1, capacitor C3 separates with the operational amplifier input end, and integrator keeps formerly being transferred to the electric charge among the C3.
C1 discharges into negative input voltage Vn-(k) during phase place F2, and the right side of C1 approximately remains on the offset voltage current potential, because the feedback of operational amplifier input end by C3 remains unchanged.This means that during F2, electric charge (Vin (k) * C1) commentaries on classics that is stored among the capacitor C1 is charged on the C3, it and operational amplifier side-play amount have nothing to do.Simultaneously, electric charge+-Uref*C2 and side-play amount irrespectively change from C2 and be charged on the C3, and wherein relevant is the symbol of a last sampling period integrator output terminal.Therefore offset voltage does not influence the signal transmission from the integrator input end to output terminal.
Consider explanation just now, the electric charge of a part of signal and reference value input end is transmitted and is integrated to the output voltage that also then produces integrator among the capacitor C3 in each sampling period during phase place F2.Integrator output voltage Vint (K) is changing value Δ K when K week, after date integrate phase F2 finished, and can be written as following equation:
Δ(k)?=?Vint(k)-Vint(k-1)?=?[Vin(k)×(C1/C3)+SD(k-1)×U
Ref×(C2/C3)]，
SD in the formula (K-1)=sign[V
COM3(K-1)]=± 1, corresponding to the integrator output symbol during the marginal edge of the K-1 of phase place F2 F2 in the sampling period.
Comparer K1 and K2 be the detection comparator output symbol side by side, and the value when wherein each integrate phase F2 finishes only is used for the next cycle as feedback signal.Therefore be stored in the d type flip flop along last comparer output voltage sampling and with the symbol that engraves this moment F2 is marginal, produce SD (K) thus.On the implementation d type flip flop, comparer, and the sampling logical gate can be combined in the circuit.
The d type flip flop output terminal of storage flip-flop original state is determined in the sampling period symbol of DAC output source during the phase place F2.In Fig. 2 a, express the typical waveform of the modulator signal of a positive input voltage.D type flip flop output SD (t) is equivalent to the output signal of modulator.The substantial error that is produced by quantization noise appears in the zone of upper frequency, and it can be suppressed effectively by digital filter.By corresponding wave filter, on the Sigma/Delta modulator, can reach the resolution more than the 20Bit at present:
Fout(t)～(C1/C2)×(Fs/U
Ref)×Vin(t).
In actual applications, the precision of Sigma/Delta modulator is subjected to the restriction of imperfect assembly.It for example is: the non-infinitely great amplification coefficient of operational amplifier, the charge injection of analog switch, thermal noise, flicker noise, the crosstalking etc. of the digital circuit part by body effect.Because these error sources, typically, the resolution limit of an actual modulator is on 15Bit.Have a series of adjunct circuit, they can improve imperfect assembly.By the fully differential mimic channel, the integrator of amplification coefficient compensation, expensive phase generator etc. can be realized substantial improvement.In order to make the pulse current counter more than 1 grade, require resolution to be higher than 17Bit, in other words, import noise and input off-set voltage must be in the scope of μ V for this reason.Usually use higher expensive wave filter for higher Sigma/Delta modulator for this reason.This can cause usually, has raised hardware requirement significantly on high-precision Sigma/Delta modulator.In according to the embodiment of the present invention, can abandon using these measures.
The supplementary form of a kind of power-measuring device of expression among Fig. 3.It has used the degree of accuracy by the chopper voltage stabilizing to improve measure, and wherein the input end symbol of the 2nd Sigma/Delta modulator SDM2 and output signal are side by side modulated through a low frequency square wave function.This modulation is by incoming frequency fc and the output signal SD1 of an XOR gate with two modulators, and SD2 carries out.By this measure, in the one-period of signal fc the offset voltage Vos2 of modulator SDM2 in digital integrator by forward ground counting upwards, and in the second round part with negative symbolic integration.Under the accurately symmetrical situation of the sampling period fc that can realize easily by digital distributor, side-play amount is suppressed very effectively.Use several extra gates just can be by this measure in the degree of accuracy of improving circuit aspect side-play amount and the noise.
If consider that to make mimic channel simple as far as possible, reduce thus to crosstalk and the influence of substrate noise is significant, then recommend a kind of flexible program.The difference of the power-measuring device among Fig. 4 has been conversion analog modulator 20.The replacement of the control input end in the SDM2 input switch uses two interleaver 22a, 22b to replace cross-coupled analog switch 20a to 20d, and this has reduced the simulation error that may occur when switch transition.Can make the polarity of input signal anti-phase by the control phase F1 of input switch 22a, 22b in the SC integrator and the conversion of F2 in the case.Need not the further improvement that complicated hardware obtains the switch degree of accuracy thus.
Result of the present invention is, obtained a kind of very simple solution, and it only needs a kind of two elementary cells of traditional Sigma/Delta modulator and unusual simple numerical wave filter (up/down counter).
Claims (15)
1, the mlultiplying circuit that is used for power or energy measuring apparatus (P, W, 30,40), wherein:
(a) simulating signal of first measured (9) (U (t)) is imported into a Sigma-Delta converter (SDM1; 10), multiplier (20 of its output control; 20a, 20b, 20c, 20d; 21a, 21b, 22a, 22b);
(b) the simulating signal i of second measured (19) (t) is imported into multiplier (20);
(c) output of multiplier (20) is imported into the 2nd Sigma-Delta converter (SDM2; 30), provide an output signal (P (t)) on this converter output end, it represents first and second simulating signal (u, i) long-pending instantaneous value.
2, according to the circuit of claim 1, wherein
(a) first signal is the very little alternating signal of fluctuation on its effective value, especially represents line voltage (U
Netz(t)) signal;
(b) secondary signal is the obvious strong alternating signal of fluctuation on its effective value, especially represents power network current (i
Netz(t)) signal.
3, according to the circuit of claim 2,, on the standard of 220V or 380V line voltage and power network current are measured (9,19) wherein at 110V.
4, the circuit that one of requires according to aforesaid right, wherein output signal (P (t)) is imported in the integrator (40) of an analog or digital, especially in up/down counter, its counting stage can at least one, especially two and a plurality of alternate mode analog signal (u, i) binary output signal to the 2nd Sigma-Delta converter (30) does not have counting with overflowing in the cycle, so that the merit (W (t)) that on behalf of these two simulating signals, the output of integrator (40) make continuously.
5, the circuit that one of requires according to aforesaid right, first and second digital inverter stages (50a wherein, 50b), especially respectively be an XOR gate, be positioned in multiplier (20) front, and in the 2nd Sigma-Delta converter (30) back, these phase inverters are synchronously controlled by a low frequency (fc), so that the side-play amount in this multiplier is compensated for prolonged period of time.
6, according to the circuit of one of aforesaid right requirement, wherein multiplier (20) is constituted as:
(a) four analog switch (20a in a bridge circuit, 20b, 20c, 20d), its jackshaft branch road is that output terminal and last or following bridge end points are the first input ends of multiplier (20), and wherein second input end of multiplier (20) is a digital input end, and it always makes two analog switches (20a, 20d; 20b, 20c) conducting side by side and side by side shutoff; Wherein the analog switch of conducting simultaneously and shutoff simultaneously respectively is the last analog switch of a half-bridge and the following analog switch of another half-bridge, so that output signal (Ux) operation mould according to a Sigma-Delta converter (10) ' intend switch, and directly or anti-phasely transmit second simulating signal according to the on off state of analog switch
(ⅰ)：
(b) two multiplexer (21a, 21b), their multiplexer input end interconnects and constitutes second input end of multiplier (20), it is imported the output signal of a Sigma-Delta converter (10), wherein the first input end of multiplier (20) respectively has an analog switch (22a, 22b), they are according to multiplexer (21a, output signal 21b) or make second simulating signal (i) or make the simulation the second anti-phase simulating signal (i) pass through as the output signal of multiplier (20), and wherein on two input ends that the device signal that is re-used of two multiplexers is selected, dispose reverse frequency signal (f1, f2 regularly respectively; F2, f1), they are the non-overlapping clock pulse signals that are used to be configured in the analog switch control of the Sigma-Delta converter (10,30) in the SC circuit (switched-capacitor circuit).
7, the circuit that one of requires according to aforesaid right, wherein the Sigma-Delta converter (30,10) one of output and analog input signal (u on its output terminal, ± i) proportional bit stream density signal, the ratio of logical one level and logical zero level and input signal instantaneous value proportional (single order SD modulator) in this signal.
8, the circuit that one of requires according to aforesaid right, wherein drive Sigma-Delta modulator (10,30) first frequency (f1, f2) than alternate mode analog signal (u, frequency i) is much higher; And/or according to low frequency (fc) switching frequency of claim 5 be lower than significantly the alternate mode analog signal (u, frequency i) (fu, fi), as long as the words that alternating signal is used as input signal.
9, circuit according to Claim 8, wherein the Sigma-Delta modulator (10,30) driving efficient is in the MHZ scope, frequency (the fu of alternate mode analog signal, fi) in 20 to 1000Hz scopes, and digital inverter level (50a, switching frequency 50b) is lower than 10Hz, so as for measure instantaneous power (P (t)) with than the much higher frequency of the frequency of measured simulating signal and than the frequency of measured simulating signal obviously low frequency drive two Sigma-Delta transducers and compensate their side-play amount.
10, be used at a kind of measurement mechanism, measure the method for power instantaneous value (P (t)) in particular for the measurement mechanism of line voltage and power network current, in the method:
(a) a control high-frequency digital bit stream (Ux) makes the density of two logic level and first simulating signal (U (t)) proportional, and the frequency (fu) of this simulating signal (U (t)) is more much smaller than the frequency of bit stream;
(b) symbol or the polarity (10) of first digital bit stream (Ux) conversion second simulating signal (i (t)), the frequency of this second simulating signal (fi) is the order of magnitude of first simulating signal, so that obtain the fundamental signal (Uy) of a high frequency polar switching, it is applicable to determine (ZU) of long-pending signal.
11, according to the method for claim 10, wherein fundamental signal (Uy) does not need to come evaluation with AD conversion or (analog/digital) quadrature device with parallel output terminal with its low frequency component, especially by the 2nd Sigma-Delta modulator (30) evaluation, signal (Uz=P (t)) is amassed in this modulator output terminal output.
12, according to the method for claim 10 or 11, wherein first simulating signal is a voltage (u) to be measured, especially the line voltage of family expenses electrical network, and second simulating signal is the measured currents (i) of above-mentioned power supply grid, obtains the instantaneous value of power (P (t)) as long-pending signal (Uz) from electrical network so that determine.
13, according to the method for one of said method claim, wherein the driving frequency of Sigma-Delta modulator (10,30) (f1, f2) than the frequency of alternate mode analog signal (fu, fi) big by 10
5To 10
6Times, yet when using the analog DC signal, driving frequency is higher than 1MHZ.
14, according to the device or the method for one of aforesaid right requirement, wherein simulating signal is the simulation alternating signal.
15, according to the device or the method for one of aforesaid right requirement, wherein multiplier (20) is a sign inversion device.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE1996130605 DE19630605A1 (en) | 1996-07-29 | 1996-07-29 | Multiplication circuit for power measuring device |
| DE19630605.1 | 1996-07-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1226968A true CN1226968A (en) | 1999-08-25 |
| CN1213307C CN1213307C (en) | 2005-08-03 |
Family
ID=7801202
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 97196868 Expired - Fee Related CN1213307C (en) | 1996-07-29 | 1997-07-29 | Sigma-delta multiplier circuit for power measurement equipment |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0916096A1 (en) |
| CN (1) | CN1213307C (en) |
| DE (1) | DE19630605A1 (en) |
| EA (1) | EA001361B1 (en) |
| WO (1) | WO1998004926A1 (en) |
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| CN100362744C (en) * | 1999-08-04 | 2008-01-16 | 印芬龙科技股份有限公司 | Sigma-delta A/D converter |
| CN107340425A (en) * | 2017-06-30 | 2017-11-10 | 常州同惠电子股份有限公司 | It is used for the effective power measuring method and device of AC power based on analog multiplier |
| CN109990804A (en) * | 2019-04-03 | 2019-07-09 | 安徽见行科技有限公司 | The self-correcting positive circuit of sensor circuit temperature drift based on analog multiplier |
| CN111352606A (en) * | 2019-07-08 | 2020-06-30 | 神亚科技股份有限公司 | Multiplier device |
| CN111630400A (en) * | 2018-01-11 | 2020-09-04 | 汽车交通工程有限公司 | Method and device for monitoring power electronic components |
| CN113366325A (en) * | 2019-01-29 | 2021-09-07 | 森泰克有限公司 | Electric meter |
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| DE102006038031A1 (en) * | 2006-05-26 | 2007-11-29 | Rohde & Schwarz Gmbh & Co. Kg | Measuring device for measuring the power of a high frequency signal comprises a dither injection unit arranged between a detector and an analogue/digital converter for injecting a dither signal |
| US7528755B2 (en) | 2007-09-06 | 2009-05-05 | Infineon Technologies Ag | Sigma-delta modulator for operating sensors |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4224671A (en) * | 1977-07-30 | 1980-09-23 | Tokyo Shibaura Denki Kabushiki Kaisha | Arithmetic operation apparatus for an electronic watt-hour meter |
| JPS581388B2 (en) * | 1978-07-06 | 1983-01-11 | 株式会社東芝 | electricity meter |
| DE2846598A1 (en) * | 1978-10-26 | 1980-04-30 | Stepper & Co | TDM system to measure electrical power and energy - uses two pulsed logic units t- control voltage and current signal for device integration |
| JPS57146121U (en) * | 1981-03-06 | 1982-09-14 | ||
| DE3448182C2 (en) * | 1983-08-01 | 1988-09-29 | Robinton Products, Inc., Sunnyvale, Calif., Us | |
| FI90144C (en) * | 1986-02-04 | 1993-12-27 | Siemens Ag | Electronic electricity meter |
| WO1991003740A1 (en) * | 1989-09-07 | 1991-03-21 | Georgey Katrib | Electronic watt-hour meter |
| GB2239097B (en) * | 1989-12-18 | 1993-08-11 | Gen Electric Co Plc | Electrical power measuring devices |
| JP3080207B2 (en) * | 1993-01-06 | 2000-08-21 | 三菱電機株式会社 | Electronic watt-hour meter |
| DK0607714T3 (en) * | 1993-01-20 | 2001-12-10 | Schlumberger Ind Sa | Frequency modulated multi-stage circuit |
| DE69324229T2 (en) * | 1993-01-20 | 1999-09-30 | Schlumberger Ind Sa | Electricity meter with variable gain and with sigma-delta converter |
| GB2278247A (en) * | 1993-05-17 | 1994-11-23 | Nat Science Council | Chopper-stabilized sigma-delta converter |
| US5483238A (en) * | 1993-12-16 | 1996-01-09 | At&T Ipm Corp. | Data converter with gain scaling including dither |
| CH689471A5 (en) * | 1994-05-05 | 1999-04-30 | Landis & Gyr Tech Innovat | Summer for products of similar or different signals e.g. for electricity meter |
-
1996
- 1996-07-29 DE DE1996130605 patent/DE19630605A1/en not_active Ceased
-
1997
- 1997-07-29 EP EP97936570A patent/EP0916096A1/en not_active Withdrawn
- 1997-07-29 CN CN 97196868 patent/CN1213307C/en not_active Expired - Fee Related
- 1997-07-29 EA EA199900176A patent/EA001361B1/en not_active IP Right Cessation
- 1997-07-29 WO PCT/DE1997/001597 patent/WO1998004926A1/en not_active Application Discontinuation
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100362744C (en) * | 1999-08-04 | 2008-01-16 | 印芬龙科技股份有限公司 | Sigma-delta A/D converter |
| CN107340425A (en) * | 2017-06-30 | 2017-11-10 | 常州同惠电子股份有限公司 | It is used for the effective power measuring method and device of AC power based on analog multiplier |
| CN111630400A (en) * | 2018-01-11 | 2020-09-04 | 汽车交通工程有限公司 | Method and device for monitoring power electronic components |
| CN113366325A (en) * | 2019-01-29 | 2021-09-07 | 森泰克有限公司 | Electric meter |
| CN109990804A (en) * | 2019-04-03 | 2019-07-09 | 安徽见行科技有限公司 | The self-correcting positive circuit of sensor circuit temperature drift based on analog multiplier |
| CN109990804B (en) * | 2019-04-03 | 2021-06-29 | 安徽见行科技有限公司 | Self-correcting circuit of sensor circuit temperature drift based on analog multiplier |
| CN111352606A (en) * | 2019-07-08 | 2020-06-30 | 神亚科技股份有限公司 | Multiplier device |
Also Published As
| Publication number | Publication date |
|---|---|
| DE19630605A1 (en) | 1998-02-05 |
| WO1998004926A1 (en) | 1998-02-05 |
| EA001361B1 (en) | 2001-02-26 |
| EA199900176A1 (en) | 1999-08-26 |
| CN1213307C (en) | 2005-08-03 |
| EP0916096A1 (en) | 1999-05-19 |
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