DK143628B - ASYNCHRON DIGITAL DETECTOR - Google Patents

Description

(19) DENMARK

^ (12) SUBMISSION WRITING on 11 * 3628 B

DIRECTORATE OF THE PATENT AND TRADEMARKET SYSTEM

(21) Application No. 1896/72 (51) Int.CI.® H Oi L 1/00 (22) Date of filing ^ 9 * aPr · 1972 H 06 Q 7/00 (24) Race day 19 · aPr · 1972 (41) ) Aim. available Oct. 20 1972 (44) Presented l4. BeP · 1981 (86) International application no. ** (86) International filing day (85) Transfer day '(62) Master application no. ~

(30) Priority 19 · Apr. 1971, 134932, US

(71) Applicant MOTOROLA INC., Franklin Park, US.

(72) Inventor William V. Braun, US: Eugene J. Bruckert, US.

(74) Associate Patent Agent firm Magnue Jensens Eftf.

(54) Asynchronous digital detector.

The present invention relates to a detector as set forth in claim 1.

Such a detector, known from CH-PS 439,391, is used to recognize, in a signal sequence, a certain five-bit word consisting of the beginning or end of a message and which is to trigger a synchronization of the message receiving device D equipment. For this, any of the five bit words in the received signal sequence are read sequentially into a shift register controlled by a clock pulse synchronized to the signal sequence, ^ The synchronized clock pulse is derived by a signal sequence - unsynchronized clock generator by processing a synchronized pulse transmitted as well. The switch register has, in accordance with the word length, five steps, all connected to a coincidence link. This coupling examines the bits contained in the shift register and emits a pulse when the predetermined word occurs in the shift register.

This known detector operates with so-called synchronous sensing, where the received signal sequence is sensed with synchronized clock pulses, which always occur in the middle of the individual received bits.

Such a detector, due to the transmitted synchronization signals, requires a relatively large range of components on both the transmitter and receiver side and is also extremely noise sensitive, since a single wrong bit already causes an incorrect detection.

In certain communication systems, for example by mobile, portable and selectively calling systems, where binary words are used for selective calling by a receiver, the said component offering cannot be tolerated. In such systems, the addition of synchronization signals at the beginning and / or end of a desired binary word causes a delay in transmission which is also undesirable.

By a method known from German disclosure 1,252,727 for noise-safe reception of transmitted data, a signal sequence with a frequency above the bit rate of the signal sequence is sensed.

The binary values of a certain number of sensors are compared with the binary values of another number of subsequent scans, and a binary signal corresponding to the majority of all the binary values is output. There is thus a so-called majority logic, which prevents the error pulses contained in the signal sequence from being mistaken as information bits. This known method does not serve to determine whether a received signal sequence contains a predetermined binary word, nor does it allow for synchronization between the received message and a message processing circuit.

The object of the invention is to provide a detector of the kind which is capable of operating without transmitted synchronization signals.

This is achieved according to the invention in the embodiment of claim 1.

Due to the repeated scanning during a bit period, synchronization between the signal generating and sending device and the detector, respectively, can be avoided. The design provided allows, by appropriate selection of the binary word searched, so that it differs a certain minimum degree from other words in the signal sequence and from words obtained by cyclic offset, that the searched word can be recognized without word synchronization, even by itself. whether the correspondence between the contents of the shift register and the stored word is not complete.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will now be explained in more detail in connection with the drawing, in which: FIG. 1 is a block diagram of an asynchronous detector according to the invention; FIG. 2 is a block diagram of another embodiment of the detector; FIG. 3 is a graphical representation of a binary signal sequence; and FIG. 4 is a block diagram of another embodiment of one of FIG. 2 illustrates storage circuits.

The detectors shown in the drawing are binary detectors intended to detect a binary word in a signal sequence. A binary word consists of a predetermined sequence of binary digits or bits, each bit having a predetermined period length. The detectors shown are capable of detecting the desired binary word without the need for synchronization of the receiver to the bit periods.

In FIG. 3 (a) is shown a binary signal sequence detectable by those of FIG. 1 and 2. The transitions from one signal level to another indicate the length or duration of a bit period. One of two levels represents a binary 0 and the other a binary 1_. At (c) three bit periods with the same level are shown. Thus, the individual bits are not always separated by a level change.

In FIG. 1, signals from, for example, a receiver's discriminator and containing the desired binary word are applied to a low-pass filter 10. This filter cuts off all signal components over a certain frequency to eliminate unwanted high-frequency noise signals that could make detection difficult. The cut-off frequency of the filter is chosen equal to approx. half the sample frequency mentioned later. For example, the cut-off frequency of the low-pass filter 10 may be 200 Hz. The signals from the low-pass filter 10 are applied to a limiter 11 which amplifies and cuts signals having an amplitude different from 0. The signals at the output of the limiter 11 are thus bipolar signals, the signal levels being either equal to the limiter cut-off level or zero. The output signals of the limiter 11 can be considered as a result of binary signals such as that shown in FIG. 3 (a).

In connection with the detectors shown in the drawing, it is now assumed that the binary word consists of 23 bits. With 23 bits it is possible to use 178 different binary words that differ from each other and from cyclical variants of other words with at least 7 bits. This group of binary words can be a so-called subset of a cyclic code. Due to the large difference between the words and their cyclic variants, frame signals before or after a word are not necessary. Such a word also makes it possible to detect the desired word, although the correlation between the received and the correct word is less than 100%.

The binary signal sequence from constraint 11 is applied to a shift register 12, which is a multi-stage shift register. A portion 13a of a control circuit 13 is coupled to the shift register 12 and generates a plurality of first control pulses in each bit period, as indicated in FIG. 3 (b) used to activate switch register 12 so that the binary information is switched from each step to the next, and the binary signal supplied to the first step from the limiter 11 is exemplified. Thus, the binary signal coupled to the first step in the signal sequence is introduced in the first step by the first control pulse. In a preferred embodiment, the control circuit 13 produces four first control pulses in a bit period. Thus, each bit of signal sequence applied to the shift register 12 can be scanned four times. If the number of bits per Thus, the control circuit must generate first control pulses with a pulse frequency of 400 Hz.

The switch register 12 has four times as many steps as the number of bits in the desired word, i.e. 92 steps for a 23-bit word.

The FIG. 1 further comprises a memory register 14 with as many steps as the number of bits in the desired word. The binary signals in each of the switch register steps are applied to one input of a number of exclusive NOR gate circuits, hereinafter referred to as EX-NOR circuits 15. The number of EX-NOR circuits 15 is equal to the number of steps in the shift register. 12. Each stage of the storage register 14 is coupled to the second input of the EX-NOR circuit 15, so that the storage register 14 is coupled to the inputs of four of the circuits 15, the binary signals to four EX-NOR circuits 15 from the switch register 12. corresponds to the four binary signals from one bit.

A second portion 13b of the control circuit 13 produces different control pulses between each of the first control pulses. The other control pulses are applied to the memory register 14 and each cause bits in each of the memory register steps to be applied to the respective inputs of the EX-NOR circuits 15. If the signals are matched on the two inputs of a NOR circuit 15, the circuit will output a signal. . It should be noted that any circuit that can output an output signal in accordance with two input signals may replace the EX-NOR circuits 15. The output signals of the EX-Nor circuits are applied to a counter 16. This counter 16 is also applied to the other control signals so that the counter detects the number of signals from the EX-NOR circuits. If this number is greater than a predetermined percentage of the number of EXT-NOR circuits, the counter 16 gives a signal that the received word is recognized as desired. For example, 80% of the comparative circles may require compliance.

For example, the signal emitted by the counter can be used to activate a receiver's low frequency step.

It should be noted that the register 14 of FIG. 1 is shown with 2 steps, while register 12 has 8 steps. Of course, in the aforementioned example, where the word consists of 23 bits, the memory register 14 consists of 23 steps, and the shift register 12 consists of 92 steps.

It has been mentioned before that the desired binary word may be contained in a cyclic code. Furthermore, it is characteristic of the desired word that an upper limit exists for the number of level changes in the word. Thus, in a word of 23 bits, a maximum of 16 level changes can occur. With four scans in each bit period, accurate synchronization between transmitter and receiver is not necessary. This is because the probability of t 6 errors due to a scan in a wrong bit period or in the transition between two bits in the absence of synchronization is small compared to the number of errors needed for the received word to be rejected as incorrect . For example, being scanned at the beginning or end of a bit period, which is assumed to be the worst that can happen, - when only 16 level changes can take place - a maximum of 16 scans could be incorrect.

According to probability theory, only 50% of the transient scans will cause errors, but assuming said worst option, only 16 of 92 scans corresponding to 17 »4% will be incorrect. Thus, since the counter 16 gives a signal for, for example, 80% compliance, an additional 2.6% error, for example noise in the system, may occur before a correct word is rejected due to system failure.

If 50% of the transitional scans are incorrect, only 8.7% of all scans will be wrong. With an 80% approval limit, 11.3% errors can then be allowed from the system.

If only scanned once in each bit period, 16 errors on 23 scans could occur. The probable margin error is then 34.8%.

Three scans each bit period will be sufficient to allow accurate synchronization between transmitter and receiver, but said four scans allow few system errors other than errors due to lack of synchronization. Furthermore, the four scans reduce pr. bit period the number of rejections of the correct words per se.

FIG. 2 shows another embodiment in which the signals from the limiter 11 are applied to a gate circuit 25. First control pulses from a part 26a of a control circuit 26 are applied to the gate circuit 25 for a number of four in each bit period. The control pulses open the gate circuit 25 so that the binary signals in the binary signal sequence are coupled through the gate circuit to a switch register 27. This register comprises as switch register 12 92 steps when the binary word consists of 23 bits.

As in the embodiment described above, the shift register 27 is applied to the first control pulses.

Another portion 26b of the control circuit 26 generates other control pulses between each of the first. For example, 92 different control pulses can be generated for each of the first control pulses. The other control pulses are applied to the shift register 27 so that the binary signals are switched through the steps of the register. As the binary signals reach the last register stage, they are coupled through a gate circuit 30 which is also activated by the other control pulses to one input of an EX-NOR circuit 31. A 92 stage storage register 35 contains binary signals corresponding to the correct one. following binary signals in the predetermined binary word. Each group of four register steps corresponds to one bit.

The storage register 35 is applied to the other control pulses, whereby the binary signals are cyclically switched through the register, such as the signals in the switch register 27. The binary signal in the last step of the storage register is applied to the second input of the EX-NOR circuit 31. According to the EX-NOR circuit two inputs output a signal to a counter 36. The counter records the number of matches between the signals in the two registers 35 and 27 and outputs a counter signal for each match. The counter signal is applied to an AND circuit 37.

If a predetermined number of count signals is obtained, the counter will signal to all inputs on the AND circuit 37 so that an approval signal is output. Again, it can be assumed that 8Q? 4 compliance will elicit an approval signal. The signal from the AND circuit 37 is applied to a bistable multivibrator 38 which changes state when it receives an approval signal and outputs a signal to one input of an AND circuit 39. The second input of the AND circuit 39 is applied to the first control pulses. If the AND circuit 39 is applied to a first control pulse simultaneously with the occurrence of a signal from the multivibrator 38, the circuit 39 will output a signal thereon.

The first control pulses are further applied to the counter 36 and the multivibrator 38 so that these circuits are reset.

The signal from AND circuit 39 is applied to a controllable delay circuit 40 such as a monostable multivibrator. The delay circuit 40 will change state when such a signal is applied and remain in the new state for a predetermined period. In this mode, the multivibrator emits a control signal at its output 41 corresponding to the received word being accepted as being correct. The duration of the period during which the multivibrator 40 remains in the switched state is somewhat greater than is necessary to receive a following 23 bit binary word.

If this following word corresponds to the predetermined, monostable multivibrator 40 will again be activated and the control signal at output 41 is maintained.

The duration of the delay period of the multivibrator 40 may be selected such that the multivibrator remains in the switched period longer than necessary to receive two or three additional 23-bit binary words. Thereby, the control signal is maintained at output 41, even if one of these later binary words is lost.

FIG. 2 shows another shift register 140 which may be identical to register 35. This additional register 140 can be used to store another predetermined word which is compared to that received in shift register 27 by means of an EX-NOR circuit 141 which controls a counter 42, an AND circuit 43 »a bistable multivibrator 44, an AND circuit 45, and a monostable multivibrator 46. This multivibrator provides, by appropriate predetermined correspondence between the signals received in the shift register 27 and the signals stored in register 140, a control signal of the output 47-

For example, register 140 may contain 0 or 1 at all stages. The corresponding word can then be transmitted as a sign of the termination of the transmission, which is particularly convenient when the monostable multivibrator 40 is arranged to maintain the control signal for a predetermined period, even if the predetermined binary word is not repeated.

For example, the EX-NOR circuits 15 and 31 shown and mentioned may be replaced by EX-OR circuits. These will output signals when there is no match between the applied signals.

The number of steps in register 35 may be equal to the number of bits in the predetermined word, ie 23.

Then, between the control circuit 26 and the register 35, a circuit is inserted which causes every fourth of the other control pulses to be applied to the register 35, so that this changes only once, for every four times the register 27 changes.

With the selected word type, each word and cyclic variants will be determined by the first twelve bits. Thus, the last eleven bits can be calculated when the first twelve bits are known. In Fig. 4 is shown a shift register 50 which, taking advantage of this context, can replace those in Figs. 2 stores 35 and 140.

The switch register 50 contains twelve steps and is coupled to a parity circuit 51. The register 50 is applied to other control pulses from the circuit 26b which cause the binary signals to be switched through the register and the following bits are generated.

Using multiple scans per bit increases the sensitivity of the detector and decreases the number of erroneous rejections of a correct word. This is because failure to receive a bit, for example, due to a noise pulse or due to diminished signal strength that impedes proper reception of a bit, will only cause a reduction in the number of signals from the circuit or circuits to determine the correspondence of the signals in the two registers, but not recognition of an useless bit. Of course, the number of matches may be so small that the word cannot be recognized, but in such cases the whole signal will usually be so distorted that the transmission is worthless.

The detectors shown are asynchronous and thus do not require synchronization between transmitter and receiver. Also, frame synchronization is not required. With proper selection of scans for each bit and the number of matches relative to the number of scans, accurate synchronization between bit occurrence and detection is not necessary. The use of multiple scans per bit further reduces the risk of incorrect rejection of a correct word and increases the sensitivity of the detector. Furthermore, the use of multiple scans of the received signal and correlation with a stored word means that the two-step process with recognition of bits and the subsequent correlation of these is reduced to a one-step process.

Claims (3)

10 143828 Patent Claims. An asynchronous digital detector for detecting a predetermined binary word in a signal sequence of bits each having a predetermined length, and comprising a non-synchronized control circuit for generating first control pulses at a greater frequency than the signal frequency bit frequency, a shift register which influenced by control pulses receiving and switching bits in the signal sequence, and a comparative circuit for determining the correspondence between the contents of the shift register and the predetermined word, characterized in that the shift register (12,27) is controlled immediately by unsynchronized control pulses from the control circuit (13,13a , 26.26a) that the number of steps in the shift register is equal to the product of the number of bits in the word to be detected and the number of first control pulses in each bit period that the comparative circuit consists of at least one gate circuit (15,31,141) and one associated with this ((16, 36.42) counts that the gate circuit is applied partly to values from switching the register, and partly values from a storage circuit (14,35,140) containing a word corresponding to the predetermined word, such that the counter state is an expression of correspondence between the contents of the shift register and the contents of the storage circuit, and that the counter obtains a predetermined degree of compliance gives a signal. Detector according to claim 1, characterized in that the storage circuit (14,35,140) comprises a number of bits corresponding to the predetermined word corresponding to the storage stage. Detector according to claim 2, characterized in that the comparative circuit comprises one number of switch register stages (15) corresponding to the number of gate circuits (15), each gate having an input connected to a step in the shift register.