DE2217392A1 - Asynchronous detector for detecting binary words in a signal sequence - Google Patents

Description

DIPL.-ING. LEO FLEUCHAUS DR.-ING. HANSLEYH

Münch «n7 !, H. April 1972

Melcbiorstrasse, 42

Our reference: MO18P-792

Motorola, Inc. 9401 West Grand Avenue Franklin Park , Illinois V.St.A.

Asynchronous detector for detecting binary words in a signal sequence

The invention relates to an asynchronous detector for determining certain binary words in a signal sequence, which includes bits with a certain duration.

Digital systems used to detect digital information and in particular binary words are used in a signal sequence, usually work according to a method with two method steps. The first step involves recognizing the binary Bits, whereby it is determined which of the two binary levels the bit represents. In the second process step all bits are recorded together and compared with the desired binary word. A two-stage detector and decoder has, since it must first recognize every bit of the desired word, a relatively high proportion of false alarms and a low one

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Sensitivity. Therefore it is possible that the detector-decoder combination responds to a binary word, that is different from the desired binary word. However, it can also happen that the detector-decoder combination is even in the presence of the correct binary word does not respond. Therefore, a non-system noise is often the cause of an incorrect one Functionality.

Since the bits of a binary word have a certain duration, the system clock must be correlated to a very high degree be. This means that the sender and receiver of a system must be synchronized in order to get the bits right ascertain. In addition, in order to recognize and identify the entire desired binary word, the word must also be synchronized as a whole. The word synchronization requires the transmission of appropriate synchronization signals before the beginning and / or at the end of the desired binary word.

With certain communication systems, e.g. with mobile, portable or selective calling communication systems, where binary words are used to selectively call a recipient, long delays can occur in the transmission or receiving messages will not be tolerated. However, in such systems, the insertion of Synchronization signals at the beginning and / or end of a desired binary word to the transmitter and receiver synchronize, a long delay for the transmission and reception of the message and is therefore undesirable.

The invention is based on the object of creating an asynchronous digital detector which does not require any time for system synchronization before detection. In particular

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the digital detector should have a high sensitivity and a very low error rate. The Detection process run in one process step.

According to the invention, this object is achieved in that The following components are available: A clock, which a plurality of first clock pulses during the duration of a Bit period supplies, a sample and register storage device coupled to the clock generator with a plurality of stages for storing binary signals stored in series, the sampling and register storage means being based on the responds to the first clock pulse in order to sample the signal of the signal sequence applied on the input side and the signal corresponding to this signal to store binary signal, a data memory that contains a binary corresponding to the particular binary word Word supplies and a comparison device which is coupled to the sample and register storage device to to compare the binary word with the sampled binary signal and a comparison signal as a function of one to generate a predeterminable correlation between the binary signals and the binary word.

Further features and advantages of the invention are the subject of subclaims.

A particularly advantageous implementation of the invention is an asynchronous detector for detecting a binary word within a signal sequence, this signal sequence and the binary word ₍ comprising bits of a specific duration. The detector contains a clock generator that generates a plurality of first clock pulses during the duration of a The signal sequence is applied to a first shift register which shifts the contents of the stages of the shift register further depending on the respective first clock pulse.

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the signal sequence applied on the side, the binary signals are stored in the first stage of the shift register. There is also a second shift register in which a binary word is stored which corresponds to the binary word to be recognized. A comparison device is coupled to the first and second shift register and operates as a function of a second clock pulse which is generated between the first clock pulses. This comparison device compares the content of the first and second shift register. If a certain number of correlations occur between the signals of the first and second shift register, the comparison device supplies a detection signal which indicates that the correct binary word has been determined. In a preferred embodiment, a correlation of about 80 % is required. The multiple sampling within the time period of a bit period eliminates the need for system synchronization, reduces the error or false alarm rate and improves the system sensitivity.

In order to prevent the detection of an incorrect word, the desired binary words are selected in such a way that that they are each different from one another, the cyclical differences of the binary words being a certain Should not fall below the size. This makes it possible to use the detector system without the need for word synchronization to operate.

Further advantages and features of the invention emerge from the following description of exemplary embodiments Hand of the drawing and the claims. Show it:

1 shows a block diagram of an asynchronous detector according to the invention;

- ⁴ - Fig. 2

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Fig. 2 is a block diagram of a second embodiment an asynchronous detector according to the invention;

Fig. 3 shows a binary signal sequence, as well as the first from Clock generated clock pulses;

FIG. 4 shows the block diagram of a further embodiment of a memory circuit according to FIG. 2.

The detectors shown in FIGS. 1 and 2 operate as binary detectors and can detect a binary word in a signal sequence. A binary word consists of a specific sequence of binary digits or bits, with each bit having a specific duration. The detectors can determine the desired binary word without the need to synchronize the receiver to the clock of the bit period. FIG. 3a shows a binary signal sequence which can be scanned by the detectors according to FIGS. 1 and 2. The transitions from one level to the other show the length of a bit period and simultaneously identify a binary 1 and a binary 0. Each transition marks the end of a bit period and the beginning of the next bit period. One level denotes a binary 0, while the other level denotes a binary 1. 3 shows three bit periods without transitions and denoted by c _{} in} order to show that a transition is not absolutely necessary for the start and end of a bit period. Although FIG. 3 a shows a sequence of binary 1 and 2 which can be viewed as a binary signal sequence, this does not mean that the signal sequence represents a specific binary word which can be recognized by the detectors 1 and 2. Of course, however, the specific sequence of bits shown in FIG. 3a can also be a binary word in the special case.

Referring to Fig. 1, signals such as those from a discriminator

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aine receiver generates signals that have the desired binary Word contained, applied to the detector via a low-pass filter 10. The low-pass filter 10 over-attenuates all signals a certain frequency to eliminate unwanted high frequency noise signals that prevent the detection of the certain binary word can affect. The cutoff frequency of the filter is selected to be approximately corresponds to half the sampling frequency. The sampling frequency will be discussed in more detail below. With a preferred Embodiment is the cutoff frequency of the low-pass filter

200 Hz. The signals transmitted via the low-pass filter 10 are fed to a limiter 11, which is controlled by the Signals deviating from amplitude 0 are amplified and limited. The signals appearing at the limiter on the output side then represent the binary signals, i.e. that these signals either have the amplitude 0 or one through the limiter have a fixed signal level. These output-side signals of the limiter 11 can be used as a binary Signal sequence can be considered as shown in FIG. 3a.

For the special embodiment of the binary word which is recognized by the detectors according to FIGS 23 bits are provided. 178 different binary words with a 23-bit sequence are possible, each of the 178 binary words and the associated cyclical change in the bit sequence by at least 7 binary bits from any other of the 178 binary words or their cyclic bit sequence is different. This group of binary words will also often referred to as the cyclic code participant group. Each word would then be within that group of participants represent an element. Because of the big difference between the individual words and the individual With cyclic bit sequences, word synchronization is not required either at the beginning or at the end of the word.

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Such a binary word enables the detector to provide a recognition signal in the event of a correlation between the received word and the searched word of less than 100 I.

The binary signal sequence according to FIG. 3a is used by the limiter according to FIG. 1 applied to a shift register 12, which as multi-stage shift register is formed. A clock generator 13 has a part 13a with the shift register is coupled and delivered a plurality of first clock pulses according to FIG. 3b within the duration of a bit period The first clock pulses cause the binary signal of the respective stage of the shift register 12 in the next Stage is shifted, making it possible to use the binary signal applied to the first stage from the limiter to feel. The binary signal coupled to the first stage becomes the signal sequence when it occurs first Clock pulse stored in the first stage. In a preferred embodiment of the clock four first clock pulses are supplied by the clock generator part 13a within the duration of one bit period. Based on these four first clock pulses can be the binary signal applied to the shift register 12 for the duration of one bit period scanned four times. If 100 bits per second are applied to the shift register, the clock part must 13a generate 400 pulses per second, so that the sampling takes place with a sampling frequency of 400 Hz.

The shift register 12 must contain four times the number of stages as the number of bits of the desired word, in order to be able to include all the sampled signals in the word. Thus, the shift register 12 comprises 92 stages if a Word with 23 bits is used. When the 93rd binary signal is stored, the first scanned binary Signal from the last stage of the shift register 12

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pushed and gets lost.

The detector according to FIG. 1 also includes a data memory 14, which has as many levels as the desired binary word bits. The binary in each stage of the shift register 12 stored signal is fed to an input of a series of exclusive NOR gates 15 according to FIG. The number of NOR gates corresponds to the number of stages in the shift register 12. Each stage of the data memory 14 is connected to a second input of four each of the exclusive NOR gates 15. The data store 14 is connected to one input of four of the exclusive NOR gates 15, since the binary ones, to these four exclusive NOR gate from the shift register 12 coupled signals, the four binary signals of a bit in the desired should correspond to binary word.

The clock generator 13 has a clock generator part 13b that generates second clock pulses between the first clock pulses lie. These second clock pulses are applied to the data memory 14 and cause the bits of the individual stages of the data memory 14 are transmitted to the assigned inputs of the exclusive NOR gates 15. When the two Input signals for the exclusive NOR gates 15 correspond to one another, the one input signal from one stage of the shift register 12, and the other input signal is supplied from one stage of the data memory 14, then this special exclusive NOR gate 15 becomes effective and provides an output signal. Instead of the exclusive NOR gate any logic circuit can be used which provides an output signal in dependence on the match which supplies both signals applied to the inputs. Logical circuits used to carry out this operational function usually used are exclusive

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OR and exclusive NOR circuits. The output-side signal of the individual exclusive NOR gates is fed to a counter 16 at which the second clock pulses from the clock generator part 13b are also effective. These clock pulses cause the number of signals applied by the exclusive NOR gates to be counted. If the number of these signals exceeds a certain percentage of the total number of possible signals applied from the exclusive NOR gates, the counter 16 generates a detection signal indicating that the desired binary word has been received. In a preferred embodiment, about 80 % of the exclusive NOR gate signals must be fed to the counter 16 so that it emits the identification signal. Although the data memory 14 according to FIG. 1 consists of two stages, and the shift register 12 is shown consisting of eight stages, this is not of any restrictive significance Data memory 14 is provided. Although not necessary, the data memory 14 can also have 92 stages or 4 stages for each bit of the desired binary word, each stage being connected to a second input of an exclusive NOR gate 15.

As already mentioned above, the desired binary words from a group of participants can be a cyclic Codes exist. Another characteristic selection for the desired binary word can also be that a Upper limit for the maximum number of level changes or level jumps from one binary level to the other binary Level is determined that can occur for a specific word. In the case of a 23-bit word, can a maximum number of 16 level jumps can be provided if four samples are taken during the duration of a bit period exact synchronization of the transmitter

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and receiver clock not necessary. This is because the likelihood of failure due to the Sampling for the duration of a wrong bit period or when the interval jump between two bits for the case the lack of exact synchronization is very small compared to the number of errors involved in the display of an incorrect word are necessary. If, for example, a sample is taken at the beginning or at the end of a bit word becomes, which corresponds to the worst case, if only 16 interval jumps occur, then a maximum of all can 16 samples contain incorrect samples.

Although only 50% of the sampled level jumps would be wrong due to the probability theory, the most unfavorable situation should be used as a basis for the consideration, for example. With 16 incorrect level jumps, an error rate of 17.4 % results for 22 samples. Since a correlation failure only occurs with an error rate of 20 % and more , an additional 2.6% error rate can occur due to the system, e.g. due to noise, before the correct binary word is not recognized. The mean level jump error rate, however, is 8.7 I if 50 \ of the level jumps are incorrect, so that an error rate of 11.3 % is still available for system-specific errors, such as system noise. The previously mentioned error reserve of 2.6 % is no longer sufficient for system-specific influences such as noise, but the error reserve of 11.3 % is fully sufficient.

If only a single sample were to take place during the duration of each bit, there would be the possibility of 16 erroneous level jumps out of 23 samples in the worst case. This corresponds to an error rate of 69.6 %. However, if you have the middle level

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If the jump error rate is considered instead of the worst case, the result is an error rate of 34.8 %. This is above the maximum correlation error that is permitted in such a system.

Although the mean error rate at three samples per bit period would indicate that three samples per bit for a 23-bit word is sufficient to dispense with an exact synchronization between the transmitter and the receiver to be able to show that four samples per bit period is a sufficiently small, average level jump error rate results, so that further system errors, when they add up to the synchronization error, the detection not prevent a correct or the desired word. Furthermore, by using four samples per Bit period, the triggering of an alarm due to an error rate is further reduced in the desired manner. This alarm failure rate is defined as the ratio of the system's response to wrong or erroneous words.

In Fig. 2 a further embodiment of an asynchronous detector according to the invention is shown. To the low-pass filter 10, which corresponds to the low-pass filter 10 according to FIG. 1, the signal sequence is coupled. Output side a limiter designed according to FIG. 1 is connected to the low-pass filter and produces a binary signal sequence according to 3a supplies the gate 25 in series. A clock generator 26 having a first clock generator part 26 a is connected to the gate 25 connected and generates four first clock pulses during the duration of a bit period corresponding to the first clock part 13a according to FIG. 1. The clock pulses are shown in FIG. 3b.

Each clock pulse applied to gate 25 causes the

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binary signal of the signal sequence via the gate to the shift register 27 is created. This shift register 27 is constructed as a multi-stage shift register corresponding to the embodiment of the shift register 12 according to FIG. For the preferred embodiment includes the desired or certain binary word 23 binary bits, so that 92 stages are provided for the shift register 27. The first clock pulses from the clock part 26a are also applied to the shift register 27 and cause the binary signals of the individual levels can be moved to the next level. In this way, the binary can be sent to the first stage of the shift register from the gate 25 applied signal are sampled. That divided into groups and applied to the first stage of the shift register 27 binary signal of the signal sequence is dependent on the first Clock pulses, as mentioned, fed into the shift register in series. Assume that all 23 binary bits are fed into the shift register 27 in a particular binary word, then each group contains four stages in shift register 27, four binary signals corresponding to a binary bit in the particular binary word.

The clock generator 26 further has a clock generator part 26b which generates a second plurality of second clock pulses, which occur between two first clock pulses. According to the preferred embodiment, 92 second clock pulses generated, each between «4 ·« -first Clock pulses occur. These second clock pulses are also applied to the shift register 27 and cause that the binary signals stored in the shift register from the last stage via the gate 25 to the first stage are shifted back until the entire word is shifted once in a circle through the shift register 27. Any binary Signal that appears in the last stage of the shift register is passed through a gate 30, which is also used by the second

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Clock pulses is excited to one input of an exclusive NOR gate 31 is applied. It is also a second shift register 35 is provided, which can also comprise 92 stages. This shift register 35 contains binary signals that correspond in the correct sequence to the particular binary word. Each contains a group of four stages of the shift register 35 four binary signals corresponding to one bit of the particular one or desired binary word.

The second clock pulses of the clock generator part 26b are also applied to the shift register 35 and have the effect that the binary signals in the shift register 35 are shifted once in a circle from the output to the input in accordance with the shift register 27. The binary signal stored in the last stage of the shift register 35 is transmitted to the second input of the exclusive NOR gate 31. When the two inputs of the exclusive NOR gate 31, ie the binary signal from the shift register 35 and the binary signal from the shift register 27, correspond to one another, an output signal is transmitted from the exclusive NOR gate 31 to a counter 36. This counter 36 counts the number of correlations between the signals of the shift registers 35 and 2 7 and supplies a count signal at each count. This count signal is transmitted to an AND gate 37. After a certain number of counts, each input of the AND gate 37 has a count signal applied to it, so that an AND signal is then available on the output side at the AND gate. If, according to the preferred embodiment, about 80 % of the binary signals in the shift register 35 and in the shift register correspond to one another, this AND signal is triggered by the counting signals applied to the AND gate 37 by the counter 36. This AND signal is applied to a flip-flop 38, which switches its state accordingly and an output

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signal to one input of a further AND gate 39 supplies. This further AND gate 39 is at the second input acted upon with a first clock pulse from the clock generator part 26a in such a way that when a first Clock pulse, as well as the signal supplied by the flip-flop 39, the AND gate 39 emits an AND signal. The first to that AND gate 39 applied clock pulse is also applied to the counter 36 and the flip-flop 38 to use them for the next Prepare for counting.

The AND signal from AND gate 39 is applied to a resettable timer 40, which is a resettable monostable Multivibrator can be constructed. This monostable multivibrator 40 can switch from the first to the second switching state are switched and remains in the second switching state for a certain period of time before it automatically switches back. In the second switching state, the multivibrator 40 generates a detection signal that is sent to the output terminal 41 Available. This recognition signal indicates that the correct binary word has been received. After a certain For a period of time, the multivibrator falls back into its first switching state and thus also switches off the detection signal. The length of time for which the monostable multivibrator 40 remains in the second switching state is slightly longer than the time required to to receive a subsequently transmitted binary word with 23 bits. If the following binary word with 23 bits again corresponds to the particular binary word, the monostable multivibrator 40 is again excited so that the Detection signal at output 41 is maintained. The time constant of the mcnostable multivibrator 40 can also be set so that it remains in the second switching state for a period of time that is slightly greater than that Is the time it takes to receive two or three consecutive

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following binary words with 23 bits is required. With this setting of the time constant it is possible that the detection signal is maintained even if there is a fade in the RF signal and thereby the next word cannot be recognized. In this application, compensation is provided by the detector made, which can also be referred to as shrinkage compensation.

The detector according to FIG. 2 also includes a further second shift register 140, which can be constructed in the same way as the shift register 35 and is used to store further words to be recognized. The clock part 26b is connected to the shift register 140 and operates it in the same way as the shift register 35 in response to the second clock pulses. An exclusive NOR gate 141 responds to the signals applied from the shift register 140 as well as from the exclusive NOR gate 30 corresponding to the exclusive NOR gate 31 to generate an output signal which is fed to a counter 42. This counter 42 counts the number of NOR signals or the matches at the gate input and triggers counting signals which are fed to an AND gate 43. When the desired number of matches occurs, which, for example, has a correlation of 80 « _o i ₅ t, the AND gate 43 generates an AND signal which switches a downstream flip-flop to another switching state and the output signal emitted by the flip-flop supplies an AND gate. The AND gate 45 operates in the same way as the AND gate 39 and delivers an AND signal at its output on the next second clock pulse from the clock generator 26. This AND signal triggers a monostable multivibrator 46, which emits a detection signal via its output terminal 47.

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In the preferred embodiment, the second shift register 40 comprise 12 levels, all of which contain either a binary 0 or a binary 1. The detector speaks either to the receipt of all binary 0s or all binary 1s, depending on what is stored in the shift register is to provide a positive switch-off feature by switching back the monostable multivibrator 40. So that can the transmitted message will be terminated at a certain point in time, so that the monostable multivibrator 40 does not have to be maintained for the entire period of time. When this signal is used is used to enable the transmission of LF signals in a receiver, this is a positive switch-off feature particularly desirable.

The number of shift registers such as shift registers 140 and 140 may vary according to the number of different words to be determined are chosen. However, these shift registers can also be of advantage for multiple detection of the same word. This can be done by using the same word after having shifted it a few bits in position is fed into a second or third shift register. Recognizing this shifted form of the desired word occurs between the first and second reception of the desired word. With that it is possible to obtain a greater number of detections during a given period of time, which is the time constant of the monostable Multi-vibrators 40 and 46 can be reduced.

Although the embodiment according to FIG. 2 does not have NOR gates 31 is used, exclusive OR gates can also be used in their place. An exclusive OR gate delivers a Output signal in the absence of corresponding signals from the last stage of the shift registers 35 and 27. The counter 36

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then also supplies counting signals depending on the lack of a correlation between the binary signals in the shift register 35 and in the shift register 27. The AND gate 37 supplies an AND signal in this case if the number of counting signals shows a correlation between the binary signals in the shift registers 35 and 27 show less than 20 % . In this case, the recognition signal at terminal 41 indicates that a wrong word, as opposed to a correct word, has been received and recognized.

The circuit of Figure 2 can be further modified by providing the shift register 35 with a number of stages corresponding to the number of bits in the particular binary word. In the preferred embodiment this would be 23 stages. A divider stage with the ratio 4 to 1 is connected between the shift register 35 and the clock generator part 26b, so that the number of second clock pulses applied to the shift register 35 is reduced by the division factor 4. Thus every fourth of the second clock pulses would be applied to the shift register 35 from the clock generator part 26b. As a result, the content of the shift register 35 shifts only once every four shifts of the content in the shift register 27. Each _{bit stored in binary t} in the shift register 35 is compared four times with four sampled binary signals in the shift register 27.

Another characteristic of the desired binary word with 23 bits and some fine cyclic variation exists in that the last 11 bits of the word are determined by the first 12 bits and their sequence. In other words that means, if the first 12 bits are determined, you can

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the following 11 bits are derived from it. In Fig. 4, a shift register is shown, the corresponding works according to this principle and can be used instead of the shift registers 35 and 40. The shift register 50 consists of 12 stages and a parity circuit 51, which with certain stages of the shift register 50 is connected and is used to generate the last 11 bits. The pulses from the clock part 26b are on the shift register 50 is applied in the same way as they were fed to the shift register 35 and cause shifting the bits from one level to the next, with the simultaneous generation of the next bit. The last stage bit can be asserted through the exclusive NOR gate 31 as explained above.

Scanning with multiple samples increases the sensitivity of the detector, while the alarm error rate is increased is decreased. This arises due to the fact that errors occur when receiving a binary bit like them can be triggered by noise impulses or due to reduced signal strength, only the number of matches decrease, as opposed to detecting a wrong bit. Although the decrease in the number of Correspondence between a certain or desired word and the scanned signal means recognizing one Word can prevent this usually only occurs when the signal is so weak that the following received message could no longer be clearly understood.

From the foregoing it can be seen that an asynchronous digital detector can be created that does not waste time needed to synchronize the transmitted and received signal prior to detecting the signal. There aren't any

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Word synchronization by preceding or following synchronization signals required for the desired binary word. As a result of the multiple sampling during each bit period and a requirement of less than 100 % correlation, synchronization between the clock of the bit period and the clock of the detector is no longer necessary. Multiple sampling reduces the likelihood of receiving false or erroneous messages and improves the sensitivity of the detector. Due to the multiple sampling of the received signal and the correlation of the sampled samples with the desired specific word, a one-step method can be used instead of a two-step method, namely to recognize the binary bits and then to correlate the recognized binary bits with the bits of the desired word will. The use of the detector with the features described above is possible through the use of a word which is an element in a subscriber group of a cyclic code.

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Claims (12)

MO18P-792 Claims Asynchronous detector for determining certain binary words in a signal sequence, which bits with a certain duration, characterized by a clock, which a plurality supplies of first clock pulses during the duration of a bit period, one coupled to the clock generator Sampling and register storage device with a plurality of stages for storing serially stored binary signals, the sample and register storage means on the first Clock pulses responds in order to sample the signal applied on the input side of the signal sequence and this Signal corresponding binary signal to store, a data memory, which is a certain binary Word corresponding binary word and by a comparison device, which with the scanning and register storage means is coupled to the binary word with the sampled binary signal to compare and a comparison signal as a function of a predeterminable correlation between the generate binary signals and the binary word. 2. Detector according to claim 1, characterized in that the scanning and register storage device is a first shift register having a plurality of stages, each of which is a binary signal accordingly 209846 / 10G2 221739? MOl8P-792 contains a sampled signal. 3. Detector according to claim 1 or 2, characterized in that the data memory has a plurality comprised of stages each of which contains one bit of the binary word. 4. Detector according to one or more of claims 1 to 3, characterized in that the comparison means comprises a plurality of gates, each of which is connected to a stage of the shift register and is coupled to a stage of the register storage device that the gate circuits depending on a correlation between the binary signals in the first shift register and the binary bits in the register storage means are effective to produce a gate signal to be supplied and that a counter is coupled to the large number of gate circuits and counts the gate signals, wherein the counter supplies a detection signal as a function of a specific number of the gate signals. 5. Detector according to one or more of claims 1 to 4, characterized in that the clock delivers second clock pulses between the first clock pulses and that with the clock coupled counter responsive to the second clock pulses to count the gate signals and the detection signal to create. 6. Detector according to claim 5, characterized in that the clock generator has four clock pulses during the duration of a bit period. 7. Detector according to one or more of claims 3 to, characterized in that the binary 209846/1082 MO18P-792 Word comprises a certain number of binary bits, and that the first shift register has a has four times the number of stages as the specific number of binary bits of the binary word. 8. Detector according to claim 1 or 2, characterized in that the data memory is a second Shift register with a plurality of stages comprises, and that a switching device with certain stages of the second shift register is coupled, so that the shift register and the switching device in the Are able to generate the bits of the binary word. 9. Detector according to one or more of claims 1 to 8, characterized in that the clock generator generates a plurality of second clock pulses between the first clock pulses, and that the first and second shift registers respond to the second clock pulses to change the bits of the binary Word, as well as the binary signals through the shift register. 10. Detector according to one or more of claims 1 to 9, characterized in that the comparison device comprises gates associated with the last stage of the first and second Shift registers are coupled, the gate circuits depending on a correlation between the binary signal applied to the first shift register and the binary bit applied to the second shift register is effective that a counter is coupled to the gate circuits and counting signals as a function of the first gate signals that a switching device is coupled to the counter, which is based on a plurality of counting signals for generating the detection signal 209846/1062 MO18P-792 appeals to. 11. Detector according to claim 10, characterized in that the switching device responsive to the counting signals indicates a correlation of more than 80 % of the bits in the binary word and in the binary signal and generates an identification signal. 12. Detector according to claim 11, characterized in that the clock generator fourth clock pulses during each bit period that the first shift register supplies one of the fourfold Number of binary bits in the binary word comprises corresponding number of stages that the first shift register depending on every second clock pulse is wirsam and the binary signals through the shift register shifts that the second shift register depending on every fourth of the second clock pulses takes effect and shifts the binary bits through the shift register, with each binary bit in the second shift register and four of the binary signals in the first shift register are compared with one another will. 209846 / 10S2 L e r s e i t e