DK1246072T3 - Adaptiv læsning af forudhentning - Google Patents

Adaptiv læsning af forudhentning

Info

Publication number
DK1246072T3
DK1246072T3 DK02252252T DK02252252T DK1246072T3 DK 1246072 T3 DK1246072 T3 DK 1246072T3 DK 02252252 T DK02252252 T DK 02252252T DK 02252252 T DK02252252 T DK 02252252T DK 1246072 T3 DK1246072 T3 DK 1246072T3
Authority
DK
Denmark
Prior art keywords
retrieval
data
fetched
adaptive reading
amount
Prior art date
Application number
DK02252252T
Other languages
Danish (da)
English (en)
Inventor
Gary A Solomon
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of DK1246072T3 publication Critical patent/DK1246072T3/da

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
DK02252252T 2001-03-27 2002-03-27 Adaptiv læsning af forudhentning DK1246072T3 (da)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/818,951 US6795876B1 (en) 2001-03-27 2001-03-27 Adaptive read pre-fetch

Publications (1)

Publication Number Publication Date
DK1246072T3 true DK1246072T3 (da) 2004-01-26

Family

ID=25226857

Family Applications (1)

Application Number Title Priority Date Filing Date
DK02252252T DK1246072T3 (da) 2001-03-27 2002-03-27 Adaptiv læsning af forudhentning

Country Status (9)

Country Link
US (1) US6795876B1 (de)
EP (1) EP1246072B1 (de)
AT (1) ATE250242T1 (de)
DE (1) DE60200031T2 (de)
DK (1) DK1246072T3 (de)
ES (1) ES2206437T3 (de)
HK (1) HK1046746B (de)
PT (1) PT1246072E (de)
TW (1) TW564352B (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7051162B2 (en) * 2003-04-07 2006-05-23 Hewlett-Packard Development Company, L.P. Methods and apparatus used to retrieve data from memory before such data is requested
US7424562B2 (en) * 2004-03-01 2008-09-09 Cisco Technology, Inc. Intelligent PCI bridging consisting of prefetching data based upon descriptor data
US7318125B2 (en) * 2004-05-20 2008-01-08 International Business Machines Corporation Runtime selective control of hardware prefetch mechanism
TWI243999B (en) * 2004-08-17 2005-11-21 Via Tech Inc Apparatus and related method for maintaining read caching data of south bridge with north bridge
JP2006251923A (ja) * 2005-03-08 2006-09-21 Oki Electric Ind Co Ltd 先読み制御方法
CN100375068C (zh) * 2005-09-29 2008-03-12 威盛电子股份有限公司 选择性预取方法以及桥接模块
CN100392621C (zh) * 2005-10-14 2008-06-04 威盛电子股份有限公司 总线控制器及数据缓冲空间分配方法
JP2007200169A (ja) * 2006-01-30 2007-08-09 Hitachi Ltd ストレージシステム及び記憶制御方法
TWI502357B (zh) * 2009-08-11 2015-10-01 Via Tech Inc 資料預先提取方法、裝置及電腦系統
US8718806B2 (en) * 2011-09-02 2014-05-06 Apple Inc. Slave mode transmit with zero delay for audio interface
US8766707B1 (en) 2013-03-15 2014-07-01 Seagate Technology Llc Integrated always on power island for low power mode operation
US9335809B2 (en) 2013-03-15 2016-05-10 Seagate Technology Llc Volatile memory storing system data during low power mode operation and monitoring the voltage supplied to the memory during low power mode
US9411394B2 (en) 2013-03-15 2016-08-09 Seagate Technology Llc PHY based wake up from low power mode operation
JP6457836B2 (ja) * 2015-02-26 2019-01-23 ルネサスエレクトロニクス株式会社 プロセッサおよび命令コード生成装置

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EP0284100A3 (de) * 1987-03-27 1991-10-09 Nec Corporation Informationsprozessor mit einer Befehlsvorabruffunktion
JP2530873B2 (ja) * 1988-01-25 1996-09-04 富士通株式会社 命令プリフェッチアドレスの更新回路
US5146578A (en) * 1989-05-01 1992-09-08 Zenith Data Systems Corporation Method of varying the amount of data prefetched to a cache memory in dependence on the history of data requests
US5768548A (en) 1992-04-15 1998-06-16 Intel Corporation Bus bridge for responding to received first write command by storing data and for responding to received second write command by transferring the stored data
US5761464A (en) 1995-05-22 1998-06-02 Emc Corporation Prefetching variable length data
US5860150A (en) * 1995-10-06 1999-01-12 International Business Machines Corporation Instruction pre-fetching of a cache line within a processor
US6085291A (en) * 1995-11-06 2000-07-04 International Business Machines Corporation System and method for selectively controlling fetching and prefetching of data to a processor
US5765213A (en) * 1995-12-08 1998-06-09 Emc Corporation Method providing for the flexible prefetching of data from a data storage system
US5778435A (en) * 1996-05-30 1998-07-07 Lucent Technologies, Inc. History-based prefetch cache including a time queue
US6029228A (en) * 1996-12-31 2000-02-22 Texas Instruments Incorporated Data prefetching of a load target buffer for post-branch instructions based on past prediction accuracy's of branch predictions
US6195735B1 (en) * 1996-12-31 2001-02-27 Texas Instruments Incorporated Prefetch circuity for prefetching variable size data
US5958040A (en) * 1997-05-28 1999-09-28 Digital Equipment Corporation Adaptive stream buffers
US6012106A (en) 1997-11-03 2000-01-04 Digital Equipment Corporation Prefetch management for DMA read transactions depending upon past history of actual transfer lengths
US6167506A (en) * 1997-11-17 2000-12-26 Advanced Micro Devices, Inc. Replacing displacement in control transfer instruction with encoding indicative of target address, including offset and target cache line location
US6134643A (en) * 1997-11-26 2000-10-17 Intel Corporation Method and apparatus for cache line prediction and prefetching using a prefetch controller and buffer and access history
EP0924620A3 (de) 1997-12-22 2000-06-28 Compaq Computer Corporation Rechnersystem mit einer Busbrücke zur Durchführung von adaptiven spekulativen Leseoperationen
US6401193B1 (en) * 1998-10-26 2002-06-04 Infineon Technologies North America Corp. Dynamic data prefetching based on program counter and addressing mode
JP3206656B2 (ja) * 1998-12-21 2001-09-10 日本電気株式会社 バス上でのプリフェッチ装置およびプリフェッチ方法
US6622212B1 (en) * 1999-05-24 2003-09-16 Intel Corp. Adaptive prefetch of I/O data blocks
US6496921B1 (en) * 1999-06-30 2002-12-17 International Business Machines Corporation Layered speculative request unit with instruction optimized and storage hierarchy optimized partitions
US6625696B1 (en) * 2000-03-31 2003-09-23 Intel Corporation Method and apparatus to adaptively predict data quantities for caching
US6609168B1 (en) * 2000-03-31 2003-08-19 Intel Corporation Bus master read request adaptive prefetch prediction method and apparatus

Also Published As

Publication number Publication date
US6795876B1 (en) 2004-09-21
HK1046746B (zh) 2004-04-23
PT1246072E (pt) 2004-02-27
DE60200031T2 (de) 2004-07-08
HK1046746A1 (en) 2003-01-24
ATE250242T1 (de) 2003-10-15
EP1246072B1 (de) 2003-09-17
DE60200031D1 (de) 2003-10-23
EP1246072A1 (de) 2002-10-02
ES2206437T3 (es) 2004-05-16
TW564352B (en) 2003-12-01

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