DK119715B - Planartransistør. - Google Patents

Planartransistør.

Info

Publication number
DK119715B
DK119715B DK330567AA DK330567A DK119715B DK 119715 B DK119715 B DK 119715B DK 330567A A DK330567A A DK 330567AA DK 330567 A DK330567 A DK 330567A DK 119715 B DK119715 B DK 119715B
Authority
DK
Denmark
Prior art keywords
planar transistor
planar
transistor
Prior art date
Application number
DK330567AA
Other languages
Danish (da)
English (en)
Inventor
G Wolfrum
T Enzlin
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Publication of DK119715B publication Critical patent/DK119715B/da

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
DK330567AA 1966-06-29 1967-06-26 Planartransistør. DK119715B (da)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL6609002A NL6609002A (xx) 1966-06-29 1966-06-29

Publications (1)

Publication Number Publication Date
DK119715B true DK119715B (da) 1971-02-15

Family

ID=19797000

Family Applications (1)

Application Number Title Priority Date Filing Date
DK330567AA DK119715B (da) 1966-06-29 1967-06-26 Planartransistør.

Country Status (10)

Country Link
US (1) US3482150A (xx)
AT (1) AT278094B (xx)
BE (1) BE700582A (xx)
CH (1) CH465063A (xx)
DK (1) DK119715B (xx)
ES (1) ES342362A1 (xx)
GB (1) GB1193113A (xx)
NL (1) NL6609002A (xx)
NO (1) NO120434B (xx)
SE (1) SE326776B (xx)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3911468A (en) * 1970-05-22 1975-10-07 Kyoichiro Fujikawa Magnetic-to-electric conversion semiconductor device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3183576A (en) * 1962-06-26 1965-05-18 Ibm Method of making transistor structures
US3302076A (en) * 1963-06-06 1967-01-31 Motorola Inc Semiconductor device with passivated junction
DE1464921B2 (de) * 1963-10-03 1971-10-07 Fujitsu Ltd , Kawasaki, Kanagawa (Japan) Verfahren zum herstellen einer halbleiteranordnung
DE1273698B (de) * 1964-01-08 1968-07-25 Telefunken Patent Halbleiteranordnung
US3363152A (en) * 1964-01-24 1968-01-09 Westinghouse Electric Corp Semiconductor devices with low leakage current across junction
NL134388C (xx) * 1964-05-15 1900-01-01
US3305913A (en) * 1964-09-11 1967-02-28 Northern Electric Co Method for making a semiconductor device by diffusing impurities through spaced-apart holes in a non-conducting coating to form an overlapped diffused region by means oftransverse diffusion underneath the coating

Also Published As

Publication number Publication date
NL6609002A (xx) 1968-01-02
BE700582A (xx) 1967-12-27
CH465063A (de) 1968-11-15
DE1614261B2 (de) 1972-07-13
US3482150A (en) 1969-12-02
SE326776B (xx) 1970-08-03
NO120434B (xx) 1970-10-19
ES342362A1 (es) 1968-10-16
GB1193113A (en) 1970-05-28
DE1614261A1 (de) 1970-05-27
AT278094B (de) 1970-01-26

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