DE69921356D1 - Boundary-scanverfahren zur beendigung oder zum ändern von betriebsarten einer integrierten schaltung - Google Patents

Boundary-scanverfahren zur beendigung oder zum ändern von betriebsarten einer integrierten schaltung

Info

Publication number
DE69921356D1
DE69921356D1 DE69921356T DE69921356T DE69921356D1 DE 69921356 D1 DE69921356 D1 DE 69921356D1 DE 69921356 T DE69921356 T DE 69921356T DE 69921356 T DE69921356 T DE 69921356T DE 69921356 D1 DE69921356 D1 DE 69921356D1
Authority
DE
Germany
Prior art keywords
terminating
integrated circuit
operating modes
boundary scan
scan method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69921356T
Other languages
English (en)
Other versions
DE69921356T8 (de
DE69921356T2 (de
Inventor
Srinivas Ramamurthy
Fahey, Jr
Jinglun Tam
S Gongwer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Application granted granted Critical
Publication of DE69921356D1 publication Critical patent/DE69921356D1/de
Publication of DE69921356T2 publication Critical patent/DE69921356T2/de
Publication of DE69921356T8 publication Critical patent/DE69921356T8/de
Active legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Microcomputers (AREA)
DE69921356T 1998-12-03 1999-07-29 Boundary-scanverfahren zur beendigung oder zum ändern von betriebsarten einer integrierten schaltung Active DE69921356T8 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US205651 1980-11-10
US09/205,651 US6158034A (en) 1998-12-03 1998-12-03 Boundary scan method for terminating or modifying integrated circuit operating modes
PCT/US1999/017349 WO2000033094A1 (en) 1998-12-03 1999-07-29 Boundary scan method for terminating or modifying integrated circuit operating modes

Publications (3)

Publication Number Publication Date
DE69921356D1 true DE69921356D1 (de) 2004-11-25
DE69921356T2 DE69921356T2 (de) 2006-02-23
DE69921356T8 DE69921356T8 (de) 2006-04-27

Family

ID=22763080

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69921356T Active DE69921356T8 (de) 1998-12-03 1999-07-29 Boundary-scanverfahren zur beendigung oder zum ändern von betriebsarten einer integrierten schaltung

Country Status (10)

Country Link
US (1) US6158034A (de)
EP (1) EP1137952B1 (de)
JP (1) JP2002531835A (de)
KR (1) KR20010082321A (de)
CA (1) CA2347846A1 (de)
DE (1) DE69921356T8 (de)
MY (1) MY135956A (de)
NO (1) NO319358B1 (de)
TW (1) TW530160B (de)
WO (1) WO2000033094A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6378093B1 (en) * 1998-02-10 2002-04-23 Texas Instruments Incorporated Controller for scan distributor and controller architecture
US6594802B1 (en) * 2000-03-23 2003-07-15 Intellitech Corporation Method and apparatus for providing optimized access to circuits for debug, programming, and test
US20020150252A1 (en) * 2001-03-27 2002-10-17 Leopard Logic, Inc. Secure intellectual property for a generated field programmable gate array
JP4491174B2 (ja) * 2001-08-31 2010-06-30 富士通株式会社 アクセス制御装置及び試験方法
US7073111B2 (en) * 2002-06-10 2006-07-04 Texas Instruments Incorporated High speed interconnect circuit test method and apparatus
US7783925B2 (en) * 2004-12-02 2010-08-24 Texas Instruments Incorporated Receiving control, data, and control segments of communication scan packets

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0358365B1 (de) * 1988-09-07 1998-10-21 Texas Instruments Incorporated Prüf-Puffer/Register
US5412260A (en) * 1991-05-03 1995-05-02 Lattice Semiconductor Corporation Multiplexed control pins for in-system programming and boundary scan state machines in a high density programmable logic device
US5400345A (en) * 1992-03-06 1995-03-21 Pitney Bowes Inc. Communications system to boundary-scan logic interface
US5528610A (en) * 1992-04-30 1996-06-18 Hughes Aircraft Company Boundary test cell with self masking capability
US5404359A (en) * 1992-06-29 1995-04-04 Tandem Computers Incorporated Fail safe, fault tolerant circuit for manufacturing test logic on application specific integrated circuits
US5448576A (en) * 1992-10-29 1995-09-05 Bull Hn Information Systems Inc. Boundary scan architecture extension
US5404358A (en) * 1993-02-04 1995-04-04 Bull Hn Information Systems Inc. Boundary scan architecture analog extension
US5459737A (en) * 1993-07-07 1995-10-17 National Semiconductor Corporation Test access port controlled built in current monitor for IC devices
US5809036A (en) * 1993-11-29 1998-09-15 Motorola, Inc. Boundary-scan testable system and method
TW253942B (de) * 1994-01-31 1995-08-11 At & T Corp
GB9417602D0 (en) * 1994-09-01 1994-10-19 Inmos Ltd A controller for implementing scan testing
US5708773A (en) * 1995-07-20 1998-01-13 Unisys Corporation JTAG interface system for communicating with compliant and non-compliant JTAG devices
GB9622686D0 (en) * 1996-10-31 1997-01-08 Sgs Thomson Microelectronics A test port controller and a method of effecting communication using the same
US6314550B1 (en) * 1997-06-10 2001-11-06 Altera Corporation Cascaded programming with multiple-purpose pins

Also Published As

Publication number Publication date
MY135956A (en) 2008-07-31
NO20012711L (no) 2001-06-01
EP1137952A1 (de) 2001-10-04
EP1137952A4 (de) 2002-01-30
EP1137952B1 (de) 2004-10-20
DE69921356T8 (de) 2006-04-27
NO20012711D0 (no) 2001-06-01
DE69921356T2 (de) 2006-02-23
NO319358B1 (no) 2005-07-18
US6158034A (en) 2000-12-05
CA2347846A1 (en) 2000-06-08
KR20010082321A (ko) 2001-08-29
TW530160B (en) 2003-05-01
WO2000033094A1 (en) 2000-06-08
JP2002531835A (ja) 2002-09-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition