DE69840877D1 - Icher - Google Patents

Icher

Info

Publication number
DE69840877D1
DE69840877D1 DE69840877T DE69840877T DE69840877D1 DE 69840877 D1 DE69840877 D1 DE 69840877D1 DE 69840877 T DE69840877 T DE 69840877T DE 69840877 T DE69840877 T DE 69840877T DE 69840877 D1 DE69840877 D1 DE 69840877D1
Authority
DE
Germany
Prior art keywords
icher
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69840877T
Other languages
German (de)
English (en)
Inventor
Han Sung Chen
Tzeng-Huei Shiau
Tso-Ming Chang
Ray-Lin Wan
Fuchia Shone
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Macronix International Co Ltd
Original Assignee
Macronix International Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Macronix International Co Ltd filed Critical Macronix International Co Ltd
Application granted granted Critical
Publication of DE69840877D1 publication Critical patent/DE69840877D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4403—Processor initialisation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
DE69840877T 1998-01-06 1998-01-06 Icher Expired - Lifetime DE69840877D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1998/000459 WO1999035649A1 (en) 1998-01-06 1998-01-06 A memory supporting multiple address protocols

Publications (1)

Publication Number Publication Date
DE69840877D1 true DE69840877D1 (en) 2009-07-16

Family

ID=22266182

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69840877T Expired - Lifetime DE69840877D1 (en) 1998-01-06 1998-01-06 Icher

Country Status (4)

Country Link
EP (1) EP1058930B1 (enExample)
JP (1) JP2002501275A (enExample)
DE (1) DE69840877D1 (enExample)
WO (1) WO1999035649A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6058463A (en) * 1998-01-20 2000-05-02 Motorola, Inc. Paged memory data processing system with overlaid memory control registers
US6407949B1 (en) * 1999-12-17 2002-06-18 Qualcomm, Incorporated Mobile communication device having integrated embedded flash and SRAM memory
JP4731020B2 (ja) * 2001-01-24 2011-07-20 富士通セミコンダクター株式会社 半導体記憶装置、セクタアドレス変換回路、アドレス変換方法及び半導体記憶装置の使用方法
US7813212B2 (en) * 2008-01-17 2010-10-12 Mosaid Technologies Incorporated Nonvolatile memory having non-power of two memory capacity

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1254937B (it) * 1991-05-06 1995-10-11 Aggiornamento dinamico di memoria non volatile in un sistema informatico
US5245572A (en) * 1991-07-30 1993-09-14 Intel Corporation Floating gate nonvolatile memory with reading while writing capability
US5473775A (en) * 1991-10-11 1995-12-05 Kabushiki Kaisha Toshiba Personal computer using flash memory as BIOS-ROM
JPH06119230A (ja) * 1992-10-06 1994-04-28 Fujitsu Ltd 半導体記憶装置
US5680556A (en) * 1993-11-12 1997-10-21 International Business Machines Corporation Computer system and method of operation thereof wherein a BIOS ROM can be selectively locatable on diffeent buses

Also Published As

Publication number Publication date
WO1999035649A1 (en) 1999-07-15
EP1058930B1 (en) 2009-06-03
EP1058930A4 (en) 2005-02-16
EP1058930A1 (en) 2000-12-13
JP2002501275A (ja) 2002-01-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition