DE69835784D1 - Pseudoschmelzsicherung und ihre Anwendung bei einer Schaltung zum Setzen eines bistabilen Flip-Flop - Google Patents
Pseudoschmelzsicherung und ihre Anwendung bei einer Schaltung zum Setzen eines bistabilen Flip-FlopInfo
- Publication number
- DE69835784D1 DE69835784D1 DE69835784T DE69835784T DE69835784D1 DE 69835784 D1 DE69835784 D1 DE 69835784D1 DE 69835784 T DE69835784 T DE 69835784T DE 69835784 T DE69835784 T DE 69835784T DE 69835784 D1 DE69835784 D1 DE 69835784D1
- Authority
- DE
- Germany
- Prior art keywords
- flop
- fuse
- pseudo
- setting
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9702951A FR2760563A1 (fr) | 1997-03-07 | 1997-03-07 | Pseudofusible et application a un circuit d'etablissement d'une bascule a la mise sous tension |
Publications (1)
Publication Number | Publication Date |
---|---|
DE69835784D1 true DE69835784D1 (de) | 2006-10-19 |
Family
ID=9504667
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69835784T Expired - Lifetime DE69835784D1 (de) | 1997-03-07 | 1998-03-03 | Pseudoschmelzsicherung und ihre Anwendung bei einer Schaltung zum Setzen eines bistabilen Flip-Flop |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0863546B1 (de) |
JP (1) | JP3062471B2 (de) |
DE (1) | DE69835784D1 (de) |
FR (1) | FR2760563A1 (de) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6756255B1 (en) * | 2001-12-10 | 2004-06-29 | Advanced Micro Devices, Inc. | CMOS process with an integrated, high performance, silicide agglomeration fuse |
FR2835947A1 (fr) * | 2002-02-11 | 2003-08-15 | St Microelectronics Sa | Extraction d'un code binaire a partir de parametres physiques d'un circuit integre |
FR2835945A1 (fr) * | 2002-02-11 | 2003-08-15 | St Microelectronics Sa | Extraction d'un code binaire a partir de parametres physiques d'un circuit integre |
WO2004100271A1 (en) | 2003-04-11 | 2004-11-18 | International Business Machines Corporation | Programmable semiconductor device |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0758773B2 (ja) * | 1989-07-14 | 1995-06-21 | 三菱電機株式会社 | 半導体装置の製造方法及び半導体装置 |
DE4005851A1 (de) * | 1990-02-23 | 1991-08-29 | Siemens Ag | Verfahren zur stabilisierung von duennschichtwiderstaenden aus einem mehrkomponentigen widerstandsmaterial |
WO1992013359A1 (en) * | 1991-01-17 | 1992-08-06 | Crosspoint Solutions, Inc. | An improved antifuse circuit structure for use in a field programmable gate array and method of manufacture thereof |
WO1993003500A1 (en) * | 1991-08-01 | 1993-02-18 | Sierra Semiconductor Corporation | Method of forming a resistive element in a semiconductor device and a sram cell made thereby |
US5708291A (en) * | 1995-09-29 | 1998-01-13 | Intel Corporation | Silicide agglomeration fuse device |
-
1997
- 1997-03-07 FR FR9702951A patent/FR2760563A1/fr active Pending
-
1998
- 1998-03-03 DE DE69835784T patent/DE69835784D1/de not_active Expired - Lifetime
- 1998-03-03 EP EP98410025A patent/EP0863546B1/de not_active Expired - Lifetime
- 1998-03-06 JP JP10054824A patent/JP3062471B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0863546A1 (de) | 1998-09-09 |
FR2760563A1 (fr) | 1998-09-11 |
EP0863546B1 (de) | 2006-09-06 |
JP3062471B2 (ja) | 2000-07-10 |
JPH10340663A (ja) | 1998-12-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8332 | No legal effect for de |