DE69822534D1 - Gemeinsame Speicherbenutzung mit variablen Blockgrössen für symmetrische Multiporzessor-Gruppen - Google Patents

Gemeinsame Speicherbenutzung mit variablen Blockgrössen für symmetrische Multiporzessor-Gruppen

Info

Publication number
DE69822534D1
DE69822534D1 DE69822534T DE69822534T DE69822534D1 DE 69822534 D1 DE69822534 D1 DE 69822534D1 DE 69822534 T DE69822534 T DE 69822534T DE 69822534 T DE69822534 T DE 69822534T DE 69822534 D1 DE69822534 D1 DE 69822534D1
Authority
DE
Germany
Prior art keywords
shared memory
block sizes
memory use
variable block
symmetric multi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69822534T
Other languages
English (en)
Other versions
DE69822534T2 (de
Inventor
Daniel J Scales
Kourosh Gharachorloo
Anshu Aggarwal
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compaq Computer Corp
Original Assignee
Compaq Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compaq Computer Corp filed Critical Compaq Computer Corp
Publication of DE69822534D1 publication Critical patent/DE69822534D1/de
Application granted granted Critical
Publication of DE69822534T2 publication Critical patent/DE69822534T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9047—Buffering arrangements including multiple buffers, e.g. buffer pools
    • H04L49/9052—Buffering arrangements including multiple buffers, e.g. buffer pools with buffers of different sizes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/62—Queue scheduling characterised by scheduling criteria
    • H04L47/622—Queue service order
    • H04L47/6225—Fixed service order, e.g. Round Robin
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
DE69822534T 1997-02-03 1998-01-29 Gemeinsame Speicherbenutzung mit variablen Blockgrössen für symmetrische Multiporzessor-Gruppen Expired - Lifetime DE69822534T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/794,172 US5950228A (en) 1997-02-03 1997-02-03 Variable-grained memory sharing for clusters of symmetric multi-processors using private and shared state tables
US794172 1997-02-03

Publications (2)

Publication Number Publication Date
DE69822534D1 true DE69822534D1 (de) 2004-04-29
DE69822534T2 DE69822534T2 (de) 2005-01-27

Family

ID=25161908

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69822534T Expired - Lifetime DE69822534T2 (de) 1997-02-03 1998-01-29 Gemeinsame Speicherbenutzung mit variablen Blockgrössen für symmetrische Multiporzessor-Gruppen

Country Status (5)

Country Link
US (1) US5950228A (de)
EP (1) EP0856796B1 (de)
JP (1) JP4124849B2 (de)
CA (1) CA2228483A1 (de)
DE (1) DE69822534T2 (de)

Families Citing this family (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6324623B1 (en) 1997-05-30 2001-11-27 Oracle Corporation Computing system for implementing a shared cache
US6574720B1 (en) 1997-05-30 2003-06-03 Oracle International Corporation System for maintaining a buffer pool
US6542926B2 (en) 1998-06-10 2003-04-01 Compaq Information Technologies Group, L.P. Software partitioned multi-processor system with flexible resource sharing levels
US6199179B1 (en) 1998-06-10 2001-03-06 Compaq Computer Corporation Method and apparatus for failure recovery in a multi-processor computer system
US6633916B2 (en) 1998-06-10 2003-10-14 Hewlett-Packard Development Company, L.P. Method and apparatus for virtual resource handling in a multi-processor computer system
US6332180B1 (en) 1998-06-10 2001-12-18 Compaq Information Technologies Group, L.P. Method and apparatus for communication in a multi-processor computer system
US6381682B2 (en) * 1998-06-10 2002-04-30 Compaq Information Technologies Group, L.P. Method and apparatus for dynamically sharing memory in a multiprocessor system
US6647508B2 (en) 1997-11-04 2003-11-11 Hewlett-Packard Development Company, L.P. Multiprocessor computer architecture with multiple operating system instances and software controlled resource allocation
US6260068B1 (en) 1998-06-10 2001-07-10 Compaq Computer Corporation Method and apparatus for migrating resources in a multi-processor computer system
US6185662B1 (en) * 1997-12-22 2001-02-06 Nortel Networks Corporation High availability asynchronous computer system
US6279085B1 (en) * 1999-02-26 2001-08-21 International Business Machines Corporation Method and system for avoiding livelocks due to colliding writebacks within a non-uniform memory access system
GB2348303B (en) * 1999-03-23 2003-11-26 Ibm Data processing systems and method for processing work items in such systems
US7996843B2 (en) * 1999-08-25 2011-08-09 Qnx Software Systems Gmbh & Co. Kg Symmetric multi-processor system
US6487619B1 (en) * 1999-10-14 2002-11-26 Nec Corporation Multiprocessor system that communicates through an internal bus using a network protocol
US7509648B1 (en) * 2000-02-28 2009-03-24 At & T Corp. Paradigm in multimedia services creation methodology, and new service creation and service execution environments
US6457107B1 (en) 2000-02-28 2002-09-24 International Business Machines Corporation Method and apparatus for reducing false sharing in a distributed computing environment
US7185076B1 (en) 2000-05-31 2007-02-27 International Business Machines Corporation Method, system and program products for managing a clustered computing environment
US7487152B1 (en) 2000-05-31 2009-02-03 International Business Machines Corporation Method for efficiently locking resources of a global data repository
US6907601B1 (en) * 2000-06-30 2005-06-14 Intel Corporation Method and apparatus for inserting more than one allocation instruction within a routine
US6742086B1 (en) * 2000-08-11 2004-05-25 Unisys Corporation Affinity checking process for multiple processor, multiple bus optimization of throughput
US6751721B1 (en) 2000-08-31 2004-06-15 Hewlett-Packard Development Company, L.P. Broadcast invalidate scheme
US6633960B1 (en) * 2000-08-31 2003-10-14 Hewlett-Packard Development Company, L.P. Scalable directory based cache coherence protocol
US6546453B1 (en) 2000-08-31 2003-04-08 Compaq Information Technologies Group, L.P. Proprammable DRAM address mapping mechanism
US7213087B1 (en) 2000-08-31 2007-05-01 Hewlett-Packard Development Company, L.P. Mechanism to control the allocation of an N-source shared buffer
US6715057B1 (en) 2000-08-31 2004-03-30 Hewlett-Packard Development Company, L.P. Efficient translation lookaside buffer miss processing in computer systems with a large range of page sizes
US6704817B1 (en) 2000-08-31 2004-03-09 Hewlett-Packard Development Company, L.P. Computer architecture and system for efficient management of bi-directional bus
US6636955B1 (en) * 2000-08-31 2003-10-21 Hewlett-Packard Development Company, L.P. Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature
US6662319B1 (en) 2000-08-31 2003-12-09 Hewlett-Packard Development Company, L.P. Special encoding of known bad data
US6622225B1 (en) 2000-08-31 2003-09-16 Hewlett-Packard Development Company, L.P. System for minimizing memory bank conflicts in a computer system
US6662265B1 (en) 2000-08-31 2003-12-09 Hewlett-Packard Development Company, L.P. Mechanism to track all open pages in a DRAM memory system
US7099913B1 (en) * 2000-08-31 2006-08-29 Hewlett-Packard Development Company, L.P. Speculative directory writes in a directory based cache coherent nonuniform memory access protocol
US6668335B1 (en) 2000-08-31 2003-12-23 Hewlett-Packard Company, L.P. System for recovering data in a multiprocessor system comprising a conduction path for each bit between processors where the paths are grouped into separate bundles and routed along different paths
US6671822B1 (en) * 2000-08-31 2003-12-30 Hewlett-Packard Development Company, L.P. Method and system for absorbing defects in high performance microprocessor with a large n-way set associative cache
US6754739B1 (en) 2000-08-31 2004-06-22 Hewlett-Packard Development Company Computer resource management and allocation system
US6678840B1 (en) * 2000-08-31 2004-01-13 Hewlett-Packard Development Company, Lp. Fault containment and error recovery in a scalable multiprocessor
US6779142B1 (en) 2000-08-31 2004-08-17 Hewlett-Packard Development Company, L.P. Apparatus and method for interfacing a high speed scan-path with slow-speed test equipment
US6961781B1 (en) 2000-08-31 2005-11-01 Hewlett-Packard Development Company, L.P. Priority rules for reducing network message routing latency
US6654858B1 (en) 2000-08-31 2003-11-25 Hewlett-Packard Development Company, L.P. Method for reducing directory writes and latency in a high performance, directory-based, coherency protocol
US6738836B1 (en) * 2000-08-31 2004-05-18 Hewlett-Packard Development Company, L.P. Scalable efficient I/O port protocol
US6546465B1 (en) 2000-08-31 2003-04-08 Hewlett-Packard Development Company, L.P. Chaining directory reads and writes to reduce DRAM bandwidth in a directory based CC-NUMA protocol
US6681295B1 (en) 2000-08-31 2004-01-20 Hewlett-Packard Development Company, L.P. Fast lane prefetching
US6567900B1 (en) 2000-08-31 2003-05-20 Hewlett-Packard Development Company, L.P. Efficient address interleaving with simultaneous multiple locality options
US6665671B2 (en) * 2001-04-04 2003-12-16 Hewlett-Packard Development Company, L.P. System and method for optimization of shared data
US7380085B2 (en) * 2001-11-14 2008-05-27 Intel Corporation Memory adapted to provide dedicated and or shared memory to multiple processors and method therefor
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US6985984B2 (en) * 2002-11-07 2006-01-10 Sun Microsystems, Inc. Multiprocessing systems employing hierarchical back-off locks
US7080213B2 (en) * 2002-12-16 2006-07-18 Sun Microsystems, Inc. System and method for reducing shared memory write overhead in multiprocessor systems
GB2416417B (en) * 2003-04-11 2006-12-13 Sun Microsystems Inc Multi-node computer system with proxy transaction to read data from a non-owning memory device
US7945738B2 (en) 2003-04-11 2011-05-17 Oracle America, Inc. Multi-node computer system employing a reporting mechanism for multi-node transactions
US7334089B2 (en) * 2003-05-20 2008-02-19 Newisys, Inc. Methods and apparatus for providing cache state information
US7249224B2 (en) * 2003-08-05 2007-07-24 Newisys, Inc. Methods and apparatus for providing early responses from a remote data cache
US7139881B2 (en) * 2003-09-25 2006-11-21 International Business Machines Corporation Semiconductor device comprising a plurality of memory structures
US20060161718A1 (en) * 2005-01-20 2006-07-20 Berke Stuart A System and method for a non-uniform crossbar switch plane topology
US7844862B1 (en) * 2006-03-23 2010-11-30 Azul Systems, Inc. Detecting software race conditions
US9817914B2 (en) * 2006-05-09 2017-11-14 International Business Machines Corporation Extensible markup language (XML) performance optimization on a multi-core central processing unit (CPU) through core assignment
US7769964B2 (en) * 2006-08-21 2010-08-03 Intel Corporation Technique to perform memory reference filtering
JP5308629B2 (ja) * 2007-03-26 2013-10-09 ルネサスエレクトロニクス株式会社 マルチプロセッサシステム及びマルチプロセッサシステムにおけるアクセス保護方法
US7765242B2 (en) * 2007-05-10 2010-07-27 Hewlett-Packard Development Company, L.P. Methods and apparatus for structure layout optimization for multi-threaded programs
EP2210398A2 (de) * 2007-09-11 2010-07-28 Mentor Graphics Corporation Speicher-sharing und datenverteilung
FR2927437B1 (fr) 2008-02-07 2013-08-23 Bull Sas Systeme informatique multiprocesseur
US20090222832A1 (en) * 2008-02-29 2009-09-03 Dell Products, Lp System and method of enabling resources within an information handling system
CN101681345B (zh) * 2008-03-19 2013-09-11 松下电器产业株式会社 处理装置、处理系统、数据共享处理方法及数据共享处理用集成电路
US9274855B2 (en) * 2008-12-24 2016-03-01 Intel Corporation Optimization for safe elimination of weak atomicity overhead
SG169246A1 (en) * 2009-08-24 2011-03-30 Dell Products Lp System and method of enabling resources within an information handling system
US8607004B2 (en) * 2009-11-13 2013-12-10 Richard S. Anderson Distributed symmetric multiprocessing computing architecture
WO2013088283A2 (en) 2011-12-16 2013-06-20 International Business Machines Corporation Memory sharing by processors
CN103716753B (zh) * 2012-09-29 2018-12-25 中兴通讯股份有限公司 一种小数据发送方法、系统及用户设备
CN106796536A (zh) * 2016-12-27 2017-05-31 深圳前海达闼云端智能科技有限公司 用于多操作系统的内存访问方法、装置和电子设备
TWI704460B (zh) * 2019-01-19 2020-09-11 神雲科技股份有限公司 叢集式系統中維持記憶體共享方法
JP7049290B2 (ja) 2019-05-15 2022-04-06 本田技研工業株式会社 回転電気のロータ

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4442487A (en) * 1981-12-31 1984-04-10 International Business Machines Corporation Three level memory hierarchy using write and share flags
US5426747A (en) * 1991-03-22 1995-06-20 Object Design, Inc. Method and apparatus for virtual memory mapping and transaction management in an object-oriented database system
US5428803A (en) * 1992-07-10 1995-06-27 Cray Research, Inc. Method and apparatus for a unified parallel processing architecture
JP3740195B2 (ja) * 1994-09-09 2006-02-01 株式会社ルネサステクノロジ データ処理装置
US5758183A (en) * 1996-07-17 1998-05-26 Digital Equipment Corporation Method of reducing the number of overhead instructions by modifying the program to locate instructions that access shared data stored at target addresses before program execution
US5761729A (en) * 1996-07-17 1998-06-02 Digital Equipment Corporation Validation checking of shared memory accesses
US6148377A (en) * 1996-11-22 2000-11-14 Mangosoft Corporation Shared memory computer networks

Also Published As

Publication number Publication date
US5950228A (en) 1999-09-07
JP4124849B2 (ja) 2008-07-23
CA2228483A1 (en) 1998-08-03
DE69822534T2 (de) 2005-01-27
EP0856796A2 (de) 1998-08-05
EP0856796A3 (de) 2001-09-26
EP0856796B1 (de) 2004-03-24
JPH10289214A (ja) 1998-10-27

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