DE69814491D1 - Vorrichtung und Verfahren zur Fehlererkennung in einer integrierten Schaltung mit einer parallelen-seriellen Anschlussstelle - Google Patents

Vorrichtung und Verfahren zur Fehlererkennung in einer integrierten Schaltung mit einer parallelen-seriellen Anschlussstelle

Info

Publication number
DE69814491D1
DE69814491D1 DE69814491T DE69814491T DE69814491D1 DE 69814491 D1 DE69814491 D1 DE 69814491D1 DE 69814491 T DE69814491 T DE 69814491T DE 69814491 T DE69814491 T DE 69814491T DE 69814491 D1 DE69814491 D1 DE 69814491D1
Authority
DE
Germany
Prior art keywords
integrated circuit
parallel
connection point
fault detection
serial connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69814491T
Other languages
English (en)
Other versions
DE69814491T2 (de
Inventor
Jean-Francois Autechaud
Christophe Dionet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull Sa Les Clayes Sous Bois Fr
Original Assignee
Bull SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull SA filed Critical Bull SA
Application granted granted Critical
Publication of DE69814491D1 publication Critical patent/DE69814491D1/de
Publication of DE69814491T2 publication Critical patent/DE69814491T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/104—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error using arithmetic codes, i.e. codes which are preserved during operation, e.g. modulo 9 or 11 check
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H04L69/324—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Detection And Correction Of Errors (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE69814491T 1997-02-19 1998-02-12 Vorrichtung und Verfahren zur Fehlererkennung in einer integrierten Schaltung mit einer parallelen-seriellen Anschlussstelle Expired - Lifetime DE69814491T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9701944 1997-02-19
FR9701944A FR2759796B1 (fr) 1997-02-19 1997-02-19 Dispositif et procede de detection d'erreurs sur un circuit integre comportant un port parallele serie

Publications (2)

Publication Number Publication Date
DE69814491D1 true DE69814491D1 (de) 2003-06-18
DE69814491T2 DE69814491T2 (de) 2004-04-08

Family

ID=9503904

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69814491T Expired - Lifetime DE69814491T2 (de) 1997-02-19 1998-02-12 Vorrichtung und Verfahren zur Fehlererkennung in einer integrierten Schaltung mit einer parallelen-seriellen Anschlussstelle

Country Status (5)

Country Link
US (1) US6173423B1 (de)
EP (1) EP0860778B1 (de)
JP (1) JP2988901B2 (de)
DE (1) DE69814491T2 (de)
FR (1) FR2759796B1 (de)

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US6560290B2 (en) * 1998-01-20 2003-05-06 Silicon Image, Inc. CMOS driver and on-chip termination for gigabaud speed data communication
US7167892B2 (en) * 1998-03-19 2007-01-23 Isochron, Inc. System, method and apparatus for vending machine wireless audit and cashless transaction transport
US6385236B1 (en) * 1998-10-05 2002-05-07 Lsi Logic Corporation Method and Circuit for testing devices with serial data links
US6886126B1 (en) * 2000-03-23 2005-04-26 Cypress Semiconductor Corp. Apparatus and protocol for detected error propagation in serial-transport block-coded interfaces
US7016430B1 (en) 2001-03-21 2006-03-21 Cyrpess Semiconductor Corp. Apparatus and protocol for exception propagation in serial transport block coded interfaces
US20030165242A1 (en) * 2001-11-19 2003-09-04 Adrian Walker Confusion encryption
US8650470B2 (en) 2003-03-20 2014-02-11 Arm Limited Error recovery within integrated circuit
US8185812B2 (en) 2003-03-20 2012-05-22 Arm Limited Single event upset error detection within an integrated circuit
US7278080B2 (en) * 2003-03-20 2007-10-02 Arm Limited Error detection and recovery within processing stages of an integrated circuit
EP1604281B1 (de) * 2003-03-20 2006-08-09 ARM Limited Fehlererkennung und fehlerbehebung für systematische und zufällige fehler innerhalb einer verarbeitungsstufe einer integrierten schaltung
US7260001B2 (en) * 2003-03-20 2007-08-21 Arm Limited Memory system having fast and slow data reading mechanisms
US8234399B2 (en) * 2003-05-29 2012-07-31 Seagate Technology Llc Method and apparatus for automatic phy calibration based on negotiated link speed
US7730476B2 (en) 2003-07-01 2010-06-01 Hewlett-Packard Development Company, L.P. Field-replaceable unit revision compatibility
US7725892B2 (en) 2003-07-01 2010-05-25 Hewlett-Packard Development Company, L.P. Field-replaceable unit revision compatibility
US7606253B2 (en) * 2004-01-12 2009-10-20 Hewlett-Packard Development Company, L.P. Successful transactions
US7613958B2 (en) 2004-01-12 2009-11-03 Hewlett-Packard Development Company, L.P. Error detection in a system having coupled channels
US7672222B2 (en) * 2004-01-12 2010-03-02 Hewlett-Packard Development Company, L.P. Link failures
US20060184707A1 (en) * 2005-02-11 2006-08-17 Lesartre Gregg B Error injection
FR2870958B1 (fr) * 2004-05-25 2008-01-25 Hewlett Packard Development Co Systeme pour injecter des erreurs dans une liaison de commun ications
US7624213B2 (en) * 2005-02-11 2009-11-24 Hewlett-Packard Development Company, L.P. Passing identification information
US7721159B2 (en) * 2005-02-11 2010-05-18 Hewlett-Packard Development Company, L.P. Passing debug information
US8073042B1 (en) 2005-04-13 2011-12-06 Cypress Semiconductor Corporation Recursive range controller
US8171386B2 (en) * 2008-03-27 2012-05-01 Arm Limited Single event upset error detection within sequential storage circuitry of an integrated circuit
US8161367B2 (en) * 2008-10-07 2012-04-17 Arm Limited Correction of single event upset error within sequential storage circuitry of an integrated circuit
US8493120B2 (en) 2011-03-10 2013-07-23 Arm Limited Storage circuitry and method with increased resilience to single event upsets
US9262270B2 (en) * 2012-12-28 2016-02-16 Intel Corporation Live error recovery

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Publication number Priority date Publication date Assignee Title
GB2097653B (en) 1981-04-07 1985-06-05 Sadler James & Sons Ltd Insulated containers for dispensing liquids
JPS59136843A (ja) * 1983-01-27 1984-08-06 Yokogawa Hokushin Electric Corp シリアルデ−タ転送における誤り訂正機能の動作チエツク方法
JPS6159547A (ja) * 1984-08-30 1986-03-27 Yokogawa Hokushin Electric Corp 誤り訂正機能の動作チエツク装置
US4712215A (en) * 1985-12-02 1987-12-08 Advanced Micro Devices, Inc. CRC calculation machine for separate calculation of checkbits for the header packet and data packet
US4809273A (en) * 1987-01-29 1989-02-28 International Business Machines Corporation Device for verifying operation of a checking code generator
US4935925A (en) * 1987-03-11 1990-06-19 Aristacom International, Inc. Adaptive digital network interface
US4907225A (en) * 1987-04-03 1990-03-06 Advanced Micro Devices, Inc. Data protocol controller
US4827477A (en) * 1987-05-15 1989-05-02 Grumman Aerospace Corporation Bus interface unit
US5394390A (en) * 1993-10-29 1995-02-28 International Business Machines Corporation FDDI network test adapter history store circuit (HSC)
US5754525A (en) * 1994-12-30 1998-05-19 Advanced Micro Devices Inc. Programmable delay of disrupt for secure networks
US5581559A (en) * 1995-03-17 1996-12-03 Advanced Micro Devices, Inc. Inverse packet disrupt for secure networks
US5907566A (en) * 1997-05-29 1999-05-25 3Com Corporation Continuous byte-stream encoder/decoder using frequency increase and cyclic redundancy check

Also Published As

Publication number Publication date
DE69814491T2 (de) 2004-04-08
US6173423B1 (en) 2001-01-09
FR2759796A1 (fr) 1998-08-21
JP2988901B2 (ja) 1999-12-13
JPH10260914A (ja) 1998-09-29
EP0860778A1 (de) 1998-08-26
FR2759796B1 (fr) 2001-12-07
EP0860778B1 (de) 2003-05-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: BULL S.A., LES CLAYES SOUS BOIS, FR