DE69810896D1 - Kommunikationsfehlererkennung an einem Chipübergang - Google Patents
Kommunikationsfehlererkennung an einem ChipübergangInfo
- Publication number
- DE69810896D1 DE69810896D1 DE69810896T DE69810896T DE69810896D1 DE 69810896 D1 DE69810896 D1 DE 69810896D1 DE 69810896 T DE69810896 T DE 69810896T DE 69810896 T DE69810896 T DE 69810896T DE 69810896 D1 DE69810896 D1 DE 69810896D1
- Authority
- DE
- Germany
- Prior art keywords
- serial
- test
- communication
- data
- error condition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0763—Error or fault detection not based on redundancy by bit configuration check, e.g. of formats or tags
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318544—Scanning methods, algorithms and patterns
- G01R31/31855—Interconnection testing, e.g. crosstalk, shortcircuits
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Tests Of Electronic Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GBGB9810512.5A GB9810512D0 (en) | 1998-05-15 | 1998-05-15 | Detecting communication errors across a chip boundary |
Publications (1)
Publication Number | Publication Date |
---|---|
DE69810896D1 true DE69810896D1 (de) | 2003-02-27 |
Family
ID=10832164
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69810896T Expired - Lifetime DE69810896D1 (de) | 1998-05-15 | 1998-11-27 | Kommunikationsfehlererkennung an einem Chipübergang |
Country Status (4)
Country | Link |
---|---|
US (1) | US6381721B1 (de) |
EP (1) | EP0957429B1 (de) |
DE (1) | DE69810896D1 (de) |
GB (1) | GB9810512D0 (de) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1213876B1 (de) * | 2000-12-06 | 2007-07-25 | Tektronix Berlin GmbH & Co. KG | Schaltungsanordnung zum Testen eines Kommunikationssystems |
US7065675B1 (en) * | 2001-05-08 | 2006-06-20 | Mips Technologies, Inc. | System and method for speeding up EJTAG block data transfers |
DE60125360D1 (de) * | 2001-09-18 | 2007-02-01 | Sgs Thomson Microelectronics | Abfrageprüfgerät, das Überabtastung zur Synchronisierung verwendet |
US7085859B2 (en) * | 2003-05-14 | 2006-08-01 | International Business Machines Corporation | Method, apparatus and program storage device for automatically presenting status from a host bus adapter until an error is detected |
US20050099832A1 (en) * | 2003-11-12 | 2005-05-12 | Agere Systems, Incorporated | System and method for securing an integrated circuit as against subsequent reprogramming |
DE102006016303B4 (de) * | 2006-04-06 | 2015-06-18 | Infineon Technologies Ag | Untergeordnete Testschnittstelle |
US8473818B2 (en) * | 2009-10-12 | 2013-06-25 | Empire Technology Development Llc | Reliable communications in on-chip networks |
US10949278B2 (en) * | 2018-06-26 | 2021-03-16 | Qualcomm Incorporated | Early detection of execution errors |
CN111371632B (zh) * | 2018-12-25 | 2023-04-28 | 阿里巴巴集团控股有限公司 | 通信方法、装置、设备及存储介质 |
CN116738020B (zh) * | 2023-04-17 | 2024-06-11 | 深圳市晶存科技有限公司 | 芯片测试结果的展示方法、系统、装置及存储介质 |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4692918A (en) * | 1984-12-17 | 1987-09-08 | At&T Bell Laboratories | Reliable local data network arrangement |
US4975828A (en) * | 1987-08-05 | 1990-12-04 | Cirrus Logic, Inc. | Multi-channel data communications controller |
US5535331A (en) * | 1987-09-04 | 1996-07-09 | Texas Instruments Incorporated | Processor condition sensing circuits, systems and methods |
US5029166A (en) * | 1989-05-31 | 1991-07-02 | At&T Bell Laboratories | Method and apparatus for testing circuit boards |
US5056094A (en) * | 1989-06-09 | 1991-10-08 | Texas Instruments Incorporated | Delay fault testing method and apparatus |
US5068851A (en) * | 1989-08-01 | 1991-11-26 | Digital Equipment Corporation | Apparatus and method for documenting faults in computing modules |
JP3555953B2 (ja) * | 1993-12-21 | 2004-08-18 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴイ | プリング抵抗を備える接続部をテストする装置 |
GB9417268D0 (en) | 1994-08-26 | 1994-10-19 | Inmos Ltd | Testing an integrated circuit device |
GB9417590D0 (en) | 1994-09-01 | 1994-10-19 | Inmos Ltd | Scan latch |
GB9417592D0 (en) | 1994-09-01 | 1994-10-19 | Inmos Ltd | Single clock scan latch |
GB9417602D0 (en) | 1994-09-01 | 1994-10-19 | Inmos Ltd | A controller for implementing scan testing |
GB9417591D0 (en) | 1994-09-01 | 1994-10-19 | Inmos Ltd | Scan testable double edge triggered scan cell |
GB9417589D0 (en) | 1994-09-01 | 1994-10-19 | Inmos Ltd | Scan test |
JPH0895439A (ja) | 1994-09-14 | 1996-04-12 | Eastman Kodak Co | 複写装置のオペレータ操作パネル |
GB9421977D0 (en) | 1994-10-31 | 1994-12-21 | Inmos Ltd | A scan latch and test method therefor |
JP3099703B2 (ja) * | 1995-02-22 | 2000-10-16 | 株式会社デンソー | 通信システム |
US5649001A (en) * | 1995-03-24 | 1997-07-15 | U.S. Robotics Mobile Communications Corp. | Method and apparatus for adapting a communication interface device to multiple networks |
US5691998A (en) * | 1995-05-10 | 1997-11-25 | Teltrend Inc. | Data transmission protection circuit with error correction |
TW297096B (de) * | 1995-06-07 | 1997-02-01 | Ast Res Inc | |
US5659552A (en) * | 1995-10-17 | 1997-08-19 | Lucent Technologies Inc. | Method and apparatus for verifying test information on a backplane test bus |
GB9622687D0 (en) * | 1996-10-31 | 1997-01-08 | Sgs Thomson Microelectronics | An integrated circuit with tap controller |
GB9622685D0 (en) | 1996-10-31 | 1997-01-08 | Sgs Thomson Microelectronics | An integrated circuit device and method of communication therewith |
US5841867A (en) * | 1996-11-01 | 1998-11-24 | Xilinx, Inc. | On-chip programming verification system for PLDs |
-
1998
- 1998-05-15 GB GBGB9810512.5A patent/GB9810512D0/en not_active Ceased
- 1998-11-27 DE DE69810896T patent/DE69810896D1/de not_active Expired - Lifetime
- 1998-11-27 EP EP98309735A patent/EP0957429B1/de not_active Expired - Lifetime
-
1999
- 1999-05-14 US US09/311,990 patent/US6381721B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0957429A1 (de) | 1999-11-17 |
EP0957429B1 (de) | 2003-01-22 |
US6381721B1 (en) | 2002-04-30 |
GB9810512D0 (en) | 1998-07-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8332 | No legal effect for de |