DE69803373D1 - Verdrahtung von Zellen in logischen Feldern - Google Patents

Verdrahtung von Zellen in logischen Feldern

Info

Publication number
DE69803373D1
DE69803373D1 DE69803373T DE69803373T DE69803373D1 DE 69803373 D1 DE69803373 D1 DE 69803373D1 DE 69803373 T DE69803373 T DE 69803373T DE 69803373 T DE69803373 T DE 69803373T DE 69803373 D1 DE69803373 D1 DE 69803373D1
Authority
DE
Germany
Prior art keywords
logical fields
wiring cells
wiring
cells
logical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69803373T
Other languages
English (en)
Other versions
DE69803373T2 (de
Inventor
Alan Marshall
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Application granted granted Critical
Publication of DE69803373D1 publication Critical patent/DE69803373D1/de
Publication of DE69803373T2 publication Critical patent/DE69803373T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks
DE69803373T 1998-07-06 1998-07-06 Verdrahtung von Zellen in logischen Feldern Expired - Lifetime DE69803373T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP98305369A EP0978944B1 (de) 1998-07-06 1998-07-06 Verdrahtung von Zellen in logischen Feldern

Publications (2)

Publication Number Publication Date
DE69803373D1 true DE69803373D1 (de) 2002-02-28
DE69803373T2 DE69803373T2 (de) 2002-08-14

Family

ID=8234918

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69803373T Expired - Lifetime DE69803373T2 (de) 1998-07-06 1998-07-06 Verdrahtung von Zellen in logischen Feldern

Country Status (3)

Country Link
US (1) US6157214A (de)
EP (1) EP0978944B1 (de)
DE (1) DE69803373T2 (de)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
DE19651075A1 (de) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen
DE19654595A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
EP1329816B1 (de) 1996-12-27 2011-06-22 Richter, Thomas Verfahren zum selbständigen dynamischen Umladen von Datenflussprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o.dgl.)
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
WO2000077652A2 (de) 1999-06-10 2000-12-21 Pact Informationstechnologie Gmbh Sequenz-partitionierung auf zellstrukturen
EP2226732A3 (de) 2000-06-13 2016-04-06 PACT XPP Technologies AG Cachehierarchie für einen Multicore-Prozessor
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
WO2005045692A2 (en) 2003-08-28 2005-05-19 Pact Xpp Technologies Ag Data processing device and method
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7657877B2 (en) 2001-06-20 2010-02-02 Pact Xpp Technologies Ag Method for processing data
WO2003005583A2 (en) * 2001-06-29 2003-01-16 Koninklijke Philips Electronics N.V. A reconfigurable analog cell and an arrangement comprising a plurality of such cell
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
AU2003208266A1 (en) 2002-01-19 2003-07-30 Pact Xpp Technologies Ag Reconfigurable processor
AU2003214003A1 (en) 2002-02-18 2003-09-09 Pact Xpp Technologies Ag Bus systems and method for reconfiguration
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
WO2004021176A2 (de) 2002-08-07 2004-03-11 Pact Xpp Technologies Ag Verfahren und vorrichtung zur datenverarbeitung
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
US7394284B2 (en) 2002-09-06 2008-07-01 Pact Xpp Technologies Ag Reconfigurable sequencer structure
US7225422B2 (en) * 2003-06-19 2007-05-29 International Business Machines Corporation Wire trimmed programmable logic array
US7327591B2 (en) * 2004-06-17 2008-02-05 Texas Instruments Incorporated Staggered memory cell array
WO2007082730A1 (de) 2006-01-18 2007-07-26 Pact Xpp Technologies Ag Hardwaredefinitionsverfahren
CN103048955B (zh) * 2012-12-04 2015-10-28 常州大学 一种基于fpaa和fpga的智能重构柔性电机控制系统
CN114781300B (zh) * 2022-06-21 2022-09-09 上海国微思尔芯技术股份有限公司 可编辑逻辑阵列布线方法、装置、设备和存储介质

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5073729A (en) * 1990-06-22 1991-12-17 Actel Corporation Segmented routing architecture
US5367209A (en) * 1992-01-07 1994-11-22 Hauck Scott A Field programmable gate array for synchronous and asynchronous operation
JPH06276086A (ja) * 1993-03-18 1994-09-30 Fuji Xerox Co Ltd フィールドプログラマブルゲートアレイ
US5581199A (en) * 1995-01-04 1996-12-03 Xilinx, Inc. Interconnect architecture for field programmable gate array using variable length conductors
US5631578A (en) * 1995-06-02 1997-05-20 International Business Machines Corporation Programmable array interconnect network

Also Published As

Publication number Publication date
EP0978944A1 (de) 2000-02-09
EP0978944B1 (de) 2002-01-02
DE69803373T2 (de) 2002-08-14
US6157214A (en) 2000-12-05

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