DE69732738D1 - Verwendung von untergeordneten Busgeräten in einem Rechnersystem - Google Patents

Verwendung von untergeordneten Busgeräten in einem Rechnersystem

Info

Publication number
DE69732738D1
DE69732738D1 DE69732738T DE69732738T DE69732738D1 DE 69732738 D1 DE69732738 D1 DE 69732738D1 DE 69732738 T DE69732738 T DE 69732738T DE 69732738 T DE69732738 T DE 69732738T DE 69732738 D1 DE69732738 D1 DE 69732738D1
Authority
DE
Germany
Prior art keywords
computer system
bus devices
subordinate bus
subordinate
devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69732738T
Other languages
English (en)
Inventor
William F Whiteman
Alan L Goodrum
Tod B Cox
Barry S Basile
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compaq Computer Corp
Original Assignee
Compaq Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compaq Computer Corp filed Critical Compaq Computer Corp
Application granted granted Critical
Publication of DE69732738D1 publication Critical patent/DE69732738D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/404—Coupling between buses using bus bridges with address mapping

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69732738T 1996-06-05 1997-06-04 Verwendung von untergeordneten Busgeräten in einem Rechnersystem Expired - Lifetime DE69732738D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/658,634 US5911055A (en) 1996-06-05 1996-06-05 Using subordinate bus devices that are connected to a common bus

Publications (1)

Publication Number Publication Date
DE69732738D1 true DE69732738D1 (de) 2005-04-21

Family

ID=24642042

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69732738T Expired - Lifetime DE69732738D1 (de) 1996-06-05 1997-06-04 Verwendung von untergeordneten Busgeräten in einem Rechnersystem

Country Status (4)

Country Link
US (1) US5911055A (de)
EP (1) EP0811938B1 (de)
JP (1) JPH10124451A (de)
DE (1) DE69732738D1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3429149B2 (ja) * 1996-12-19 2003-07-22 ソニー株式会社 伝送装置及びサーバ装置並びに伝送方法
US7734852B1 (en) 1998-08-06 2010-06-08 Ahern Frank W Modular computer system
US7269680B1 (en) 1998-08-06 2007-09-11 Tao Logic Systems Llc System enabling device communication in an expanded computing device
US6502156B1 (en) 1999-12-27 2002-12-31 Intel Corporation Controlling I/O devices independently of a host processor
US6594719B1 (en) 2000-04-19 2003-07-15 Mobility Electronics Inc. Extended cardbus/pc card controller with split-bridge ™technology
US7107383B1 (en) * 2000-05-03 2006-09-12 Broadcom Corporation Method and system for multi-channel transfer of data and control information
US20030188061A1 (en) * 2002-03-28 2003-10-02 Luse Paul E. Device discovery and dynamic configuration of control application
US6772272B2 (en) * 2002-04-25 2004-08-03 International Business Machines Corporation Apparatus and method for writing information to a designated information storage medium with an allocated data storage device using a specified information recording format
US7143217B2 (en) * 2002-05-28 2006-11-28 Intel Corporation Device configuration
US20060106796A1 (en) * 2004-11-17 2006-05-18 Honeywell International Inc. Knowledge stores for interactive diagnostics
JP4987376B2 (ja) * 2006-07-26 2012-07-25 タオ ロジック システムズ リミティド ライアビリティ カンパニー リンクブリッジ
JP2006323869A (ja) * 2006-07-26 2006-11-30 Mobility Electronics Inc 結合システムおよび方法
TWI439869B (zh) * 2010-08-18 2014-06-01 Pegatron Corp 調整連結速度的方法及其電腦系統
JP5033228B2 (ja) * 2010-09-13 2012-09-26 タオ ロジック システムズ リミティド ライアビリティ カンパニー リンクブリッジ

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1122890B (it) * 1979-08-30 1986-04-30 Honeywell Inf Systems Italia Sistema a microprocessori con struttura modulare a bus e configurazione espandibile
US4682326A (en) * 1985-11-27 1987-07-21 General Electric Company Method and apparatus for maintaining a dynamic logical ring in a token passing lan
JP2703668B2 (ja) * 1991-03-18 1998-01-26 株式会社日立製作所 データ転送制御装置および磁気ディスク制御装置
JP3528094B2 (ja) * 1994-02-09 2004-05-17 株式会社日立製作所 バス利用方法および記憶制御装置
SG47015A1 (en) * 1994-02-24 1998-03-20 Intel Corp Apparatus and method for prefetching data to load buffers in a bridge between two buses in a computer
US5555383A (en) * 1994-11-07 1996-09-10 International Business Machines Corporation Peripheral component interconnect bus system having latency and shadow timers

Also Published As

Publication number Publication date
US5911055A (en) 1999-06-08
EP0811938A3 (de) 1999-08-04
EP0811938A2 (de) 1997-12-10
EP0811938B1 (de) 2005-03-16
JPH10124451A (ja) 1998-05-15

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Legal Events

Date Code Title Description
8332 No legal effect for de