DE69726248D1 - Addierer mit bedingter Summe unter Benutzung von Durchlasstransistor-Logik - Google Patents

Addierer mit bedingter Summe unter Benutzung von Durchlasstransistor-Logik

Info

Publication number
DE69726248D1
DE69726248D1 DE69726248T DE69726248T DE69726248D1 DE 69726248 D1 DE69726248 D1 DE 69726248D1 DE 69726248 T DE69726248 T DE 69726248T DE 69726248 T DE69726248 T DE 69726248T DE 69726248 D1 DE69726248 D1 DE 69726248D1
Authority
DE
Germany
Prior art keywords
pass transistor
transistor logic
sum adder
conditional sum
conditional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69726248T
Other languages
English (en)
Other versions
DE69726248T2 (de
Inventor
Min-Kyu Song
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
Publication of DE69726248D1 publication Critical patent/DE69726248D1/de
Publication of DE69726248T2 publication Critical patent/DE69726248T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5318—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with column wise addition of partial products, e.g. using Wallace tree, Dadda counters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/507—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using selection between two conditionally calculated carry or sum values
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4816—Pass transistors
DE69726248T 1996-12-18 1997-12-18 Addierer mit bedingter Summe unter Benutzung von Durchlasstransistor-Logik Expired - Lifetime DE69726248T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019960067478A KR100224278B1 (ko) 1996-12-18 1996-12-18 패스 트랜지스터 로직을 사용하는 조건 합 가산기 및 그것을 구비한 집적 회로
KR9667478 1996-12-18

Publications (2)

Publication Number Publication Date
DE69726248D1 true DE69726248D1 (de) 2003-12-24
DE69726248T2 DE69726248T2 (de) 2004-09-02

Family

ID=19488899

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69726248T Expired - Lifetime DE69726248T2 (de) 1996-12-18 1997-12-18 Addierer mit bedingter Summe unter Benutzung von Durchlasstransistor-Logik

Country Status (5)

Country Link
US (1) US6012079A (de)
EP (1) EP0849663B1 (de)
JP (1) JP3765658B2 (de)
KR (1) KR100224278B1 (de)
DE (1) DE69726248T2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3608970B2 (ja) * 1999-03-16 2005-01-12 富士通株式会社 論理回路
US6346427B1 (en) 1999-08-18 2002-02-12 Utmc Microelectronic Systems Inc. Parameter adjustment in a MOS integrated circuit
US6615229B1 (en) * 2000-06-29 2003-09-02 Intel Corporation Dual threshold voltage complementary pass-transistor logic implementation of a low-power, partitioned multiplier
US6990508B1 (en) * 2001-09-11 2006-01-24 Cypress Semiconductor Corp. High performance carry chain with reduced macrocell logic and fast carry lookahead
KR100866787B1 (ko) 2002-01-16 2008-11-04 삼성전자주식회사 Ｘｏｒ에 기반한 캐리 생성기와 이를 이용한 조건 선택가산 장치 및 그 방법
US7206802B2 (en) * 2002-10-10 2007-04-17 International Business Machines Corporation Hybrid carry look ahead/carry select adder including carry logic generating complementary hot carry signals, and method for producing the carry logic
KR100459735B1 (ko) * 2003-02-22 2004-12-03 삼성전자주식회사 블록 캐리 전파 즉시 합산 값을 출력하는 한 위상내 자체동기 캐리 룩어헤드 애더 및 그 합산 방법
US7313585B2 (en) * 2003-08-30 2007-12-25 Hewlett-Packard Development Company, L.P. Multiplier circuit
US20090063609A1 (en) * 2007-06-08 2009-03-05 Honkai Tam Static 4:2 Compressor with Fast Sum and Carryout
US8868634B2 (en) * 2011-12-02 2014-10-21 Advanced Micro Devices, Inc. Method and apparatus for performing multiplication in a processor
CN116931873B (zh) * 2023-09-11 2023-11-28 安徽大学 两字节乘法电路及其任意位宽为2次幂的乘法电路与芯片

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4622648A (en) * 1982-05-10 1986-11-11 American Microsystems, Inc. Combinational logic structure using PASS transistors
US4556948A (en) * 1982-12-15 1985-12-03 International Business Machines Corporation Multiplier speed improvement by skipping carry save adders
BR8602717A (pt) * 1985-09-11 1987-04-14 Sperry Corp Aparelho para efetuar adicao de binarios
US4858168A (en) * 1988-02-16 1989-08-15 American Telephone And Telegraph Company Carry look-ahead technique having a reduced number of logic levels
US4879675A (en) * 1988-02-17 1989-11-07 International Business Machines Corporation Parity generator circuit and method
JPH01244531A (ja) * 1988-03-25 1989-09-28 Fujitsu Ltd 論理回路
US4982357A (en) * 1989-04-28 1991-01-01 International Business Machines Corporation Plural dummy select chain logic synthesis network
DE69131218D1 (de) * 1990-04-02 1999-06-17 Advanced Micro Devices Inc Schnelladdierer mit gemischter Basis
US5040139A (en) * 1990-04-16 1991-08-13 Tran Dzung J Transmission gate multiplexer (TGM) logic circuits and multiplier architectures
US5163020A (en) * 1991-04-15 1992-11-10 Texas Instruments Incorporated High speed BiCMOS conditional sum adder
US5258943A (en) * 1991-12-23 1993-11-02 Intel Corporation Apparatus and method for rounding operands
US5347482A (en) * 1992-12-14 1994-09-13 Hal Computer Systems, Inc. Multiplier tree using nine-to-three adders
US5608741A (en) * 1993-11-23 1997-03-04 Intel Corporation Fast parity generator using complement pass-transistor logic
US5511016A (en) * 1994-11-30 1996-04-23 International Business Machines Corporation Method for store rounding and circuit therefor
US5671171A (en) * 1995-07-05 1997-09-23 Sun Microsystems, Inc. Shared rounding hardware for multiplier and divider/square root unit using conditional sum adder

Also Published As

Publication number Publication date
US6012079A (en) 2000-01-04
EP0849663A3 (de) 1999-06-09
DE69726248T2 (de) 2004-09-02
JPH10187418A (ja) 1998-07-21
KR100224278B1 (ko) 1999-10-15
KR19980048830A (ko) 1998-09-15
JP3765658B2 (ja) 2006-04-12
EP0849663A2 (de) 1998-06-24
EP0849663B1 (de) 2003-11-19

Similar Documents

Publication Publication Date Title
DE69802540T2 (de) System mit bedingtem zugang
DE69525170T2 (de) System mit bedingtem zugang
DE69300878T2 (de) Reinigungsmittel.
DE9408502U1 (de) Zusammenklappbarer Spültisch
FI960090A0 (fi) Naetadapter samt dataoeverfoeringsfoerfarande i mobiltelenaet
DE69522158T2 (de) Skalierung von Binärbildern
TR199601066A2 (tr) Metakrilat recine harmanlari.
DE69726248D1 (de) Addierer mit bedingter Summe unter Benutzung von Durchlasstransistor-Logik
ITTO940058A0 (it) Macchina di lavaggio con controllo dell'impianto di detersivo, e rela-tivo metodo di controllo.
FI953012A0 (fi) Telekommunikationssystem samt samtalsuppkopplingsfoerfarande
DE69637688D1 (de) Mit mehreren Entwicklerförderern ausgestattetes Entwicklergerät
DE69604024D1 (de) Haustiergarten
FR2705527B1 (fr) ÓOEillères pour gallinacée.
KR970001937U (ko) 플라스틱 물꼬
DE9321146U1 (de) Zusammenlegbarer Wäscheständer
ES1031096Y (es) Ducha antivandalica.
DE9308222U1 (de) Abfallkorb
KR950006430U (ko) 빨래판
MA22976A1 (fr) Bassine frottoir.
ES1041577Y (es) Bañera especial basculante.
DE9308543U1 (de) Zusammenlegbarer Wäscheständer
KR960034940U (ko) 오폐수이송용 펌프
DE9316363U1 (de) Wäscheständer
ES1026775Y (es) Cubeta desmontable.
KR950003077U (ko) 밀착수단이 구비된 부항기

Legal Events

Date Code Title Description
8364 No opposition during term of opposition