DE69131218D1 - Schnelladdierer mit gemischter Basis - Google Patents
Schnelladdierer mit gemischter BasisInfo
- Publication number
- DE69131218D1 DE69131218D1 DE69131218T DE69131218T DE69131218D1 DE 69131218 D1 DE69131218 D1 DE 69131218D1 DE 69131218 T DE69131218 T DE 69131218T DE 69131218 T DE69131218 T DE 69131218T DE 69131218 D1 DE69131218 D1 DE 69131218D1
- Authority
- DE
- Germany
- Prior art keywords
- independent
- adder
- mixed
- adders
- producing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
- G06F7/507—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using selection between two conditionally calculated carry or sum values
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/49—Computations with a radix, other than binary, 8, 16 or decimal, e.g. ternary, negative or imaginary radices, mixed radix non-linear PCM
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US50381890A | 1990-04-02 | 1990-04-02 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE69131218D1 true DE69131218D1 (de) | 1999-06-17 |
Family
ID=24003637
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69131218T Expired - Lifetime DE69131218D1 (de) | 1990-04-02 | 1991-02-20 | Schnelladdierer mit gemischter Basis |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0450752B1 (de) |
JP (1) | JPH04227533A (de) |
AT (1) | ATE180068T1 (de) |
DE (1) | DE69131218D1 (de) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ES2071556B1 (es) * | 1992-12-31 | 1996-01-16 | Alcatel Standard Electrica | Dispositivo de reduccion del numero de palabras de datos en operaciones aritmeticas binarias. |
KR100224278B1 (ko) * | 1996-12-18 | 1999-10-15 | 윤종용 | 패스 트랜지스터 로직을 사용하는 조건 합 가산기 및 그것을 구비한 집적 회로 |
JP2010122741A (ja) * | 2008-11-17 | 2010-06-03 | Kumamoto Univ | データ処理装置 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3993891A (en) * | 1975-07-03 | 1976-11-23 | Burroughs Corporation | High speed parallel digital adder employing conditional and look-ahead approaches |
JPH01244531A (ja) * | 1988-03-25 | 1989-09-28 | Fujitsu Ltd | 論理回路 |
-
1991
- 1991-02-20 DE DE69131218T patent/DE69131218D1/de not_active Expired - Lifetime
- 1991-02-20 EP EP91301348A patent/EP0450752B1/de not_active Expired - Lifetime
- 1991-02-20 AT AT91301348T patent/ATE180068T1/de not_active IP Right Cessation
- 1991-04-01 JP JP3068498A patent/JPH04227533A/ja not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
EP0450752A3 (en) | 1993-05-26 |
EP0450752A2 (de) | 1991-10-09 |
EP0450752B1 (de) | 1999-05-12 |
ATE180068T1 (de) | 1999-05-15 |
JPH04227533A (ja) | 1992-08-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE3274407D1 (en) | Method and circuit for contrast enhancement | |
EP0615212A3 (de) | Verfahren zur Postverarbeitung mit hoher Geschwindigkeit. | |
IT1208687B (it) | Macchina e metodo di imballaggio ad alta velocita' con camera di evacuazione | |
EP0265184A3 (en) | Opaque polymer film laminates | |
DE69425363D1 (de) | Signalverarbeitungsapparat mit PLL-Schaltungen | |
JPS52127134A (en) | Data processing unit | |
DE69033965D1 (de) | Multiprozessorsystem mit mehrfachen Befehlsquellen | |
EP0026233A4 (de) | Integrierte halbleiterschaltung und verdrahtungsverfahren dafür. | |
JPS56147260A (en) | Lsi for digital signal processing | |
DE69131218D1 (de) | Schnelladdierer mit gemischter Basis | |
EP0452904A3 (en) | Information processing system for determining process based on specified output specification | |
CA2055037A1 (en) | Arbitration circuit for a multimedia system | |
DE69026648T2 (de) | Differenzverstärkerschaltung mit hoher Betriebsgeschwindigkeit | |
DE69112677T2 (de) | Anzapfverstärkungsregulierungsschaltung mit hoher Geschwindigkeit in einem adaptiven Filter. | |
EP0467504A3 (en) | Data processing apparatus having an anti-lockout circuit | |
IT1285852B1 (it) | Circuito di pilotaggio ad alta velocita' di sorgenti ottiche realizzato in tecnologia cmos. | |
CA2055144A1 (en) | Vector calculation apparatus capable of rapidly carrying out vector calculation of two input vectors | |
DE69213026T2 (de) | Digitaler addierer mit hohem geschwindigkeitsnachrichtenweg bei niedrigem kapazitäts - "carry bypass". | |
JPS526073A (en) | Magnetic field type electronic lens | |
FR2653628B3 (fr) | Procede et circuit pour modifier la position d'une image de dessin anime de structure numerique. | |
JPS52140241A (en) | Binary #-digit addition circuit | |
IT8819991A0 (it) | Stadio ad alta resistenza d'uscita in tecnologia mos, particolarmente per circuiti integrati. | |
JPS6465628A (en) | Digital operation deciding circuit | |
NO930934D0 (no) | Databehandling med fordelte regneenheter | |
CA2078636A1 (en) | Demodulator for continuously and accurately carrying out demodulating operation by a frequency multiplication method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8332 | No legal effect for de |