DE69722448D1 - Netzvermittlung mit arbitrierungssystem - Google Patents

Netzvermittlung mit arbitrierungssystem

Info

Publication number
DE69722448D1
DE69722448D1 DE69722448T DE69722448T DE69722448D1 DE 69722448 D1 DE69722448 D1 DE 69722448D1 DE 69722448 T DE69722448 T DE 69722448T DE 69722448 T DE69722448 T DE 69722448T DE 69722448 D1 DE69722448 D1 DE 69722448D1
Authority
DE
Germany
Prior art keywords
networking
arbitration system
arbitration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69722448T
Other languages
English (en)
Other versions
DE69722448T2 (de
Inventor
Ger-Chih Chou
Blair Dahlgren
Wen-Jai Hsieh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor Corp filed Critical Fairchild Semiconductor Corp
Publication of DE69722448D1 publication Critical patent/DE69722448D1/de
Application granted granted Critical
Publication of DE69722448T2 publication Critical patent/DE69722448T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
    • H04L49/254—Centralised controller, i.e. arbitration or scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks
    • H04L12/427—Loop networks with decentralised control
    • H04L12/433—Loop networks with decentralised control with asynchronous transmission, e.g. token ring, register insertion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/35—Switches specially adapted for specific applications
    • H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S370/00—Multiplex communications
    • Y10S370/908—Local area network
    • Y10S370/909—Token ring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Small-Scale Networks (AREA)
DE69722448T 1996-03-25 1997-03-18 Netzvermittlung mit arbitrierungssystem Expired - Fee Related DE69722448T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/621,422 US5689644A (en) 1996-03-25 1996-03-25 Network switch with arbitration sytem
US621422 1996-03-25
PCT/US1997/004250 WO1997036242A1 (en) 1996-03-25 1997-03-18 Network switch with arbitration system

Publications (2)

Publication Number Publication Date
DE69722448D1 true DE69722448D1 (de) 2003-07-03
DE69722448T2 DE69722448T2 (de) 2004-04-08

Family

ID=24490128

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69722448T Expired - Fee Related DE69722448T2 (de) 1996-03-25 1997-03-18 Netzvermittlung mit arbitrierungssystem

Country Status (5)

Country Link
US (1) US5689644A (de)
EP (1) EP0954792B1 (de)
JP (1) JP3852953B2 (de)
DE (1) DE69722448T2 (de)
WO (1) WO1997036242A1 (de)

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US6865154B1 (en) 1998-01-12 2005-03-08 Enterasys Networks, Inc. Method and apparatus for providing bandwidth and delay guarantees in combined input-output buffered crossbar switches that implement work-conserving arbitration algorithms
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US6757246B2 (en) 2001-08-14 2004-06-29 Pts Corporation Method and apparatus for weighted arbitration scheduling separately at the input ports and the output ports of a switch fabric
US6990072B2 (en) * 2001-08-14 2006-01-24 Pts Corporation Method and apparatus for arbitration scheduling with a penalty for a switch fabric
US6804245B2 (en) 2001-08-17 2004-10-12 Mcdata Corporation Compact, shared route lookup table for a fiber channel switch
US7295555B2 (en) 2002-03-08 2007-11-13 Broadcom Corporation System and method for identifying upper layer protocol message boundaries
US7934021B2 (en) 2002-08-29 2011-04-26 Broadcom Corporation System and method for network interfacing
US7346701B2 (en) 2002-08-30 2008-03-18 Broadcom Corporation System and method for TCP offload
US7313623B2 (en) 2002-08-30 2007-12-25 Broadcom Corporation System and method for TCP/IP offload independent of bandwidth delay product
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US8180928B2 (en) 2002-08-30 2012-05-15 Broadcom Corporation Method and system for supporting read operations with CRC for iSCSI and iSCSI chimney
US20040057377A1 (en) * 2002-09-10 2004-03-25 John Tinney Routing patterns for avoiding congestion in networks that convert between circuit-switched and packet-switched traffic
US6799304B2 (en) * 2002-10-01 2004-09-28 Lsi Logic Corporation Arbitration within a multiport AMBA slave
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US7249178B2 (en) * 2003-03-28 2007-07-24 International Business Machines Corporation Non-intrusive recursive dispatching of nested service collections for aggregating web services
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US8549207B2 (en) * 2009-02-13 2013-10-01 The Regents Of The University Of Michigan Crossbar circuitry for applying an adaptive priority scheme and method of operation of such crossbar circuitry
US8230152B2 (en) * 2009-02-13 2012-07-24 The Regents Of The University Of Michigan Crossbar circuitry and method of operation of such crossbar circuitry
JP5208080B2 (ja) * 2009-09-28 2013-06-12 三菱電機株式会社 シーケンス制御回路及び制御回路
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US8984206B2 (en) 2012-10-31 2015-03-17 International Business Machines Corporation Weightage-based scheduling for hierarchical switching fabrics
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US8902899B2 (en) * 2013-02-08 2014-12-02 International Business Machines Corporation Input buffered switching device including bypass logic
US9467396B2 (en) 2014-04-11 2016-10-11 International Business Machines Corporation Simultaneous transfers from a single input link to multiple output links with a timesliced crossbar
US10073939B2 (en) 2015-11-04 2018-09-11 Chronos Tech Llc System and method for application specific integrated circuit design
US9977853B2 (en) 2015-11-04 2018-05-22 Chronos Tech Llc Application specific integrated circuit link
US11550982B2 (en) 2015-11-04 2023-01-10 Chronos Tech Llc Application specific integrated circuit interconnect
US10181939B2 (en) 2016-07-08 2019-01-15 Chronos Tech Llc Systems and methods for the design and implementation of an input and output ports for circuit design
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Also Published As

Publication number Publication date
EP0954792A4 (de) 1999-11-10
EP0954792A1 (de) 1999-11-10
US5689644A (en) 1997-11-18
EP0954792B1 (de) 2003-05-28
WO1997036242A1 (en) 1997-10-02
JP2001500324A (ja) 2001-01-09
DE69722448T2 (de) 2004-04-08
JP3852953B2 (ja) 2006-12-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee