DE69710842D1 - Verfahren und Einrichtung zur Ruhestrombestimmung - Google Patents

Verfahren und Einrichtung zur Ruhestrombestimmung

Info

Publication number
DE69710842D1
DE69710842D1 DE69710842T DE69710842T DE69710842D1 DE 69710842 D1 DE69710842 D1 DE 69710842D1 DE 69710842 T DE69710842 T DE 69710842T DE 69710842 T DE69710842 T DE 69710842T DE 69710842 D1 DE69710842 D1 DE 69710842D1
Authority
DE
Germany
Prior art keywords
determining
quiescent current
quiescent
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69710842T
Other languages
English (en)
Other versions
DE69710842T2 (de
Inventor
Charles Allen Brown
Don R Wiseman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Avago Technologies International Sales Pte Ltd
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of DE69710842D1 publication Critical patent/DE69710842D1/de
Application granted granted Critical
Publication of DE69710842T2 publication Critical patent/DE69710842T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3004—Current or voltage test
    • G01R31/3008—Quiescent current [IDDQ] test or leakage current test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3004—Current or voltage test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE69710842T 1996-10-30 1997-10-08 Verfahren und Einrichtung zur Ruhestrombestimmung Expired - Fee Related DE69710842T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/741,879 US5789933A (en) 1996-10-30 1996-10-30 Method and apparatus for determining IDDQ

Publications (2)

Publication Number Publication Date
DE69710842D1 true DE69710842D1 (de) 2002-04-11
DE69710842T2 DE69710842T2 (de) 2002-08-29

Family

ID=24982592

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69710842T Expired - Fee Related DE69710842T2 (de) 1996-10-30 1997-10-08 Verfahren und Einrichtung zur Ruhestrombestimmung

Country Status (4)

Country Link
US (1) US5789933A (de)
EP (1) EP0840227B1 (de)
JP (1) JP2983938B2 (de)
DE (1) DE69710842T2 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6087843A (en) * 1997-07-14 2000-07-11 Credence Systems Corporation Integrated circuit tester with test head including regulating capacitor
DE19836361C1 (de) * 1998-08-11 2000-03-30 Siemens Ag Verfahren zur Leckstromprüfung einer Kontaktierungsstelle einer integrierten Schaltung
US6366108B2 (en) 1998-12-01 2002-04-02 Agilent Technologies, Inc. System and method for detecting defects within an electrical circuit by analyzing quiescent current
US6307376B1 (en) 1998-12-23 2001-10-23 Eaton Corporation Fault detection system and method for solenoid controlled actuators of a transmission system
DE69926126T2 (de) * 1999-09-14 2006-05-11 Stmicroelectronics S.R.L., Agrate Brianza Verfahren zur ruhestrombestimmung
US6810344B1 (en) * 1999-11-11 2004-10-26 Kabushiki Kaisha Toshiba Semiconductor testing method and semiconductor testing apparatus for semiconductor devices, and program for executing semiconductor testing method
US6342790B1 (en) 2000-04-13 2002-01-29 Pmc-Sierra, Inc. High-speed, adaptive IDDQ measurement
US6535005B1 (en) * 2000-04-26 2003-03-18 Emc Corporation Systems and methods for obtaining an electrical characteristics of a circuit board assembly process
US6586921B1 (en) 2000-05-12 2003-07-01 Logicvision, Inc. Method and circuit for testing DC parameters of circuit input and output nodes
US6693439B1 (en) 2000-09-28 2004-02-17 Cadence Design Systems, Inc. Apparatus and methods for measuring noise in a device
US6542385B1 (en) 2000-11-22 2003-04-01 Teradyne, Inc. DUT power supply having improved switching DC-DC converter
US6556034B1 (en) 2000-11-22 2003-04-29 Teradyne, Inc. High speed and high accuracy DUT power supply with active boost circuitry
US6448748B1 (en) 2001-03-01 2002-09-10 Teradyne, Inc. High current and high accuracy linear amplifier
US6623992B1 (en) * 2002-03-08 2003-09-23 Lsi Logic Corporation System and method for determining a subthreshold leakage test limit of an integrated circuit
JP2006500559A (ja) * 2002-09-20 2006-01-05 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ Ｉｄｄｑの判定方法および装置
KR100496861B1 (ko) * 2002-09-26 2005-06-22 삼성전자주식회사 하나의 핸들러에 2개 이상의 테스트 보드를 갖는 테스트장비 및 그 테스트 방법
DE602007006031D1 (de) * 2006-09-06 2010-06-02 Nxp Bv Prüfbare integrierte schaltung und ic-prüfverfahren
US8526252B2 (en) * 2009-03-17 2013-09-03 Seagate Technology Llc Quiescent testing of non-volatile memory array
US9324822B2 (en) * 2014-07-01 2016-04-26 Globalfoundries Inc. Gate dielectric protection for transistors
US11599098B2 (en) 2019-05-08 2023-03-07 Ares Technologies, Inc. Apparatus and methods for testing circuit elements at one or more manufacturing stages

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2285516B (en) * 1994-01-05 1997-07-30 Hewlett Packard Co Quiescent current testing of dynamic logic systems
US5552744A (en) * 1994-08-11 1996-09-03 Ltx Corporation High speed IDDQ monitor circuit
US5519333A (en) * 1994-09-09 1996-05-21 Sandia Corporation Elevated voltage level IDDQ failure testing of integrated circuits

Also Published As

Publication number Publication date
EP0840227A1 (de) 1998-05-06
JPH10142288A (ja) 1998-05-29
EP0840227B1 (de) 2002-03-06
US5789933A (en) 1998-08-04
JP2983938B2 (ja) 1999-11-29
DE69710842T2 (de) 2002-08-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: AVAGO TECHNOLOGIES GENERAL IP ( SINGAPORE) PTE. LT

8328 Change in the person/name/address of the agent

Representative=s name: DILG HAEUSLER SCHINDELMANN PATENTANWALTSGESELLSCHA

8339 Ceased/non-payment of the annual fee