DE69707034D1 - Selbstprüfende und korrigierende Cache-Speicherverwaltung - Google Patents

Selbstprüfende und korrigierende Cache-Speicherverwaltung

Info

Publication number
DE69707034D1
DE69707034D1 DE69707034T DE69707034T DE69707034D1 DE 69707034 D1 DE69707034 D1 DE 69707034D1 DE 69707034 T DE69707034 T DE 69707034T DE 69707034 T DE69707034 T DE 69707034T DE 69707034 D1 DE69707034 D1 DE 69707034D1
Authority
DE
Germany
Prior art keywords
checking
self
cache management
correcting cache
correcting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69707034T
Other languages
English (en)
Other versions
DE69707034T2 (de
Inventor
Billy J Fuller
Dale R Passmore
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of DE69707034D1 publication Critical patent/DE69707034D1/de
Publication of DE69707034T2 publication Critical patent/DE69707034T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
    • G06F11/141—Saving, restoring, recovering or retrying at machine instruction level for bus or memory accesses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69707034T 1996-03-08 1997-03-03 Selbstprüfende und korrigierende Cache-Speicherverwaltung Expired - Fee Related DE69707034T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/612,754 US5893152A (en) 1996-03-08 1996-03-08 Method and apparatus that detects and tolerates inconsistencies between the cache and main memory, and the translation lookaside buffer and the virtual memory page table in main memory

Publications (2)

Publication Number Publication Date
DE69707034D1 true DE69707034D1 (de) 2001-11-08
DE69707034T2 DE69707034T2 (de) 2002-06-27

Family

ID=24454523

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69707034T Expired - Fee Related DE69707034T2 (de) 1996-03-08 1997-03-03 Selbstprüfende und korrigierende Cache-Speicherverwaltung

Country Status (4)

Country Link
US (2) US5893152A (de)
EP (1) EP0794494B1 (de)
JP (1) JPH1021141A (de)
DE (1) DE69707034T2 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5893152A (en) * 1996-03-08 1999-04-06 Sun Microsystems, Inc. Method and apparatus that detects and tolerates inconsistencies between the cache and main memory, and the translation lookaside buffer and the virtual memory page table in main memory
DE19737182A1 (de) * 1997-08-26 1999-03-04 Bosch Gmbh Robert Verfahren zum Ändern von Daten
US6901540B1 (en) * 1999-11-08 2005-05-31 International Business Machines Corporation TLB parity error recovery
US6671792B1 (en) * 2000-04-28 2003-12-30 Hewlett-Packard Development Company, L.P. Share masks and alias for directory coherency
US6658592B1 (en) * 2000-07-20 2003-12-02 Emc Corporation Error detection in disk storage systems
DE10340861A1 (de) * 2003-09-04 2005-04-07 Infineon Technologies Ag Prozessorschaltung und Verfahren zum Zuordnen eines Logikchips zu einem Speicherchip
WO2005073992A1 (en) * 2004-01-30 2005-08-11 Abb Technology Ltd. Condition monitor for an electrical distribution device
US7234038B1 (en) * 2004-05-28 2007-06-19 Sun Microsystems, Inc. Page mapping cookies
US7555628B2 (en) * 2006-08-15 2009-06-30 Intel Corporation Synchronizing a translation lookaside buffer to an extended paging table
KR100858237B1 (ko) 2006-11-07 2008-09-12 주식회사 안철수연구소 Ｔｌｂ를 이용한 메모리 접근 제어 방법
US7895404B2 (en) * 2008-02-14 2011-02-22 Atmel Rousset S.A.S. Access rights on a memory map
CN101615145B (zh) * 2009-07-24 2011-12-07 中兴通讯股份有限公司 一种提高存储器数据缓存可靠性的方法和装置
US9513843B2 (en) 2010-04-13 2016-12-06 Dot Hill Systems Corporation Method and apparatus for choosing storage components within a tier
US9223663B2 (en) * 2012-06-22 2015-12-29 International Business Machines Corporation Resolving memory faults with reduced processing impact
US8990542B2 (en) * 2012-09-12 2015-03-24 Dot Hill Systems Corporation Efficient metadata protection system for data storage
US9684606B2 (en) 2014-11-14 2017-06-20 Cavium, Inc. Translation lookaside buffer invalidation suppression
US9697137B2 (en) * 2014-11-14 2017-07-04 Cavium, Inc. Filtering translation lookaside buffer invalidations
US9633155B1 (en) * 2015-11-10 2017-04-25 International Business Machines Corporation Circuit modification
CN109416656B (zh) 2016-10-31 2023-08-11 拉姆伯斯公司 混合存储器模块
JP6579149B2 (ja) * 2017-04-20 2019-09-25 富士通株式会社 ストレージ制御装置、及びストレージ制御プログラム
WO2019074743A1 (en) 2017-10-12 2019-04-18 Rambus Inc. NON-VOLATILE PHYSICAL MEMORY WITH DRAM CACHE MEMORY

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61166653A (ja) * 1985-01-19 1986-07-28 Panafacom Ltd アドレス変換エラー処理方法
US4831622A (en) * 1987-12-22 1989-05-16 Honeywell Bull Inc. Apparatus for forcing a reload from main memory upon cache memory error
US5386527A (en) * 1991-12-27 1995-01-31 Texas Instruments Incorporated Method and system for high-speed virtual-to-physical address translation and cache tag matching
US5355471A (en) * 1992-08-14 1994-10-11 Pyramid Technology Corporation Multiprocessor cache coherency tester that exercises the coherency logic exhaustively and also detects errors in a processor using an automatic CPU sort
US5406504A (en) * 1993-06-30 1995-04-11 Digital Equipment Multiprocessor cache examiner and coherency checker
US5497458A (en) * 1993-07-06 1996-03-05 Dell Usa, L.P. Cache testability circuit for embedded diagnostics
JP2665718B2 (ja) * 1993-11-10 1997-10-22 日本電気エンジニアリング株式会社 情報処理装置のキャッシュメモリテスト方法
US5535164A (en) * 1995-03-03 1996-07-09 International Business Machines Corporation BIST tester for multiple memories
US5692153A (en) * 1995-03-16 1997-11-25 International Business Machines Corporation Method and system for verifying execution order within a multiprocessor data processing system
US5751740A (en) * 1995-12-14 1998-05-12 Gorca Memory Systems Error detection and correction system for use with address translation memory controller
US5893152A (en) * 1996-03-08 1999-04-06 Sun Microsystems, Inc. Method and apparatus that detects and tolerates inconsistencies between the cache and main memory, and the translation lookaside buffer and the virtual memory page table in main memory

Also Published As

Publication number Publication date
JPH1021141A (ja) 1998-01-23
US6032230A (en) 2000-02-29
EP0794494A3 (de) 1997-11-19
DE69707034T2 (de) 2002-06-27
US5893152A (en) 1999-04-06
EP0794494B1 (de) 2001-10-04
EP0794494A2 (de) 1997-09-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee