DE69635881D1 - VLIW-Befehlsprozessor mit variabler Wortlänge - Google Patents
VLIW-Befehlsprozessor mit variabler WortlängeInfo
- Publication number
- DE69635881D1 DE69635881D1 DE69635881T DE69635881T DE69635881D1 DE 69635881 D1 DE69635881 D1 DE 69635881D1 DE 69635881 T DE69635881 T DE 69635881T DE 69635881 T DE69635881 T DE 69635881T DE 69635881 D1 DE69635881 D1 DE 69635881D1
- Authority
- DE
- Germany
- Prior art keywords
- vliw
- word length
- command processor
- variable word
- length command
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26515195 | 1995-10-13 | ||
JP26515195 | 1995-10-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69635881D1 true DE69635881D1 (de) | 2006-05-04 |
DE69635881T2 DE69635881T2 (de) | 2006-08-10 |
Family
ID=17413346
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69635881T Expired - Fee Related DE69635881T2 (de) | 1995-10-13 | 1996-10-11 | VLIW-Befehlsprozessor mit variabler Wortlänge |
Country Status (3)
Country | Link |
---|---|
US (1) | US5774737A (de) |
EP (1) | EP0768602B1 (de) |
DE (1) | DE69635881T2 (de) |
Families Citing this family (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5898865A (en) * | 1997-06-12 | 1999-04-27 | Advanced Micro Devices, Inc. | Apparatus and method for predicting an end of loop for string instructions |
JP3790607B2 (ja) * | 1997-06-16 | 2006-06-28 | 松下電器産業株式会社 | Vliwプロセッサ |
US6032252A (en) * | 1997-10-28 | 2000-02-29 | Advanced Micro Devices, Inc. | Apparatus and method for efficient loop control in a superscalar microprocessor |
US5974537A (en) * | 1997-12-29 | 1999-10-26 | Philips Electronics North America Corporation | Guard bits in a VLIW instruction control routing of operations to functional units allowing two issue slots to specify the same functional unit |
FR2773234B1 (fr) * | 1997-12-31 | 2003-07-25 | Sgs Thomson Microelectronics | Memoire a double acces pour processeur de signal numerique |
US6081884A (en) * | 1998-01-05 | 2000-06-27 | Advanced Micro Devices, Inc. | Embedding two different instruction sets within a single long instruction word using predecode bits |
EP0942357A3 (de) * | 1998-03-11 | 2000-03-22 | Matsushita Electric Industrial Co., Ltd. | Mit einer Mehrzahl von Befehlsformaten vereinbarer Datenprozessor |
EP0947922B1 (de) * | 1998-04-01 | 2006-09-27 | Matsushita Electric Industrial Co., Ltd. | Kompiler |
US6356994B1 (en) * | 1998-07-09 | 2002-03-12 | Bops, Incorporated | Methods and apparatus for instruction addressing in indirect VLIW processors |
US6192465B1 (en) * | 1998-09-21 | 2001-02-20 | Advanced Micro Devices, Inc. | Using multiple decoders and a reorder queue to decode instructions out of order |
US6311262B1 (en) | 1999-01-18 | 2001-10-30 | Infineon Technologies Ag | Apparatus for the hierarchical and distributed control of programmable modules in large-scale integrated systems |
US6453407B1 (en) * | 1999-02-10 | 2002-09-17 | Infineon Technologies Ag | Configurable long instruction word architecture and instruction set |
US7366876B1 (en) * | 2000-10-31 | 2008-04-29 | Analog Devices, Inc. | Efficient emulation instruction dispatch based on instruction width |
US6836839B2 (en) | 2001-03-22 | 2004-12-28 | Quicksilver Technology, Inc. | Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements |
US20040133745A1 (en) | 2002-10-28 | 2004-07-08 | Quicksilver Technology, Inc. | Adaptable datapath for a digital processing system |
US7752419B1 (en) | 2001-03-22 | 2010-07-06 | Qst Holdings, Llc | Method and system for managing hardware resources to implement system functions using an adaptive computing architecture |
US7653710B2 (en) | 2002-06-25 | 2010-01-26 | Qst Holdings, Llc. | Hardware task manager |
US7962716B2 (en) | 2001-03-22 | 2011-06-14 | Qst Holdings, Inc. | Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements |
US6577678B2 (en) | 2001-05-08 | 2003-06-10 | Quicksilver Technology | Method and system for reconfigurable channel coding |
US20030023830A1 (en) * | 2001-07-25 | 2003-01-30 | Hogenauer Eugene B. | Method and system for encoding instructions for a VLIW that reduces instruction memory requirements |
US7046635B2 (en) | 2001-11-28 | 2006-05-16 | Quicksilver Technology, Inc. | System for authorizing functionality in adaptable hardware devices |
US8412915B2 (en) | 2001-11-30 | 2013-04-02 | Altera Corporation | Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements |
US6986021B2 (en) | 2001-11-30 | 2006-01-10 | Quick Silver Technology, Inc. | Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements |
US7215701B2 (en) | 2001-12-12 | 2007-05-08 | Sharad Sambhwani | Low I/O bandwidth method and system for implementing detection and identification of scrambling codes |
US7403981B2 (en) | 2002-01-04 | 2008-07-22 | Quicksilver Technology, Inc. | Apparatus and method for adaptive multimedia reception and transmission in communication environments |
US7328414B1 (en) | 2003-05-13 | 2008-02-05 | Qst Holdings, Llc | Method and system for creating and programming an adaptive computing engine |
US7660984B1 (en) | 2003-05-13 | 2010-02-09 | Quicksilver Technology | Method and system for achieving individualized protected space in an operating system |
JP3738842B2 (ja) * | 2002-06-04 | 2006-01-25 | 富士通株式会社 | 遅延分岐機能を備えた情報処理装置 |
EP1378824A1 (de) * | 2002-07-02 | 2004-01-07 | STMicroelectronics S.r.l. | Verfahren zur Ausführung von Programmen in einem Mehrprozessorsystem, und entsprechenes Prozessorsystem |
WO2004015561A1 (en) * | 2002-08-05 | 2004-02-19 | Koninklijke Philips Electronics N.V. | Processor and method for processing vliw instructions |
US8108656B2 (en) | 2002-08-29 | 2012-01-31 | Qst Holdings, Llc | Task definition for specifying resource requirements |
SE0202770D0 (sv) * | 2002-09-18 | 2002-09-18 | Coding Technologies Sweden Ab | Method for reduction of aliasing introduces by spectral envelope adjustment in real-valued filterbanks |
US8364935B2 (en) * | 2002-10-11 | 2013-01-29 | Nytell Software LLC | Data processing apparatus address range dependent parallelization of instructions |
US7937591B1 (en) | 2002-10-25 | 2011-05-03 | Qst Holdings, Llc | Method and system for providing a device which can be adapted on an ongoing basis |
US8276135B2 (en) | 2002-11-07 | 2012-09-25 | Qst Holdings Llc | Profiling of software and circuit designs utilizing data operation analyses |
US7225301B2 (en) | 2002-11-22 | 2007-05-29 | Quicksilver Technologies | External memory controller node |
EP1622009A1 (de) * | 2004-07-27 | 2006-02-01 | Texas Instruments Incorporated | JSM-Architektur und Systeme |
US7526633B2 (en) * | 2005-03-23 | 2009-04-28 | Qualcomm Incorporated | Method and system for encoding variable length packets with variable instruction sizes |
CN102707929A (zh) * | 2012-04-12 | 2012-10-03 | 江苏中科芯核电子科技有限公司 | 一种并行指令打包方法 |
CN102855120B (zh) * | 2012-09-14 | 2014-11-26 | 北京中科晶上科技有限公司 | 超长指令字vliw的处理器和处理方法 |
US11204768B2 (en) | 2019-11-06 | 2021-12-21 | Onnivation Llc | Instruction length based parallel instruction demarcator |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5241636A (en) * | 1990-02-14 | 1993-08-31 | Intel Corporation | Method for parallel instruction execution in a computer |
EP0474297B1 (de) * | 1990-09-05 | 1998-06-10 | Koninklijke Philips Electronics N.V. | Maschine mit sehr langem Befehlswort für leistungsfähige Durchführung von Programmen mit bedingten Verzweigungen |
EP0551090B1 (de) * | 1992-01-06 | 1999-08-04 | Hitachi, Ltd. | Rechner mit einer Parallelverarbeitungsfähigkeit |
JPH05233281A (ja) * | 1992-02-21 | 1993-09-10 | Toshiba Corp | 電子計算機 |
WO1994027216A1 (en) * | 1993-05-14 | 1994-11-24 | Massachusetts Institute Of Technology | Multiprocessor coupling system with integrated compile and run time scheduling for parallelism |
US5634025A (en) * | 1993-12-09 | 1997-05-27 | International Business Machines Corporation | Method and system for efficiently fetching variable-width instructions in a data processing system having multiple prefetch units |
US5664135A (en) * | 1994-09-28 | 1997-09-02 | Hewlett-Packard Company | Apparatus and method for reducing delays due to branches |
US5600810A (en) * | 1994-12-09 | 1997-02-04 | Mitsubishi Electric Information Technology Center America, Inc. | Scaleable very long instruction word processor with parallelism matching |
US5649135A (en) * | 1995-01-17 | 1997-07-15 | International Business Machines Corporation | Parallel processing system and method using surrogate instructions |
-
1996
- 1996-10-10 US US08/745,336 patent/US5774737A/en not_active Expired - Fee Related
- 1996-10-11 EP EP96116340A patent/EP0768602B1/de not_active Expired - Lifetime
- 1996-10-11 DE DE69635881T patent/DE69635881T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0768602A3 (de) | 2004-07-28 |
EP0768602B1 (de) | 2006-03-08 |
US5774737A (en) | 1998-06-30 |
EP0768602A2 (de) | 1997-04-16 |
DE69635881T2 (de) | 2006-08-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: PANASONIC CORP., KADOMA, OSAKA, JP |
|
8339 | Ceased/non-payment of the annual fee |