DE69634525D1 - Videoprozessor - Google Patents
VideoprozessorInfo
- Publication number
- DE69634525D1 DE69634525D1 DE69634525T DE69634525T DE69634525D1 DE 69634525 D1 DE69634525 D1 DE 69634525D1 DE 69634525 T DE69634525 T DE 69634525T DE 69634525 T DE69634525 T DE 69634525T DE 69634525 D1 DE69634525 D1 DE 69634525D1
- Authority
- DE
- Germany
- Prior art keywords
- video processor
- video
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
- G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
- G06F15/7864—Architectures of general purpose stored program computers comprising a single central processing unit with memory on more than one IC chip
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3834—Maintaining memory consistency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Image Processing (AREA)
- Controls And Circuits For Display Device (AREA)
- Digital Computer Display Output (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/481,966 US5696985A (en) | 1995-06-07 | 1995-06-07 | Video processor |
Publications (1)
Publication Number | Publication Date |
---|---|
DE69634525D1 true DE69634525D1 (de) | 2005-05-04 |
Family
ID=23914105
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69634525T Expired - Lifetime DE69634525D1 (de) | 1995-06-07 | 1996-05-13 | Videoprozessor |
Country Status (5)
Country | Link |
---|---|
US (1) | US5696985A (de) |
EP (1) | EP0747834B1 (de) |
JP (1) | JP3518788B2 (de) |
KR (1) | KR100218620B1 (de) |
DE (1) | DE69634525D1 (de) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100331437B1 (ko) * | 1995-06-30 | 2002-08-08 | 삼성전자 주식회사 | 디.엠.티.시스템에서적응형비트교환방법및장치 |
JP3372864B2 (ja) * | 1998-04-01 | 2003-02-04 | 日本電気株式会社 | 動画像伸長装置及び方法 |
CN1306697A (zh) * | 1998-06-25 | 2001-08-01 | 赤道技术公司 | 可变长度编码与解码的处理电路和处理方法 |
US6393551B1 (en) * | 1999-05-26 | 2002-05-21 | Infineon Technologies North America Corp. | Reducing instruction transactions in a microprocessor |
US7039906B1 (en) * | 2000-09-29 | 2006-05-02 | International Business Machines Corporation | Compiler for enabling multiple signed independent data elements per register |
US6895520B1 (en) | 2001-03-02 | 2005-05-17 | Advanced Micro Devices, Inc. | Performance and power optimization via block oriented performance measurement and control |
US8401084B2 (en) * | 2002-04-01 | 2013-03-19 | Broadcom Corporation | System and method for multi-row decoding of video with dependent rows |
US7392368B2 (en) * | 2002-08-09 | 2008-06-24 | Marvell International Ltd. | Cross multiply and add instruction and multiply and subtract instruction SIMD execution on real and imaginary components of a plurality of complex data elements |
AU2003256870A1 (en) | 2002-08-09 | 2004-02-25 | Intel Corporation | Multimedia coprocessor control mechanism including alignment or broadcast instructions |
US6986023B2 (en) * | 2002-08-09 | 2006-01-10 | Intel Corporation | Conditional execution of coprocessor instruction based on main processor arithmetic flags |
CN1757018B (zh) * | 2003-03-06 | 2010-09-08 | Nxp股份有限公司 | 具有预取装置的数据处理系统、数据预取方法 |
US6862027B2 (en) | 2003-06-30 | 2005-03-01 | Microsoft Corp. | System and method for parallel execution of data generation tasks |
US20060088799A1 (en) * | 2004-08-02 | 2006-04-27 | William Dorfman | Dental impression trays |
US20060267998A1 (en) * | 2005-05-24 | 2006-11-30 | Walls Jeffrey J | Systems and methods for management of parameters in a multi-node graphics system |
US7366842B1 (en) * | 2005-12-15 | 2008-04-29 | Nvidia Corporation | Creating permanent storage on the fly within existing buffers |
WO2008006400A1 (en) * | 2006-07-11 | 2008-01-17 | Freescale Semiconductor, Inc. | Microprocessor and method for register addressing therein |
US8487947B2 (en) * | 2006-09-28 | 2013-07-16 | Agere Systems Inc. | Video processing architecture having reduced memory requirement |
JP6396715B2 (ja) * | 2014-08-07 | 2018-09-26 | ルネサスエレクトロニクス株式会社 | データ処理装置 |
US20190303037A1 (en) * | 2018-03-30 | 2019-10-03 | Ca, Inc. | Using sequential read intention to increase data buffer reuse |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR920001287B1 (ko) * | 1988-02-12 | 1992-02-10 | 니혼 호오소오 고오카이 | 디지탈 영상신호 처리장치 |
US5239654A (en) * | 1989-11-17 | 1993-08-24 | Texas Instruments Incorporated | Dual mode SIMD/MIMD processor providing reuse of MIMD instruction memories as data memories when operating in SIMD mode |
EP0429733B1 (de) * | 1989-11-17 | 1999-04-28 | Texas Instruments Incorporated | Multiprozessor mit Koordinatenschalter zwischen Prozessoren und Speichern |
EP0530310A4 (en) * | 1990-05-18 | 1993-07-21 | Star Semiconductor Corporation | Programmable signal processor architecture |
-
1995
- 1995-06-07 US US08/481,966 patent/US5696985A/en not_active Expired - Fee Related
-
1996
- 1996-05-13 DE DE69634525T patent/DE69634525D1/de not_active Expired - Lifetime
- 1996-05-13 EP EP96303354A patent/EP0747834B1/de not_active Expired - Lifetime
- 1996-05-20 JP JP12504096A patent/JP3518788B2/ja not_active Expired - Fee Related
- 1996-05-23 KR KR1019960017794A patent/KR100218620B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JPH0950402A (ja) | 1997-02-18 |
US5696985A (en) | 1997-12-09 |
EP0747834A1 (de) | 1996-12-11 |
JP3518788B2 (ja) | 2004-04-12 |
KR100218620B1 (ko) | 1999-09-01 |
EP0747834B1 (de) | 2005-03-30 |
KR970002600A (ko) | 1997-01-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8332 | No legal effect for de |